1 /* $NetBSD: apcdmareg.h,v 1.6 2008/04/28 20:23:49 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * APC DMA hardware; from SunOS header 34 * Thanks to Derrick J. Brashear for additional info on the 35 * meaning of some of these bits. 36 */ 37 #ifndef _DEV_IC_APCDMAREG_H_ 38 #define _DEV_IC_APCDMAREG_H_ 39 40 struct apc_dma { 41 volatile u_int32_t dmacsr; /* APC CSR */ 42 volatile u_int32_t lpad[3]; /* */ 43 volatile u_int32_t dmacva; /* Capture Virtual Address */ 44 volatile u_int32_t dmacc; /* Capture Count */ 45 volatile u_int32_t dmacnva; /* Capture Next Virtual Address */ 46 volatile u_int32_t dmacnc; /* Capture next count */ 47 volatile u_int32_t dmapva; /* Playback Virtual Address */ 48 volatile u_int32_t dmapc; /* Playback Count */ 49 volatile u_int32_t dmapnva; /* Playback Next VAddress */ 50 volatile u_int32_t dmapnc; /* Playback Next Count */ 51 }; 52 53 /* same as above but as offsets for bus_space ops */ 54 #define APC_DMA_CSR 0 55 #define APC_DMA_CVA 16 56 #define APC_DMA_CC 20 57 #define APC_DMA_CNVA 24 58 #define APC_DMA_CNC 28 59 #define APC_DMA_PVA 32 60 #define APC_DMA_PC 36 61 #define APC_DMA_PNVA 40 62 #define APC_DMA_PNC 44 63 64 #define APC_DMA_SIZE 48 65 66 /* 67 * APC CSR Register bit definitions 68 */ 69 #define APC_IP 0x00800000 /* Interrupt Pending */ 70 #define APC_PI 0x00400000 /* Playback interrupt */ 71 #define APC_CI 0x00200000 /* Capture interrupt */ 72 #define APC_EI 0x00100000 /* General interrupt */ 73 #define APC_IE 0x00080000 /* General ext int. enable */ 74 #define APC_PIE 0x00040000 /* Playback ext intr */ 75 #define APC_CIE 0x00020000 /* Capture ext intr */ 76 #define APC_EIE 0x00010000 /* Error ext intr */ 77 #define APC_PMI 0x00008000 /* Pipe empty interrupt */ 78 #define APC_PM 0x00004000 /* Play pipe empty */ 79 #define APC_PD 0x00002000 /* Playback NVA dirty */ 80 #define APC_PMIE 0x00001000 /* play pipe empty Int enable */ 81 #define APC_CM 0x00000800 /* Cap data dropped on floor */ 82 #define APC_CD 0x00000400 /* Capture NVA dirty */ 83 #define APC_CMI 0x00000200 /* Capture pipe empty interrupt */ 84 #define APC_CMIE 0x00000100 /* Cap. pipe empty int enable */ 85 #define APC_PPAUSE 0x00000080 /* Pause the play DMA */ 86 #define APC_CPAUSE 0x00000040 /* Pause the capture DMA */ 87 #define APC_CODEC_PDN 0x00000020 /* CODEC RESET */ 88 #define PDMA_GO 0x00000008 89 #define CDMA_GO 0x00000004 /* bit 2 of the csr */ 90 #define APC_RESET 0x00000001 /* Reset the chip */ 91 92 #define APC_BITS \ 93 "\20\30IP\27PI\26CI\25EI\24IE" \ 94 "\23PIE\22CIE\21EIE\20PMI\17PM\16PD\15PMIE" \ 95 "\14CM\13CD\12CMI\11CMIE\10PPAUSE\7CPAUSE\6PDN\4PGO\3CGO" 96 97 /* 98 * Note that when we program CSR, we should be careful to not 99 * accidentally clear any pending interrupt bits (a pending interrupt 100 * reads as 1 and writing back 1 will clear), so instead of 101 * 102 * dma->dmacsr |= bits; 103 * 104 * we should do 105 * 106 * temp = dma->dmacsr & ~APC_INTR_MASK; 107 * temp |= bits; 108 * dma->dmacsr = temp; 109 * 110 * When clearing bits, always add APC_INTR_MASK, i.e. 111 * 112 * dma->dmacsr &= ~(bits | APC_INTR_MASK); 113 */ 114 #define APC_INTR_MASK (APC_IP|APC_PI|APC_CI|APC_EI|APC_PMI|APC_CMI) 115 116 #endif /* _DEV_IC_APCDMAREG_H_ */ 117