1 /* $NetBSD: mt2131.c,v 1.7 2019/12/23 18:57:30 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: mt2131.c,v 1.7 2019/12/23 18:57:30 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/kmem.h>
36 #include <sys/syslog.h>
37 #include <sys/proc.h>
38 #include <sys/module.h>
39
40 #include <dev/i2c/mt2131var.h>
41
42 #define PWR 0x07
43 #define UPC_1 0x0b
44 #define AGC_RL 0x10
45 #define MISC_2 0x15
46
47 #define IF1 1220
48 #define IF2 44000
49 #define REF 16000
50
51 static const uint8_t mt2131_initstring[] = {
52 0x01,
53 0x50, 0x00, 0x50, 0x80, 0x00, 0x49,
54 0xfa, 0x88, 0x08, 0x77, 0x41, 0x04, 0x00, 0x00, 0x00, 0x32,
55 0x7f, 0xda, 0x4c, 0x00, 0x10, 0xaa, 0x78, 0x80, 0xff, 0x68,
56 0xa0, 0xff, 0xdd, 0x00, 0x00
57 };
58
59 static const uint8_t mt2131_agcinitstring[] = {
60 AGC_RL,
61 0x7f, 0xc8, 0x0a, 0x5f, 0x00, 0x04
62 };
63
64
65 struct mt2131_softc {
66 device_t parent;
67 i2c_tag_t tag;
68 i2c_addr_t addr;
69 uint32_t frequency;
70 uint32_t bandwidth;
71 };
72
73 static int mt2131_init(struct mt2131_softc *);
74
75 static int mt2131_read(struct mt2131_softc *, uint8_t, uint8_t *);
76 static int mt2131_write(struct mt2131_softc *, uint8_t, uint8_t);
77
78 struct mt2131_softc *
mt2131_open(device_t parent,i2c_tag_t t,i2c_addr_t a)79 mt2131_open(device_t parent, i2c_tag_t t, i2c_addr_t a)
80 {
81 struct mt2131_softc *sc;
82 int ret;
83 uint8_t cmd, reg;
84
85 cmd = reg = 0;
86
87 /* get id reg */
88 ret = iic_acquire_bus(t, 0);
89 if (ret == 0) {
90 ret = iic_exec(t, I2C_OP_READ_WITH_STOP, a, &cmd, 1, ®, 1,
91 0);
92 iic_release_bus(t, 0);
93 }
94
95 if (ret) {
96 device_printf(parent, "%s(): read fail\n", __func__);
97 return NULL;
98 }
99
100 if ((reg & 0xfe) != 0x3e) {
101 device_printf(parent, "%s(): chip id %02x unknown\n",
102 __func__, reg);
103 return NULL;
104 }
105
106 sc = kmem_alloc(sizeof(*sc), KM_SLEEP);
107 sc->parent = parent;
108 sc->tag = t;
109 sc->addr = a;
110
111 mt2131_init(sc);
112
113 return sc;
114 }
115
116 void
mt2131_close(struct mt2131_softc * sc)117 mt2131_close(struct mt2131_softc *sc)
118 {
119 kmem_free(sc, sizeof(*sc));
120 }
121
122 int
mt2131_tune_dtv(struct mt2131_softc * sc,const struct dvb_frontend_parameters * p)123 mt2131_tune_dtv(struct mt2131_softc *sc, const struct dvb_frontend_parameters *p)
124 {
125 int rv, i;
126 uint64_t o1, o2;
127 uint64_t d1, d2;
128 uint32_t r1, r2;
129 uint32_t fr;
130 uint8_t b[7];
131 uint8_t regval;
132
133 mt2131_init(sc);
134
135 b[0] = 0x01;
136
137 if(p->frequency != 0 &&
138 (p->frequency < 50000000 || p->frequency > 1000000000))
139 return EINVAL;
140
141 fr = p->frequency / 1000;
142
143 o1 = fr + IF1 * 1000;
144 o2 = o1 - fr - IF2;
145
146 d1 = (o1 * 8192)/REF;
147 d2 = (o2 * 8192)/REF;
148
149 r1 = d1/8192;
150 r2 = d2/8192;
151
152 b[1] = (d1 & 0x1fe0) >> 5;
153 b[2] = (d1 & 0x001f);
154 b[3] = r1;
155 b[4] = (d2 & 0x1fe0) >> 5;
156 b[5] = (d2 & 0x001f);
157 b[6] = r2;
158
159 rv = iic_acquire_bus(sc->tag, 0);
160 if (rv == 0) {
161 rv = iic_exec(sc->tag, I2C_OP_WRITE_WITH_STOP, sc->addr, b, 7,
162 NULL, 0, 0);
163 iic_release_bus(sc->tag, 0);
164 }
165
166 regval = (fr - 27501) / 55000;
167
168 if(regval > 0x13)
169 regval = 0x13;
170
171 rv = mt2131_write(sc, UPC_1, regval);
172
173 if (rv != 0)
174 device_printf(sc->parent, "%s write failed\n", __func__);
175
176 sc->frequency = (o1 - o2 - IF2) * 1000;
177
178 for (i = 0; i < 100; i++) {
179 kpause("mt2131", true, 1, NULL);
180
181 rv = mt2131_read(sc, 0x08, ®val);
182 if (rv != 0)
183 device_printf(sc->parent, "%s read failed\n", __func__);
184
185 if (( regval & 0x88 ) == 0x88 ) {
186 return 0;
187 }
188 }
189
190 device_printf(sc->parent, "mt2131 not locked, %02x\n", b[1]);
191
192 return rv;
193 }
194
195 static int
mt2131_init(struct mt2131_softc * sc)196 mt2131_init(struct mt2131_softc *sc)
197 {
198 int ret;
199
200 ret = iic_acquire_bus(sc->tag, 0);
201 if (ret)
202 return -1;
203 ret = iic_exec(sc->tag, I2C_OP_WRITE_WITH_STOP, sc->addr,
204 mt2131_initstring, sizeof(mt2131_initstring), NULL, 0, 0);
205 iic_release_bus(sc->tag, 0);
206 if (ret)
207 return -1;
208
209 ret = mt2131_write(sc, UPC_1, 0x09);
210 ret = mt2131_write(sc, MISC_2, 0x47);
211 ret = mt2131_write(sc, PWR, 0xf2);
212 ret = mt2131_write(sc, UPC_1, 0x01);
213
214 ret = iic_acquire_bus(sc->tag, 0);
215 if (ret)
216 return -1;
217 ret = iic_exec(sc->tag, I2C_OP_WRITE_WITH_STOP, sc->addr,
218 mt2131_agcinitstring, sizeof(mt2131_agcinitstring),
219 NULL, 0, 0);
220 iic_release_bus(sc->tag, 0);
221 if (ret)
222 return -1;
223
224 return 0;
225 }
226
227 static int
mt2131_read(struct mt2131_softc * sc,uint8_t r,uint8_t * v)228 mt2131_read(struct mt2131_softc *sc, uint8_t r, uint8_t *v)
229 {
230 int ret;
231
232 ret = iic_acquire_bus(sc->tag, 0);
233 if (ret)
234 return ret;
235 ret = iic_exec(sc->tag, I2C_OP_READ_WITH_STOP, sc->addr,
236 &r, 1, v, 1, 0);
237
238 iic_release_bus(sc->tag, 0);
239
240 return ret;
241 }
242
243 static int
mt2131_write(struct mt2131_softc * sc,uint8_t a,uint8_t v)244 mt2131_write(struct mt2131_softc *sc, uint8_t a, uint8_t v)
245 {
246 int ret;
247 uint8_t b[] = { a, v };
248
249 ret = iic_acquire_bus(sc->tag, 0);
250 if (ret)
251 return ret;
252
253 ret = iic_exec(sc->tag, I2C_OP_READ_WITH_STOP, sc->addr,
254 b, sizeof(b), NULL, 0, 0);
255
256 iic_release_bus(sc->tag, 0);
257
258 return ret;
259 }
260
261 MODULE(MODULE_CLASS_DRIVER, mt2131, "i2cexec");
262
263 static int
mt2131_modcmd(modcmd_t cmd,void * priv)264 mt2131_modcmd(modcmd_t cmd, void *priv)
265 {
266 if (cmd == MODULE_CMD_INIT || cmd == MODULE_CMD_FINI)
267 return 0;
268 return ENOTTY;
269 }
270