1 /* $NetBSD: max6900.c,v 1.19 2025/01/07 17:39:45 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2003 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 #include <sys/cdefs.h>
39 __KERNEL_RCSID(0, "$NetBSD: max6900.c,v 1.19 2025/01/07 17:39:45 andvar Exp $");
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/device.h>
44 #include <sys/kernel.h>
45 #include <sys/fcntl.h>
46 #include <sys/uio.h>
47 #include <sys/conf.h>
48 #include <sys/event.h>
49
50 #include <dev/clock_subr.h>
51
52 #include <dev/i2c/i2cvar.h>
53 #include <dev/i2c/max6900reg.h>
54
55 struct maxrtc_softc {
56 device_t sc_dev;
57 i2c_tag_t sc_tag;
58 int sc_address;
59 int sc_open;
60 struct todr_chip_handle sc_todr;
61 };
62
63 static int maxrtc_match(device_t, cfdata_t, void *);
64 static void maxrtc_attach(device_t, device_t, void *);
65
66 CFATTACH_DECL_NEW(maxrtc, sizeof(struct maxrtc_softc),
67 maxrtc_match, maxrtc_attach, NULL, NULL);
68 extern struct cfdriver maxrtc_cd;
69
70 dev_type_open(maxrtc_open);
71 dev_type_close(maxrtc_close);
72 dev_type_read(maxrtc_read);
73 dev_type_write(maxrtc_write);
74
75 const struct cdevsw maxrtc_cdevsw = {
76 .d_open = maxrtc_open,
77 .d_close = maxrtc_close,
78 .d_read = maxrtc_read,
79 .d_write = maxrtc_write,
80 .d_ioctl = noioctl,
81 .d_stop = nostop,
82 .d_tty = notty,
83 .d_poll = nopoll,
84 .d_mmap = nommap,
85 .d_kqfilter = nokqfilter,
86 .d_discard = nodiscard,
87 .d_flag = D_OTHER
88 };
89
90 static int maxrtc_gettime_ymdhms(struct todr_chip_handle *,
91 struct clock_ymdhms *);
92 static int maxrtc_settime_ymdhms(struct todr_chip_handle *,
93 struct clock_ymdhms *);
94
95 int
maxrtc_match(device_t parent,cfdata_t cf,void * aux)96 maxrtc_match(device_t parent, cfdata_t cf, void *aux)
97 {
98 struct i2c_attach_args *ia = aux;
99
100 if ((ia->ia_addr & MAX6900_ADDRMASK) == MAX6900_ADDR)
101 return (I2C_MATCH_ADDRESS_ONLY);
102
103 return (0);
104 }
105
106 void
maxrtc_attach(device_t parent,device_t self,void * aux)107 maxrtc_attach(device_t parent, device_t self, void *aux)
108 {
109 struct maxrtc_softc *sc = device_private(self);
110 struct i2c_attach_args *ia = aux;
111
112 sc->sc_tag = ia->ia_tag;
113 sc->sc_address = ia->ia_addr;
114 sc->sc_dev = self;
115
116 aprint_naive(": Real-time Clock/NVRAM\n");
117 aprint_normal(": MAX6900 Real-time Clock/NVRAM\n");
118
119 sc->sc_open = 0;
120
121 sc->sc_todr.cookie = sc;
122 sc->sc_todr.todr_gettime = NULL;
123 sc->sc_todr.todr_settime = NULL;
124 sc->sc_todr.todr_gettime_ymdhms = maxrtc_gettime_ymdhms;
125 sc->sc_todr.todr_settime_ymdhms = maxrtc_settime_ymdhms;
126 sc->sc_todr.todr_setwen = NULL;
127
128 todr_attach(&sc->sc_todr);
129 }
130
131 /*ARGSUSED*/
132 int
maxrtc_open(dev_t dev,int flag,int fmt,struct lwp * l)133 maxrtc_open(dev_t dev, int flag, int fmt, struct lwp *l)
134 {
135 struct maxrtc_softc *sc;
136
137 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
138 return (ENXIO);
139
140 /* XXX: Locking */
141
142 if (sc->sc_open)
143 return (EBUSY);
144
145 sc->sc_open = 1;
146 return (0);
147 }
148
149 /*ARGSUSED*/
150 int
maxrtc_close(dev_t dev,int flag,int fmt,struct lwp * l)151 maxrtc_close(dev_t dev, int flag, int fmt, struct lwp *l)
152 {
153 struct maxrtc_softc *sc;
154
155 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
156 return (ENXIO);
157
158 sc->sc_open = 0;
159 return (0);
160 }
161
162 /*ARGSUSED*/
163 int
maxrtc_read(dev_t dev,struct uio * uio,int flags)164 maxrtc_read(dev_t dev, struct uio *uio, int flags)
165 {
166 struct maxrtc_softc *sc;
167 u_int8_t ch, cmdbuf[1];
168 int a, error;
169
170 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
171 return (ENXIO);
172
173 if (uio->uio_offset >= MAX6900_RAM_BYTES)
174 return (EINVAL);
175
176 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
177 return (error);
178
179 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) {
180 a = (int)uio->uio_offset;
181 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_READ;
182 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
183 sc->sc_address, cmdbuf, 1,
184 &ch, 1, 0)) != 0) {
185 iic_release_bus(sc->sc_tag, 0);
186 aprint_error_dev(sc->sc_dev,
187 "maxrtc_read: read failed at 0x%x\n", a);
188 return (error);
189 }
190 if ((error = uiomove(&ch, 1, uio)) != 0) {
191 iic_release_bus(sc->sc_tag, 0);
192 return (error);
193 }
194 }
195
196 iic_release_bus(sc->sc_tag, 0);
197
198 return (0);
199 }
200
201 /*ARGSUSED*/
202 int
maxrtc_write(dev_t dev,struct uio * uio,int flags)203 maxrtc_write(dev_t dev, struct uio *uio, int flags)
204 {
205 struct maxrtc_softc *sc;
206 u_int8_t cmdbuf[2];
207 int a, error, sverror;
208
209 if ((sc = device_lookup_private(&maxrtc_cd, minor(dev))) == NULL)
210 return (ENXIO);
211
212 if (uio->uio_offset >= MAX6900_RAM_BYTES)
213 return (EINVAL);
214
215 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
216 return (error);
217
218 /* Start by clearing the control register's write-protect bit. */
219 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
220 cmdbuf[1] = 0;
221
222 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
223 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
224 iic_release_bus(sc->sc_tag, 0);
225 aprint_error_dev(sc->sc_dev,
226 "maxrtc_write: failed to clear WP bit\n");
227 return (error);
228 }
229
230 while (uio->uio_resid && uio->uio_offset < MAX6900_RAM_BYTES) {
231 a = (int)uio->uio_offset;
232
233 cmdbuf[0] = MAX6900_REG_RAM(a) | MAX6900_CMD_WRITE;
234 if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0)
235 break;
236
237 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
238 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
239 aprint_error_dev(sc->sc_dev,
240 "maxrtc_write: write failed at 0x%x\n", a);
241 break;
242 }
243 }
244
245 /* Set the write-protect bit again. */
246 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
247 cmdbuf[1] = MAX6900_CONTROL_WP;
248
249 sverror = error;
250 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
251 sc->sc_address, cmdbuf, 1,
252 &cmdbuf[1], 1, 0)) != 0) {
253 if (sverror != 0)
254 error = sverror;
255 aprint_error_dev(sc->sc_dev,
256 "maxrtc_write: failed to set WP bit\n");
257 }
258
259 iic_release_bus(sc->sc_tag, 0);
260
261 return (error);
262 }
263
264 /*
265 * While the MAX6900 has a nice Clock Burst Read/Write command,
266 * we can't use it, since some I2C controllers do not support
267 * anything other than single-byte transfers.
268 */
269 static int max6900_rtc_offset[] = {
270 MAX6900_REG_SECOND,
271 MAX6900_REG_MINUTE,
272 MAX6900_REG_HOUR,
273 MAX6900_REG_DATE,
274 MAX6900_REG_MONTH,
275 MAX6900_REG_DAY,
276 MAX6900_REG_YEAR,
277 MAX6900_REG_CENTURY, /* control, if burst */
278 };
279
280 static int
maxrtc_gettime_ymdhms(struct todr_chip_handle * ch,struct clock_ymdhms * dt)281 maxrtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
282 {
283 struct maxrtc_softc *sc = ch->cookie;
284 u_int8_t bcd[MAX6900_BURST_LEN], cmdbuf[1];
285 int i, error;
286
287 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
288 aprint_error_dev(sc->sc_dev,
289 "maxrtc_clock_read: failed to acquire I2C bus\n");
290 return (error);
291 }
292
293 /* Read each timekeeping register in order. */
294 for (i = 0; i < MAX6900_BURST_LEN; i++) {
295 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_READ;
296
297 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
298 sc->sc_address, cmdbuf, 1,
299 &bcd[i], 1, 0)) != 0) {
300 iic_release_bus(sc->sc_tag, 0);
301 aprint_error_dev(sc->sc_dev,
302 "maxrtc_clock_read: failed to read rtc "
303 "at 0x%x\n",
304 max6900_rtc_offset[i]);
305 return (error);
306 }
307 }
308
309 /* Done with I2C */
310 iic_release_bus(sc->sc_tag, 0);
311
312 /*
313 * Convert the MAX6900's register values into something useable
314 */
315 dt->dt_sec = bcdtobin(bcd[MAX6900_BURST_SECOND] & MAX6900_SECOND_MASK);
316 dt->dt_min = bcdtobin(bcd[MAX6900_BURST_MINUTE] & MAX6900_MINUTE_MASK);
317
318 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS) {
319 dt->dt_hour = bcdtobin(bcd[MAX6900_BURST_HOUR] &
320 MAX6900_HOUR_12MASK);
321 if (bcd[MAX6900_BURST_HOUR] & MAX6900_HOUR_12HRS_PM)
322 dt->dt_hour += 12;
323 } else {
324 dt->dt_hour = bcdtobin(bcd[MAX6900_BURST_HOUR] &
325 MAX6900_HOUR_24MASK);
326 }
327
328 dt->dt_day = bcdtobin(bcd[MAX6900_BURST_DATE] & MAX6900_DATE_MASK);
329 dt->dt_mon = bcdtobin(bcd[MAX6900_BURST_MONTH] & MAX6900_MONTH_MASK);
330 dt->dt_year = bcdtobin(bcd[MAX6900_BURST_YEAR]);
331 /* century in the burst control slot */
332 dt->dt_year += (int)bcdtobin(bcd[MAX6900_BURST_CONTROL]) * 100;
333
334 return (0);
335 }
336
337 static int
maxrtc_settime_ymdhms(struct todr_chip_handle * ch,struct clock_ymdhms * dt)338 maxrtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
339 {
340 struct maxrtc_softc *sc = ch->cookie;
341 uint8_t bcd[MAX6900_BURST_LEN], cmdbuf[2];
342 uint8_t init_seconds, final_seconds;
343 int i, error;
344
345 /*
346 * Convert our time representation into something the MAX6900
347 * can understand.
348 */
349 bcd[MAX6900_BURST_SECOND] = bintobcd(dt->dt_sec);
350 bcd[MAX6900_BURST_MINUTE] = bintobcd(dt->dt_min);
351 bcd[MAX6900_BURST_HOUR] = bintobcd(dt->dt_hour) & MAX6900_HOUR_24MASK;
352 bcd[MAX6900_BURST_DATE] = bintobcd(dt->dt_day);
353 bcd[MAX6900_BURST_WDAY] = bintobcd(dt->dt_wday);
354 bcd[MAX6900_BURST_MONTH] = bintobcd(dt->dt_mon);
355 bcd[MAX6900_BURST_YEAR] = bintobcd(dt->dt_year % 100);
356 /* century in control slot */
357 bcd[MAX6900_BURST_CONTROL] = bintobcd(dt->dt_year / 100);
358
359 if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
360 aprint_error_dev(sc->sc_dev,
361 "maxrtc_clock_write: failed to acquire I2C bus\n");
362 return (error);
363 }
364
365 /* Start by clearing the control register's write-protect bit. */
366 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
367 cmdbuf[1] = 0;
368
369 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
370 cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
371 iic_release_bus(sc->sc_tag, 0);
372 aprint_error_dev(sc->sc_dev,
373 "maxrtc_clock_write: failed to clear WP bit\n");
374 return (error);
375 }
376
377 /*
378 * The MAX6900 RTC manual recommends ensuring "atomicity" of
379 * a non-burst write by:
380 *
381 * - writing SECONDS
382 * - reading back SECONDS, remembering it as "initial seconds"
383 * - write the remaining RTC registers
384 * - read back SECONDS as "final seconds"
385 * - if "initial seconds" == 59, ensure "final seconds" == 59
386 * - else, ensure "final seconds" is no more than one second
387 * beyond "initial seconds".
388 */
389 again:
390 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_WRITE;
391 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
392 cmdbuf, 1, &bcd[MAX6900_BURST_SECOND], 1, 0)) != 0) {
393 iic_release_bus(sc->sc_tag, 0);
394 aprint_error_dev(sc->sc_dev,
395 "maxrtc_clock_write: failed to write SECONDS\n");
396 return (error);
397 }
398
399 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ;
400 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
401 cmdbuf, 1, &init_seconds, 1, 0)) != 0) {
402 iic_release_bus(sc->sc_tag, 0);
403 aprint_error_dev(sc->sc_dev,
404 "maxrtc_clock_write: failed to read "
405 "INITIAL SECONDS\n");
406 return (error);
407 }
408
409 for (i = 1; i < MAX6900_BURST_LEN; i++) {
410 cmdbuf[0] = max6900_rtc_offset[i] | MAX6900_CMD_WRITE;
411 if ((error = iic_exec(sc->sc_tag,
412 i != MAX6900_BURST_LEN - 1 ? I2C_OP_WRITE :
413 I2C_OP_WRITE_WITH_STOP, sc->sc_address,
414 cmdbuf, 1, &bcd[i], 1, 0)) != 0) {
415 iic_release_bus(sc->sc_tag, 0);
416 aprint_error_dev(sc->sc_dev,
417 "maxrtc_clock_write: failed to write rtc "
418 " at 0x%x\n",
419 max6900_rtc_offset[i]);
420 return (error);
421 }
422 }
423
424 cmdbuf[0] = MAX6900_REG_SECOND | MAX6900_CMD_READ;
425 if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP, sc->sc_address,
426 cmdbuf, 1, &final_seconds, 1, 0)) != 0) {
427 iic_release_bus(sc->sc_tag, 0);
428 aprint_error_dev(sc->sc_dev,
429 "maxrtc_clock_write: failed to read "
430 "FINAL SECONDS\n");
431 return (error);
432 }
433
434 if ((init_seconds == 59 && final_seconds != 59) ||
435 (init_seconds != 59 && final_seconds != init_seconds + 1)) {
436 #if 1
437 printf("%s: maxrtc_clock_write: init %d, final %d, try again\n",
438 device_xname(sc->sc_dev), init_seconds, final_seconds);
439 #endif
440 goto again;
441 }
442
443 /* Finish by setting the control register's write-protect bit. */
444 cmdbuf[0] = MAX6900_REG_CONTROL | MAX6900_CMD_WRITE;
445 cmdbuf[1] = MAX6900_CONTROL_WP;
446
447 if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP,
448 sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1,
449 0)) != 0) {
450 iic_release_bus(sc->sc_tag, 0);
451 aprint_error_dev(sc->sc_dev,
452 "maxrtc_clock_write: failed to set WP bit\n");
453 return (error);
454 }
455
456 iic_release_bus(sc->sc_tag, 0);
457
458 return (0);
459 }
460