1 /* $NetBSD: sbusreg.h,v 1.10 2011/03/16 05:49:43 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1996-1999 Eduardo Horvath 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 22 * SUCH DAMAGE. 23 * 24 */ 25 26 27 /* 28 * Sbus device addresses are obtained from the FORTH PROMs. They come 29 * in `absolute' and `relative' address flavors, so we have to handle both. 30 * Relative addresses do *not* include the slot number. 31 */ 32 #define SBUS_BASE 0xf8000000 33 #define SBUS_ADDR(slot, off) (SBUS_BASE + ((slot) << 25) + (off)) 34 #define SBUS_ABS(a) ((unsigned)(a) >= SBUS_BASE) 35 #define SBUS_ABS_TO_SLOT(a) (((a) - SBUS_BASE) >> 25) 36 #define SBUS_ABS_TO_OFFSET(a) (((a) - SBUS_BASE) & 0x1ffffff) 37 38 /* 39 * Sun4u S-bus definitions. Here's where we deal w/the machine 40 * dependencies of sysio. 41 * 42 * SYSIO implements or is the interface to several things: 43 * 44 * o The SBUS interface itself 45 * o The IOMMU 46 * o The DVMA units 47 * o The interrupt controller 48 * o The counter/timers 49 * 50 * Since it has registers to control lots of different things 51 * as well as several on-board SBUS devices and external SBUS 52 * slots scattered throughout its address space, it's a pain. 53 * 54 * One good point, however, is that all registers are 64-bit. 55 */ 56 57 struct sysioreg { 58 struct upareg { 59 uint64_t upa_portid; /* UPA port ID register */ /* 1fe.0000.0000 */ 60 uint64_t upa_config; /* UPA config register */ /* 1fe.0000.0008 */ 61 } sys_upa; 62 63 uint64_t sys_csr; /* SYSIO control/status register */ /* 1fe.0000.0010 */ 64 uint64_t pad0; 65 uint64_t sys_ecccr; /* ECC control register */ /* 1fe.0000.0020 */ 66 uint64_t reserved; /* 1fe.0000.0028 */ 67 uint64_t sys_ue_afsr; /* Uncorrectable Error AFSR */ /* 1fe.0000.0030 */ 68 uint64_t sys_ue_afar; /* Uncorrectable Error AFAR */ /* 1fe.0000.0038 */ 69 uint64_t sys_ce_afsr; /* Correctable Error AFSR */ /* 1fe.0000.0040 */ 70 uint64_t sys_ce_afar; /* Correctable Error AFAR */ /* 1fe.0000.0048 */ 71 72 uint64_t pad1[22]; 73 74 struct perfmon { 75 uint64_t pm_cr; /* Performance monitor control reg */ /* 1fe.0000.0100 */ 76 uint64_t pm_count; /* Performance monitor counter reg */ /* 1fe.0000.0108 */ 77 } sys_pm; 78 79 uint64_t pad2[990]; 80 81 struct sbusreg { 82 uint64_t sbus_cr; /* SBUS Control Register */ /* 1fe.0000.2000 */ 83 uint64_t reserved; /* 1fe.0000.2008 */ 84 uint64_t sbus_afsr; /* SBUS AFSR */ /* 1fe.0000.2010 */ 85 uint64_t sbus_afar; /* SBUS AFAR */ /* 1fe.0000.2018 */ 86 uint64_t sbus_config0; /* SBUS Slot 0 config register */ /* 1fe.0000.2020 */ 87 uint64_t sbus_config1; /* SBUS Slot 1 config register */ /* 1fe.0000.2028 */ 88 uint64_t sbus_config2; /* SBUS Slot 2 config register */ /* 1fe.0000.2030 */ 89 uint64_t sbus_config3; /* SBUS Slot 3 config register */ /* 1fe.0000.2038 */ 90 uint64_t sbus_config13; /* Slot 13 config register <audio> */ /* 1fe.0000.2040 */ 91 uint64_t sbus_config14; /* Slot 14 config register <macio> */ /* 1fe.0000.2048 */ 92 uint64_t sbus_config15; /* Slot 15 config register <slavio> */ /* 1fe.0000.2050 */ 93 } sys_sbus; 94 95 uint64_t pad3[117]; 96 97 struct iommureg sys_iommu; /* 1fe.0000.2400,2410 */ 98 99 uint64_t pad4[125]; 100 101 struct iommu_strbuf sys_strbuf; /* 1fe.0000.2800-2810 */ 102 103 uint64_t pad5[125]; 104 105 uint64_t sbus_slot0_int; /* SBUS slot 0 interrupt map reg */ /* 1fe.0000.2c00 */ 106 uint64_t sbus_slot1_int; /* SBUS slot 1 interrupt map reg */ /* 1fe.0000.2c08 */ 107 uint64_t sbus_slot2_int; /* SBUS slot 2 interrupt map reg */ /* 1fe.0000.2c10 */ 108 uint64_t sbus_slot3_int; /* SBUS slot 3 interrupt map reg */ /* 1fe.0000.2c18 */ 109 uint64_t intr_retry; /* interrupt retry timer reg */ /* 1fe.0000.2c20 */ 110 111 uint64_t pad6[123]; 112 113 uint64_t scsi_int_map; /* SCSI interrupt map reg */ /* 1fe.0000.3000 */ 114 uint64_t ether_int_map; /* ethernet interrupt map reg */ /* 1fe.0000.3008 */ 115 uint64_t bpp_int_map; /* parallel interrupt map reg */ /* 1fe.0000.3010 */ 116 uint64_t audio_int_map; /* audio interrupt map reg */ /* 1fe.0000.3018 */ 117 uint64_t power_int_map; /* power fail interrupt map reg */ /* 1fe.0000.3020 */ 118 uint64_t ser_kbd_ms_int_map; /* serial/kbd/mouse interrupt map reg *//* 1fe.0000.3028 */ 119 uint64_t fd_int_map; /* floppy interrupt map reg */ /* 1fe.0000.3030 */ 120 uint64_t therm_int_map; /* thermal warn interrupt map reg */ /* 1fe.0000.3038 */ 121 uint64_t kbd_int_map; /* kbd [unused] interrupt map reg */ /* 1fe.0000.3040 */ 122 uint64_t mouse_int_map; /* mouse [unused] interrupt map reg */ /* 1fe.0000.3048 */ 123 uint64_t serial_int_map; /* second serial interrupt map reg */ /* 1fe.0000.3050 */ 124 uint64_t pad7; 125 uint64_t timer0_int_map; /* timer 0 interrupt map reg */ /* 1fe.0000.3060 */ 126 uint64_t timer1_int_map; /* timer 1 interrupt map reg */ /* 1fe.0000.3068 */ 127 uint64_t ue_int_map; /* UE interrupt map reg */ /* 1fe.0000.3070 */ 128 uint64_t ce_int_map; /* CE interrupt map reg */ /* 1fe.0000.3078 */ 129 uint64_t sbus_async_int_map; /* SBUS error interrupt map reg */ /* 1fe.0000.3080 */ 130 uint64_t pwrmgt_int_map; /* power mgmt wake interrupt map reg */ /* 1fe.0000.3088 */ 131 uint64_t upagr_int_map; /* UPA graphics interrupt map reg */ /* 1fe.0000.3090 */ 132 uint64_t reserved_int_map; /* reserved interrupt map reg */ /* 1fe.0000.3098 */ 133 134 uint64_t pad8[108]; 135 136 /* Note: clear interrupt 0 registers are not really used */ 137 uint64_t sbus0_clr_int[8]; /* SBUS slot 0 clear int regs 0..7 */ /* 1fe.0000.3400-3438 */ 138 uint64_t sbus1_clr_int[8]; /* SBUS slot 1 clear int regs 0..7 */ /* 1fe.0000.3440-3478 */ 139 uint64_t sbus2_clr_int[8]; /* SBUS slot 2 clear int regs 0..7 */ /* 1fe.0000.3480-34b8 */ 140 uint64_t sbus3_clr_int[8]; /* SBUS slot 3 clear int regs 0..7 */ /* 1fe.0000.34c0-34f8 */ 141 142 uint64_t pad9[96]; 143 144 uint64_t scsi_clr_int; /* SCSI clear int reg */ /* 1fe.0000.3800 */ 145 uint64_t ether_clr_int; /* ethernet clear int reg */ /* 1fe.0000.3808 */ 146 uint64_t bpp_clr_int; /* parallel clear int reg */ /* 1fe.0000.3810 */ 147 uint64_t audio_clr_int; /* audio clear int reg */ /* 1fe.0000.3818 */ 148 uint64_t power_clr_int; /* power fail clear int reg */ /* 1fe.0000.3820 */ 149 uint64_t ser_kb_ms_clr_int; /* serial/kbd/mouse clear int reg */ /* 1fe.0000.3828 */ 150 uint64_t fd_clr_int; /* floppy clear int reg */ /* 1fe.0000.3830 */ 151 uint64_t therm_clr_int; /* thermal warn clear int reg */ /* 1fe.0000.3838 */ 152 uint64_t kbd_clr_int; /* kbd [unused] clear int reg */ /* 1fe.0000.3840 */ 153 uint64_t mouse_clr_int; /* mouse [unused] clear int reg */ /* 1fe.0000.3848 */ 154 uint64_t serial_clr_int; /* second serial clear int reg */ /* 1fe.0000.3850 */ 155 uint64_t pad10; 156 uint64_t timer0_clr_int; /* timer 0 clear int reg */ /* 1fe.0000.3860 */ 157 uint64_t timer1_clr_int; /* timer 1 clear int reg */ /* 1fe.0000.3868 */ 158 uint64_t ue_clr_int; /* UE clear int reg */ /* 1fe.0000.3870 */ 159 uint64_t ce_clr_int; /* CE clear int reg */ /* 1fe.0000.3878 */ 160 uint64_t sbus_clr_async_int; /* SBUS error clr interrupt reg */ /* 1fe.0000.3880 */ 161 uint64_t pwrmgt_clr_int; /* power mgmt wake clr interrupt reg */ /* 1fe.0000.3888 */ 162 163 uint64_t pad11[110]; 164 165 struct timer_counter { 166 uint64_t tc_count; /* timer/counter 0/1 count register */ /* ife.0000.3c00,3c10 */ 167 uint64_t tc_limit; /* timer/counter 0/1 limit register */ /* ife.0000.3c08,3c18 */ 168 } tc[2]; 169 170 uint64_t pad12[252]; 171 172 uint64_t sys_svadiag; /* SBUS virtual addr diag reg */ /* 1fe.0000.4400 */ 173 174 uint64_t pad13[31]; 175 176 uint64_t iommu_queue_diag[16]; /* IOMMU LRU queue diag */ /* 1fe.0000.4500-457f */ 177 uint64_t tlb_tag_diag[16]; /* TLB tag diag */ /* 1fe.0000.4580-45ff */ 178 uint64_t tlb_data_diag[32]; /* TLB data RAM diag */ /* 1fe.0000.4600-46ff */ 179 180 uint64_t pad14[32]; 181 182 uint64_t sbus_int_diag; /* SBUS int state diag reg */ /* 1fe.0000.4800 */ 183 uint64_t obio_int_diag; /* OBIO and misc int state diag reg */ /* 1fe.0000.4808 */ 184 185 uint64_t pad15[254]; 186 187 uint64_t strbuf_data_diag[128]; /* streaming buffer data RAM diag */ /* 1fe.0000.5000-53f8 */ 188 uint64_t strbuf_error_diag[128]; /* streaming buffer error status diag *//* 1fe.0000.5400-57f8 */ 189 uint64_t strbuf_pg_tag_diag[16]; /* streaming buffer page tag diag */ /* 1fe.0000.5800-5878 */ 190 uint64_t pad16[16]; 191 uint64_t strbuf_ln_tag_diag[16]; /* streaming buffer line tag diag */ /* 1fe.0000.5900-5978 */ 192 }; 193