1 /* $NetBSD: imc.c,v 1.37 2021/08/07 16:19:04 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 2001 Rafal K. Boni
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.37 2021/08/07 16:19:04 thorpej Exp $");
32
33 #include <sys/param.h>
34 #include <sys/device.h>
35 #include <sys/systm.h>
36
37 #include <machine/cpu.h>
38 #include <machine/locore.h>
39 #include <machine/autoconf.h>
40 #include <sys/bus.h>
41 #include <machine/machtype.h>
42 #include <machine/sysconf.h>
43
44 #include <sgimips/dev/imcreg.h>
45 #include <sgimips/dev/imcvar.h>
46
47 #include <sgimips/gio/giovar.h>
48
49 #include "locators.h"
50
51 struct imc_softc {
52 bus_space_tag_t iot;
53 bus_space_handle_t ioh;
54
55 int eisa_present;
56 };
57
58 static int imc_match(device_t, cfdata_t, void *);
59 static void imc_attach(device_t, device_t, void *);
60 static int imc_print(void *, const char *);
61 static void imc_bus_reset(void);
62 static void imc_bus_error(vaddr_t, uint32_t, uint32_t);
63 static void imc_watchdog_reset(void);
64 static void imc_watchdog_disable(void);
65 static void imc_watchdog_enable(void);
66
67 CFATTACH_DECL_NEW(imc, sizeof(struct imc_softc),
68 imc_match, imc_attach, NULL, NULL);
69
70 struct imc_attach_args {
71 const char* iaa_name;
72
73 bus_space_tag_t iaa_st;
74 bus_space_handle_t iaa_sh;
75
76 /* ? */
77 long iaa_offset;
78 int iaa_intr;
79 #if 0
80 int iaa_stride;
81 #endif
82 };
83
84 int imc_gio64_arb_config(int, uint32_t);
85
86 struct imc_softc isc;
87
88 static int
imc_match(device_t parent,cfdata_t match,void * aux)89 imc_match(device_t parent, cfdata_t match, void *aux)
90 {
91
92 if ((mach_type == MACH_SGI_IP22) || (mach_type == MACH_SGI_IP20))
93 return 1;
94
95 return 0;
96 }
97
98 static void
imc_attach(device_t parent,device_t self,void * aux)99 imc_attach(device_t parent, device_t self, void *aux)
100 {
101 uint32_t reg;
102 struct imc_attach_args iaa;
103 struct mainbus_attach_args *ma = aux;
104 uint32_t sysid;
105
106 isc.iot = normal_memt;
107 if (bus_space_map(isc.iot, ma->ma_addr, 0x100,
108 BUS_SPACE_MAP_LINEAR, &isc.ioh))
109 panic("imc_attach: could not map registers\n");
110
111 platform.bus_reset = imc_bus_reset;
112 platform.watchdog_reset = imc_watchdog_reset;
113 platform.watchdog_disable = imc_watchdog_disable;
114 platform.watchdog_enable = imc_watchdog_enable;
115
116 sysid = bus_space_read_4(isc.iot, isc.ioh, IMC_SYSID);
117
118 /* EISA exists on IP22 only */
119 if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
120 isc.eisa_present = (sysid & IMC_SYSID_HAVEISA);
121 else
122 isc.eisa_present = 0;
123
124 printf(": revision %d", (sysid & IMC_SYSID_REVMASK));
125
126 if (isc.eisa_present)
127 printf(", EISA bus present");
128
129 printf("\n");
130
131 /* Clear CPU/GIO error status registers to clear any leftover bits. */
132 imc_bus_reset();
133
134 /* Hook the bus error handler into the ISR */
135 platform.intr4 = imc_bus_error;
136
137 /*
138 * Enable parity reporting on GIO/main memory transactions.
139 * Disable parity checking on CPU bus transactions (as turning
140 * it on seems to cause spurious bus errors), but enable parity
141 * checking on CPU reads from main memory (note that this bit
142 * has the opposite sense... Turning it on turns the checks off!).
143 * Finally, turn on interrupt writes to the CPU from the MC.
144 */
145 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
146 reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;
147 reg |= (IMC_CPUCTRL0_GPR | IMC_CPUCTRL0_MPR | IMC_CPUCTRL0_INTENA);
148 bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
149
150 /* Setup the MC write buffer depth */
151 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL1);
152 reg = (reg & ~IMC_CPUCTRL1_MCHWMSK) | 13;
153
154 /*
155 * Force endianness on the onboard HPC and both slots.
156 * This should be safe for Fullhouse, but leave it conditional
157 * for now.
158 */
159 if (mach_type == MACH_SGI_IP20 || (mach_type == MACH_SGI_IP22 &&
160 mach_subtype == MACH_SGI_IP22_GUINNESS)) {
161 reg |= IMC_CPUCTRL1_HPCFX;
162 reg |= IMC_CPUCTRL1_EXP0FX;
163 reg |= IMC_CPUCTRL1_EXP1FX;
164 reg &= ~IMC_CPUCTRL1_HPCLITTLE;
165 reg &= ~IMC_CPUCTRL1_EXP0LITTLE;
166 reg &= ~IMC_CPUCTRL1_EXP1LITTLE;
167 }
168 bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL1, reg);
169
170
171 /*
172 * Set GIO64 arbitrator configuration register:
173 *
174 * Preserve PROM-set graphics-related bits, as they seem to depend
175 * on the graphics variant present and I'm not sure how to figure
176 * that out or 100% sure what the correct settings are for each.
177 */
178 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);
179 reg &= (IMC_GIO64ARB_GRX64 | IMC_GIO64ARB_GRXRT | IMC_GIO64ARB_GRXMST);
180
181 /* Rest of settings are machine/board dependent */
182 if (mach_type == MACH_SGI_IP20) {
183 reg |= IMC_GIO64ARB_ONEGIO;
184 reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT);
185 reg |= (IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);
186 reg &= ~(IMC_GIO64ARB_HPC64 |
187 IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EISA64 |
188 IMC_GIO64ARB_EXP064 | IMC_GIO64ARB_EXP164 |
189 IMC_GIO64ARB_EXP0PIPE | IMC_GIO64ARB_EXP1PIPE);
190 } else {
191 /*
192 * GIO64 invariant for all IP22 platforms: one GIO bus,
193 * HPC1 @ 64
194 */
195 reg |= IMC_GIO64ARB_ONEGIO | IMC_GIO64ARB_HPC64;
196
197 switch (mach_subtype) {
198 case MACH_SGI_IP22_GUINNESS:
199 /* XXX is MST mutually exclusive? */
200 reg |= (IMC_GIO64ARB_EXP0RT | IMC_GIO64ARB_EXP1RT);
201 reg |= (IMC_GIO64ARB_EXP0MST | IMC_GIO64ARB_EXP1MST);
202
203 /* EISA can bus-master, is 64-bit */
204 reg |= (IMC_GIO64ARB_EISAMST | IMC_GIO64ARB_EISA64);
205 break;
206
207 case MACH_SGI_IP22_FULLHOUSE:
208 /*
209 * All Fullhouse boards have a 64-bit HPC2 and pipelined
210 * EXP0 slot.
211 */
212 reg |= (IMC_GIO64ARB_HPCEXP64 | IMC_GIO64ARB_EXP0PIPE);
213
214 if (mach_boardrev < 2) {
215 /* EXP0 realtime, EXP1 can master */
216 reg |= (IMC_GIO64ARB_EXP0RT |
217 IMC_GIO64ARB_EXP1MST);
218 } else {
219 /* EXP1 pipelined as well, EISA masters */
220 reg |= (IMC_GIO64ARB_EXP1PIPE |
221 IMC_GIO64ARB_EISAMST);
222 }
223 break;
224 }
225 }
226
227 bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);
228
229 if (isc.eisa_present) {
230 #if notyet
231 memset(&iaa, 0, sizeof(iaa));
232
233 config_found(self, &iaa, eisabusprint,
234 CFARGS(.iattr = "eisabus"));
235 #endif
236 }
237
238 memset(&iaa, 0, sizeof(iaa));
239
240 config_found(self, &iaa, imc_print,
241 CFARGS(.iattr = "giobus"));
242
243 imc_watchdog_enable();
244 }
245
246
247 static int
imc_print(void * aux,const char * name)248 imc_print(void *aux, const char *name)
249 {
250
251 if (name)
252 aprint_normal("gio at %s", name);
253
254 return UNCONF;
255 }
256
257 static void
imc_bus_reset(void)258 imc_bus_reset(void)
259 {
260
261 bus_space_write_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT, 0);
262 bus_space_write_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT, 0);
263 }
264
265 static void
imc_bus_error(vaddr_t pc,uint32_t status,uint32_t ipending)266 imc_bus_error(vaddr_t pc, uint32_t status, uint32_t ipending)
267 {
268
269 printf("bus error: cpu_stat %08x addr %08x, gio_stat %08x addr %08x\n",
270 bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRSTAT),
271 bus_space_read_4(isc.iot, isc.ioh, IMC_CPU_ERRADDR),
272 bus_space_read_4(isc.iot, isc.ioh, IMC_GIO_ERRSTAT),
273 bus_space_read_4(isc.iot, isc.ioh, IMC_GIO_ERRADDR) );
274 imc_bus_reset();
275 }
276
277 static void
imc_watchdog_reset(void)278 imc_watchdog_reset(void)
279 {
280
281 bus_space_write_4(isc.iot, isc.ioh, IMC_WDOG, 0);
282 }
283
284 static void
imc_watchdog_disable(void)285 imc_watchdog_disable(void)
286 {
287 uint32_t reg;
288
289 bus_space_write_4(isc.iot, isc.ioh, IMC_WDOG, 0);
290 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
291 reg &= ~(IMC_CPUCTRL0_WDOG);
292 bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
293 }
294
295 static void
imc_watchdog_enable(void)296 imc_watchdog_enable(void)
297 {
298 uint32_t reg;
299
300 /* enable watchdog and clear it */
301 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
302 reg |= IMC_CPUCTRL0_WDOG;
303 bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
304 imc_watchdog_reset();
305 }
306
307 /* intended to be called from gio/gio.c only */
308 int
imc_gio64_arb_config(int slot,uint32_t flags)309 imc_gio64_arb_config(int slot, uint32_t flags)
310 {
311 uint32_t reg;
312
313 /* GIO_SLOT_EXP1 is unusable on Fullhouse */
314 if (slot == GIO_SLOT_EXP1 && mach_subtype == MACH_SGI_IP22_FULLHOUSE)
315 return EINVAL;
316
317 /* GIO_SLOT_GFX is only usable on Fullhouse */
318 if (slot == GIO_SLOT_GFX && mach_subtype != MACH_SGI_IP22_FULLHOUSE)
319 return EINVAL;
320
321 /* GIO_SLOT_GFX is always pipelined */
322 if (slot == GIO_SLOT_GFX && (flags & GIO_ARB_NOPIPE))
323 return EINVAL;
324
325 /* IP20 does not support pipelining (XXX what about Indy?) */
326 if (((flags & GIO_ARB_PIPE) || (flags & GIO_ARB_NOPIPE)) &&
327 mach_type == MACH_SGI_IP20)
328 return EINVAL;
329
330 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_GIO64ARB);
331
332 if (flags & GIO_ARB_RT) {
333 if (slot == GIO_SLOT_EXP0)
334 reg |= IMC_GIO64ARB_EXP0RT;
335 else if (slot == GIO_SLOT_EXP1)
336 reg |= IMC_GIO64ARB_EXP1RT;
337 else if (slot == GIO_SLOT_GFX)
338 reg |= IMC_GIO64ARB_GRXRT;
339 }
340
341 if (flags & GIO_ARB_MST) {
342 if (slot == GIO_SLOT_EXP0)
343 reg |= IMC_GIO64ARB_EXP0MST;
344 else if (slot == GIO_SLOT_EXP1)
345 reg |= IMC_GIO64ARB_EXP1MST;
346 else if (slot == GIO_SLOT_GFX)
347 reg |= IMC_GIO64ARB_GRXMST;
348 }
349
350 if (flags & GIO_ARB_PIPE) {
351 if (slot == GIO_SLOT_EXP0)
352 reg |= IMC_GIO64ARB_EXP0PIPE;
353 else if (slot == GIO_SLOT_EXP1)
354 reg |= IMC_GIO64ARB_EXP1PIPE;
355 }
356
357 if (flags & GIO_ARB_LB) {
358 if (slot == GIO_SLOT_EXP0)
359 reg &= ~IMC_GIO64ARB_EXP0RT;
360 else if (slot == GIO_SLOT_EXP1)
361 reg &= ~IMC_GIO64ARB_EXP1RT;
362 else if (slot == GIO_SLOT_GFX)
363 reg &= ~IMC_GIO64ARB_GRXRT;
364 }
365
366 if (flags & GIO_ARB_SLV) {
367 if (slot == GIO_SLOT_EXP0)
368 reg &= ~IMC_GIO64ARB_EXP0MST;
369 else if (slot == GIO_SLOT_EXP1)
370 reg &= ~IMC_GIO64ARB_EXP1MST;
371 else if (slot == GIO_SLOT_GFX)
372 reg &= ~IMC_GIO64ARB_GRXMST;
373 }
374
375 if (flags & GIO_ARB_NOPIPE) {
376 if (slot == GIO_SLOT_EXP0)
377 reg &= ~IMC_GIO64ARB_EXP0PIPE;
378 else if (slot == GIO_SLOT_EXP1)
379 reg &= ~IMC_GIO64ARB_EXP1PIPE;
380 }
381
382 if (flags & GIO_ARB_32BIT) {
383 if (slot == GIO_SLOT_EXP0)
384 reg &= ~IMC_GIO64ARB_EXP064;
385 else if (slot == GIO_SLOT_EXP1)
386 reg &= ~IMC_GIO64ARB_EXP164;
387 }
388
389 if (flags & GIO_ARB_64BIT) {
390 if (slot == GIO_SLOT_EXP0)
391 reg |= IMC_GIO64ARB_EXP064;
392 else if (slot == GIO_SLOT_EXP1)
393 reg |= IMC_GIO64ARB_EXP164;
394 }
395
396 if (flags & GIO_ARB_HPC2_32BIT)
397 reg &= ~IMC_GIO64ARB_HPCEXP64;
398
399 if (flags & GIO_ARB_HPC2_64BIT)
400 reg |= IMC_GIO64ARB_HPCEXP64;
401
402 bus_space_write_4(isc.iot, isc.ioh, IMC_GIO64ARB, reg);
403
404 return 0;
405 }
406
407 /*
408 * According to chapter 19 of the "IRIX Device Driver Programmer's Guide",
409 * some GIO devices, which do not drive all data lines, may cause false
410 * memory read parity errors on the SysAD bus. The workaround is to disable
411 * parity checking.
412 */
413 void
imc_disable_sysad_parity(void)414 imc_disable_sysad_parity(void)
415 {
416 uint32_t reg;
417
418 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
419 return;
420
421 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
422 reg |= IMC_CPUCTRL0_NCHKMEMPAR;
423 bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
424 }
425
426 void
imc_enable_sysad_parity(void)427 imc_enable_sysad_parity(void)
428 {
429 uint32_t reg;
430
431 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
432 return;
433
434 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
435 reg &= ~IMC_CPUCTRL0_NCHKMEMPAR;
436 bus_space_write_4(isc.iot, isc.ioh, IMC_CPUCTRL0, reg);
437 }
438
439 int
imc_is_sysad_parity_enabled(void)440 imc_is_sysad_parity_enabled(void)
441 {
442 uint32_t reg;
443
444 if (mach_type != MACH_SGI_IP20 && mach_type != MACH_SGI_IP22)
445 return 0;
446
447 reg = bus_space_read_4(isc.iot, isc.ioh, IMC_CPUCTRL0);
448
449 return reg & IMC_CPUCTRL0_NCHKMEMPAR;
450 }
451