1 /* $NetBSD: dmareg.h,v 1.4 2023/02/07 14:27:59 tsutsui Exp $ */ 2 /* 3 * Copyright (c) 1997 Rolf Grossmann 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Rolf Grossmann. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define MAX_DMASIZE 4096 33 34 /* from nextdev/dma.h */ 35 36 #if 0 37 #define DMA_BEGINALIGNMENT 4 /* initial buffer must be on long */ 38 #else 39 #define DMA_BEGINALIGNMENT 16 /* initial buffer must be on long */ 40 #endif 41 42 #define DMA_ENDALIGNMENT 16 /* DMA must end on quad longword */ 43 #define ENDMA_ENDALIGNMENT 32 /* Ethernet DMA is very special */ 44 45 #define DMA_ALIGN(type, addr) \ 46 ((type)(((unsigned)(addr)+DMA_BEGINALIGNMENT-1) \ 47 &~(DMA_BEGINALIGNMENT-1))) 48 49 #define DMA_ENDALIGN(type, addr) \ 50 ((type)(((unsigned)(addr)+DMA_ENDALIGNMENT-1) \ 51 &~(DMA_ENDALIGNMENT-1))) 52 53 #define ENDMA_ENDALIGN(type, addr) \ 54 ((type)((((unsigned)(addr)+ENDMA_ENDALIGNMENT-1) \ 55 &~(DMA_ENDALIGNMENT-1))|0x80000000)) 56 57 struct dma_dev { /* format of dma device registers */ 58 volatile uint32_t dd_csr; /* control & status register */ 59 char dd_pad[0x3fec]; /* csr not contiguous with next */ 60 char *dd_saved_next; /* saved pointers for HW restart */ 61 char *dd_saved_limit; 62 char *dd_saved_start; 63 char *dd_saved_stop; 64 char *dd_next; /* next word to dma */ 65 char *dd_limit; /* dma complete when next == limit */ 66 char *dd_start; /* start of 2nd buf to dma */ 67 char *dd_stop; /* end of 2nd buf to dma */ 68 char dd_pad2[0x1f0]; 69 char *dd_next_initbuf; /* next register that inits dma buffering */ 70 }; 71 72 /* 73 * bits in dd_csr 74 */ 75 /* read bits */ 76 #define DMACSR_ENABLE 0x01000000 /* enable dma transfer */ 77 #define DMACSR_SUPDATE 0x02000000 /* single update */ 78 #define DMACSR_COMPLETE 0x08000000 /* current dma has completed */ 79 #define DMACSR_BUSEXC 0x10000000 /* bus exception occurred */ 80 /* write bits */ 81 #define DMACSR_SETENABLE 0x00010000 /* set enable */ 82 #define DMACSR_SETSUPDATE 0x00020000 /* set single update */ 83 #define DMACSR_READ 0x00040000 /* dma from dev to mem */ 84 #define DMACSR_WRITE 0x00000000 /* dma from mem to dev */ 85 #define DMACSR_CLRCOMPLETE 0x00080000 /* clear complete conditional */ 86 #define DMACSR_RESET 0x00100000 /* clr cmplt, sup, enable */ 87 #define DMACSR_INITBUF 0x00200000 /* initialize DMA buffers */ 88 #define DMACSR_INITBUFTURBO 0x00800000 89