1 /* $NetBSD: intr.h,v 1.13 2021/02/16 05:11:26 simonb Exp $ */
2
3 /*-
4 * Copyright (c) 2009, 2010 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas <matt@3am-software.com>.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _MIPS_INTR_H_
33 #define _MIPS_INTR_H_
34
35 #ifdef _KERNEL_OPT
36 #include "opt_multiprocessor.h"
37 #endif
38
39 /*
40 * This is a common <machine/intr.h> for all MIPS platforms.
41 */
42
43 #define IPL_NONE 0
44 #define IPL_SOFTCLOCK (IPL_NONE+1)
45 #define IPL_SOFTBIO (IPL_SOFTCLOCK) /* shares SWINT with softclock */
46 #define IPL_SOFTNET (IPL_SOFTBIO+1)
47 #define IPL_SOFTSERIAL (IPL_SOFTNET) /* shares SWINT with softnet */
48 #define IPL_VM (IPL_SOFTSERIAL+1)
49 #define IPL_SCHED (IPL_VM+1)
50 #define IPL_DDB (IPL_SCHED+1)
51 #define IPL_HIGH (IPL_DDB+1)
52
53 #define IPL_SAFEPRI IPL_SOFTSERIAL
54
55 #define _IPL_N (IPL_HIGH+1)
56 #define _IPL_NAMES(pfx) { pfx"none", pfx"softclock/bio", pfx"softnet/serial", \
57 pfx"vm", pfx"sched", pfx"ddb", pfx"high" }
58
59 #define IST_UNUSABLE -1 /* interrupt cannot be used */
60 #define IST_NONE 0 /* none (dummy) */
61 #define IST_PULSE 1 /* pulsed */
62 #define IST_EDGE 2 /* edge-triggered */
63 #define IST_LEVEL 3 /* level-triggered */
64 #define IST_LEVEL_HIGH 4 /* level triggered, active high */
65 #define IST_LEVEL_LOW 5 /* level triggered, active low */
66
67 #define IST_MPSAFE 0x100 /* interrupt is MPSAFE */
68
69 #define IPI_NOP 0 /* do nothing, interrupt only */
70 #define IPI_AST 1 /* force ast */
71 #define IPI_SHOOTDOWN 2 /* do a tlb shootdown */
72 #define IPI_SYNCICACHE 3 /* sync icache for pages */
73 #define IPI_KPREEMPT 4 /* schedule a kernel preemption */
74 #define IPI_SUSPEND 5 /* DDB suspend signaling */
75 #define IPI_HALT 6 /* halt cpu */
76 #define IPI_XCALL 7 /* xcall */
77 #define IPI_GENERIC 8 /* generic IPI */
78 #define IPI_WDOG 9 /* tickle a wdog */
79 #define NIPIS 10
80
81 #ifdef __INTR_PRIVATE
82 struct splsw {
83 int (*splsw_splhigh)(void);
84 int (*splsw_splsched)(void);
85 int (*splsw_splvm)(void);
86 int (*splsw_splsoftserial)(void);
87 int (*splsw_splsoftnet)(void);
88 int (*splsw_splsoftbio)(void);
89 int (*splsw_splsoftclock)(void);
90 int (*splsw_splraise)(int);
91 void (*splsw_spl0)(void);
92 void (*splsw_splx)(int);
93 int (*splsw_splhigh_noprof)(void);
94 void (*splsw_splx_noprof)(int);
95 void (*splsw__setsoftintr)(uint32_t);
96 void (*splsw__clrsoftintr)(uint32_t);
97 int (*splsw_splintr)(uint32_t *);
98 void (*splsw_splcheck)(void);
99 };
100
101 struct ipl_sr_map {
102 uint32_t sr_bits[_IPL_N];
103 };
104 #else
105 struct splsw;
106 #endif /* __INTR_PRIVATE */
107
108 typedef int ipl_t;
109 typedef struct {
110 ipl_t _spl;
111 } ipl_cookie_t;
112
113 #ifdef _KERNEL
114
115 #if 0
116 #if defined(MULTIPROCESSOR) && defined(__HAVE_FAST_SOFTINTS)
117 #define __HAVE_PREEMPTION 1
118 #define SOFTINT_KPREEMPT (SOFTINT_COUNT+0)
119 #endif
120 #endif
121
122 #ifdef __INTR_PRIVATE
123 extern struct splsw mips_splsw;
124 extern struct ipl_sr_map ipl_sr_map;
125 #endif /* __INTR_PRIVATE */
126
127 int splhigh(void);
128 int __noprofile splhigh_noprof(void);
129 int splsched(void);
130 int splvm(void);
131 int splsoftserial(void);
132 int splsoftnet(void);
133 int splsoftbio(void);
134 int splsoftclock(void);
135 int splraise(int);
136 void splx(int);
137 void __noprofile splx_noprof(int);
138 void spl0(void);
139 int splintr(uint32_t *);
140 void _setsoftintr(uint32_t);
141 void _clrsoftintr(uint32_t);
142
143 struct cpu_info;
144
145 void ipi_init(struct cpu_info *);
146 void ipi_process(struct cpu_info *, uint64_t);
147
148 /*
149 * These make no sense *NOT* to be inlined.
150 */
151 static inline ipl_cookie_t
makeiplcookie(ipl_t s)152 makeiplcookie(ipl_t s)
153 {
154 return (ipl_cookie_t){._spl = s};
155 }
156
157 static inline int
splraiseipl(ipl_cookie_t icookie)158 splraiseipl(ipl_cookie_t icookie)
159 {
160 return splraise(icookie._spl);
161 }
162
163 #endif /* _KERNEL */
164 #endif /* _MIPS_INTR_H_ */
165