1 /* $NetBSD: am79c950reg.h,v 1.2 2022/10/31 20:30:23 andvar Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 David Huang <khym@bga.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28 /* 29 * AMD MACE (Am79C940) register definitions 30 */ 31 #define MACE_RCVFIFO 0 /* Receive FIFO [15-00] (read only) */ 32 #define MACE_XMTFIFO 1 /* Transmit FIFO [15-00] (write only) */ 33 #define MACE_XMTFC 2 /* Transmit Frame Control (read/write) */ 34 #define MACE_XMTFS 3 /* Transmit Frame Status (read only) */ 35 #define MACE_XMTRC 4 /* Transmit Retry Count (read only) */ 36 #define MACE_RCVFC 5 /* Receive Frame Control (read/write) */ 37 #define MACE_RCVFS 6 /* Receive Frame Status (4 bytes) (read only) */ 38 #define MACE_FIFOFC 7 /* FIFO Frame Count (read only) */ 39 #define MACE_IR 8 /* Interrupt Register (read only) */ 40 #define MACE_IMR 9 /* Interrupt Mask Register (read/write) */ 41 #define MACE_PR 10 /* Poll Register (read only) */ 42 #define MACE_BIUCC 11 /* BIU Configuration Control (read/write) */ 43 #define MACE_FIFOCC 12 /* FIFO Configuration Control (read/write) */ 44 #define MACE_MACCC 13 /* MAC Configuration Control (read/write) */ 45 #define MACE_PLSCC 14 /* PLS Configuration Control (read/write) */ 46 #define MACE_PHYCC 15 /* PHY Confiuration Control (read/write) */ 47 #define MACE_CHIPIDL 16 /* Chip ID Register [07-00] (read only) */ 48 #define MACE_CHIPIDH 17 /* Chip ID Register [15-08] (read only) */ 49 #define MACE_IAC 18 /* Internal Address Configuration (read/write) */ 50 /* RESERVED 19 Reserved (read/write as 0) */ 51 #define MACE_LADRF 20 /* Logical Address Filter (8 bytes) (read/write) */ 52 #define MACE_PADR 21 /* Physical Address (6 bytes) (read/write) */ 53 /* RESERVED 22 Reserved (read/write as 0) */ 54 /* RESERVED 23 Reserved (read/write as 0) */ 55 #define MACE_MPC 24 /* Missed Packet Count (read only) */ 56 /* RESERVED 25 Reserved (read/write as 0) */ 57 #define MACE_RNTPC 26 /* Runt Packet Count (read only) */ 58 #define MACE_RCVCC 27 /* Receive Collision Count (read only) */ 59 /* RESERVED 28 Reserved (read/write as 0) */ 60 #define MACE_UTR 29 /* User Test Register (read/write) */ 61 #define MACE_RTR1 30 /* Reserved Test Register 1 (read/write as 0) */ 62 #define MACE_RTR2 31 /* Reserved Test Register 2 (read/write as 0) */ 63 64 #define MACE_NREGS 32 65 66 /* 2: Transmit Frame Control (XMTFC) */ 67 #define DRTRY 0x80 /* Disable Retry */ 68 #define DXMTFCS 0x08 /* Disable Transmit FCS */ 69 #define APADXMT 0x01 /* Auto Pad Transmit */ 70 71 /* 3: Transmit Frame Status (XMTFS) */ 72 #define XMTSV 0x80 /* Transmit Status Valid */ 73 #define UFLO 0x40 /* Underflow */ 74 #define LCOL 0x20 /* Late Collision */ 75 #define MORE 0x10 /* More than one retry needed */ 76 #define ONE 0x08 /* Exactly one retry needed */ 77 #define DEFER 0x04 /* Transmission deferred */ 78 #define LCAR 0x02 /* Loss of Carrier */ 79 #define RTRY 0x01 /* Retry Error */ 80 81 /* 4: Transmit Retry Count (XMTRC) */ 82 #define EXDEF 0x80 /* Excessive Defer */ 83 #define XMTRC 0x0f /* Transmit Retry Count */ 84 85 /* 5: Receive Frame Control (RCVFC) */ 86 #define LLRCV 0x08 /* Low Latency Receive */ 87 #define MR 0x04 /* Match/Reject */ 88 #define ASTRPRCV 0x01 /* Auto Strip Receive */ 89 90 /* 6: Receive Frame Status (RCVFS) */ 91 /* 4 byte register; read 4 times to get all of the bytes */ 92 /* Read 1: RFS0 - Receive Message Byte Count [7-0] (RCVCNT) */ 93 94 /* Read 2: RFS1 - Receive Status (RCVSTS) */ 95 #define OFLO 0x80 /* Overflow flag */ 96 #define CLSN 0x40 /* Collision flag */ 97 #define FRAM 0x20 /* Framing Error flag */ 98 #define FCS 0x10 /* FCS Error flag */ 99 #define RCVCNT 0x0f /* Receive Message Byte Count [11-8] */ 100 101 /* Read 3: RFS2 - Runt Packet Count (RNTPC) [7-0] */ 102 103 /* Read 4: RFS3 - Receive Collision Count (RCVCC) [7-0] */ 104 105 /* 7: FIFO Frame Count (FIFOFC) */ 106 #define RCVFC 0xf0 /* Receive Frame Count */ 107 #define XMTFC 0x0f /* Transmit Frame Count */ 108 109 /* 8: Interrupt Register (IR) */ 110 #define JAB 0x80 /* Jabber Error */ 111 #define BABL 0x40 /* Babble Error */ 112 #define CERR 0x20 /* Collision Error */ 113 #define RCVCCO 0x10 /* Receive Collision Count Overflow */ 114 #define RNTPCO 0x08 /* Runt Packet Count Overflow */ 115 #define MPCO 0x04 /* Missed Packet Count Overflow */ 116 #define RCVINT 0x02 /* Receive Interrupt */ 117 #define XMTINT 0x01 /* Transmit Interrupt */ 118 119 /* 9: Interrupt Mask Register (IMR) */ 120 #define JABM 0x80 /* Jabber Error Mask */ 121 #define BABLM 0x40 /* Babble Error Mask */ 122 #define CERRM 0x20 /* Collision Error Mask */ 123 #define RCVCCOM 0x10 /* Receive Collision Count Overflow Mask */ 124 #define RNTPCOM 0x08 /* Runt Packet Count Overflow Mask */ 125 #define MPCOM 0x04 /* Missed Packet Count Overflow Mask */ 126 #define RCVINTM 0x02 /* Receive Interrupt Mask */ 127 #define XMTINTM 0x01 /* Transmit Interrupt Mask */ 128 129 /* 10: Poll Register (PR) */ 130 #define XMTSV 0x80 /* Transmit Status Valid */ 131 #define TDTREQ 0x40 /* Transmit Data Transfer Request */ 132 #define RDTREQ 0x20 /* Receive Data Transfer Request */ 133 134 /* 11: BIU Configuration Control (BIUCC) */ 135 #define BSWP 0x40 /* Byte Swap */ 136 #define XMTSP 0x30 /* Transmit Start Point */ 137 #define XMTSP_4 0x00 /* 4 bytes */ 138 #define XMTSP_16 0x10 /* 16 bytes */ 139 #define XMTSP_64 0x20 /* 64 bytes */ 140 #define XMTSP_112 0x30 /* 112 bytes */ 141 #define SWRST 0x01 /* Software Reset */ 142 143 /* 12: FIFO Configuration Control (FIFOCC) */ 144 #define XMTFW 0xc0 /* Transmit FIFO Watermark */ 145 #define XMTFW_8 0x00 /* 8 write cycles */ 146 #define XMTFW_16 0x40 /* 16 write cycles */ 147 #define XMTFW_32 0x80 /* 32 write cycles */ 148 #define RCVFW 0x30 /* Receive FIFO Watermark */ 149 #define RCVFW_16 0x00 /* 16 bytes */ 150 #define RCVFW_32 0x10 /* 32 bytes */ 151 #define RCVFW_64 0x20 /* 64 bytes */ 152 #define XMTFWU 0x08 /* Transmit FIFO Watermark Update */ 153 #define RCVFWU 0x04 /* Receive FIFO Watermark Update */ 154 #define XMTBRST 0x02 /* Transmit Burst */ 155 #define RCVBRST 0x01 /* Receive Burst */ 156 157 /* 13: MAC Configuration (MACCC) */ 158 #define PROM 0x80 /* Promiscuous */ 159 #define DXMT2PD 0x40 /* Disable Transmit Two Part Deferral */ 160 #define EMBA 0x20 /* Enable Modified Back-off Algorithm */ 161 #define DRCVPA 0x08 /* Disable Receive Physical Address */ 162 #define DRCVBC 0x04 /* Disable Receive Broadcast */ 163 #define ENXMT 0x02 /* Enable Transmit */ 164 #define ENRCV 0x01 /* Enable Receive */ 165 166 /* 14: PLS Configuration Control (PLSCC) */ 167 #define XMTSEL 0x08 /* Transmit Mode Select */ 168 #define PORTSEL 0x06 /* Port Select */ 169 #define PORTSEL_AUI 0x00 /* Select AUI */ 170 #define PORTSEL_10BT 0x02 /* Select 10BASE-T */ 171 #define PORTSEL_DAI 0x04 /* Select DAI port */ 172 #define PORTSEL_GPSI 0x06 /* Select GPSI */ 173 #define ENPLSIO 0x01 /* Enable PLS I/O */ 174 175 /* 15: PHY Configuration (PHYCC) */ 176 #define LNKFL 0x80 /* Link Fail */ 177 #define DLNKTST 0x40 /* Disable Link Test */ 178 #define REVPOL 0x20 /* Reversed Polarity */ 179 #define DAPC 0x10 /* Disable Auto Polarity Correction */ 180 #define LRT 0x08 /* Low Receive Threshold */ 181 #define ASEL 0x04 /* Auto Select */ 182 #define RWAKE 0x02 /* Remote Wake */ 183 #define AWAKE 0x01 /* Auto Wake */ 184 185 /* 18: Internal Address Configuration (IAC) */ 186 #define ADDRCHG 0x80 /* Address Change */ 187 #define PHYADDR 0x04 /* Physical Address Reset */ 188 #define LOGADDR 0x02 /* Logical Address Reset */ 189 190 /* 28: User Test Register (UTR) */ 191 #define RTRE 0x80 /* Reserved Test Register Enable */ 192 #define RTRD 0x40 /* Reserved Test Register Disable */ 193 #define RPA 0x20 /* Run Packet Accept */ 194 #define FCOLL 0x10 /* Force Collision */ 195 #define RCVFCSE 0x08 /* Receive FCS Enable */ 196 #define LOOP 0x06 /* Loopback Control */ 197 #define LOOP_NONE 0x00 /* No Loopback */ 198 #define LOOP_EXT 0x02 /* External Loopback */ 199 #define LOOP_INT 0x04 /* Internal Loopback, excludes MENDEC */ 200 #define LOOP_INT_MENDEC 0x06 /* Internal Loopback, includes MENDEC */ 201