1 /*        $NetBSD: cacheops_40.h,v 1.12 2023/12/27 17:35:35 thorpej Exp $       */
2 
3 /*-
4  * Copyright (c) 1997 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by Leo Weppelman
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #include <machine/fcode.h>
33 
34 /*
35  * Invalidate entire TLB.
36  */
37 static __inline void __attribute__((__unused__))
TBIA_40(void)38 TBIA_40(void)
39 {
40           __asm volatile (" .word 0xf518" ); /*  pflusha */
41 }
42 
43 /*
44  * Invalidate any TLB entry for given VA (TB Invalidate Single)
45  */
46 static __inline void __attribute__((__unused__))
TBIS_40(vaddr_t va)47 TBIS_40(vaddr_t va)
48 {
49           register uint8_t *r_va __asm("%a0") = (void *)va;
50           int       tmp;
51 
52           __asm volatile (" movc   %1, %%dfc;"    /* select supervisor          */
53                                 " .word 0xf508;"  /* pflush %a0@                */
54                                 " moveq  %3, %1;" /* select user                */
55                                 " movc   %1, %%dfc;"
56                                 " .word 0xf508;" : "=d" (tmp) :
57                                 "0" (FC_SUPERD), "a" (r_va), "i" (FC_USERD));
58 }
59 
60 /*
61  * Invalidate supervisor side of TLB
62  */
63 static __inline void __attribute__((__unused__))
TBIAS_40(void)64 TBIAS_40(void)
65 {
66           /*
67            * Cannot specify supervisor/user on pflusha, so we flush all
68            */
69           __asm volatile (" .word 0xf518;");
70 }
71 
72 /*
73  * Invalidate user side of TLB
74  */
75 static __inline void __attribute__((__unused__))
TBIAU_40(void)76 TBIAU_40(void)
77 {
78           /*
79            * Cannot specify supervisor/user on pflusha, so we flush all
80            */
81           __asm volatile (" .word 0xf518;");
82 }
83 
84 /*
85  * Invalidate instruction cache
86  */
87 static __inline void __attribute__((__unused__))
ICIA_40(void)88 ICIA_40(void)
89 {
90           __asm volatile (" .word 0xf498;"); /* cinva ic */
91 }
92 
93 static __inline void __attribute__((__unused__))
ICPA_40(void)94 ICPA_40(void)
95 {
96           __asm volatile (" .word 0xf498;"); /* cinva ic */
97 }
98 
99 /*
100  * Invalidate data cache.
101  */
102 static __inline void __attribute__((__unused__))
DCIA_40(void)103 DCIA_40(void)
104 {
105           __asm volatile (" .word 0xf478;"); /* cpusha dc */
106 }
107 
108 static __inline void __attribute__((__unused__))
DCIS_40(void)109 DCIS_40(void)
110 {
111           __asm volatile (" .word 0xf478;"); /* cpusha dc */
112 }
113 
114 static __inline void __attribute__((__unused__))
DCIU_40(void)115 DCIU_40(void)
116 {
117           __asm volatile (" .word 0xf478;"); /* cpusha dc */
118 }
119 
120 static __inline void __attribute__((__unused__))
DCIAS_40(paddr_t pa)121 DCIAS_40(paddr_t pa)
122 {
123           register uint8_t *r_pa __asm("%a0") = (void *)pa;
124 
125           __asm volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */
126 }
127 
128 static __inline void __attribute__((__unused__))
PCIA_40(void)129 PCIA_40(void)
130 {
131           __asm volatile (" .word 0xf478;"); /* cpusha dc */
132 }
133 
134 static __inline void __attribute__((__unused__))
DCFA_40(void)135 DCFA_40(void)
136 {
137           __asm volatile (" .word 0xf478;"); /* cpusha dc */
138 }
139 
140 /* invalidate instruction physical cache line */
141 static __inline void __attribute__((__unused__))
ICPL_40(paddr_t pa)142 ICPL_40(paddr_t pa)
143 {
144           register uint8_t *r_pa __asm("%a0") = (void *)pa;
145 
146           __asm volatile (" .word 0xf488;" : : "a" (r_pa)); /* cinvl ic,%a0@ */
147 }
148 
149 /* invalidate instruction physical cache page */
150 static __inline void __attribute__((__unused__))
ICPP_40(paddr_t pa)151 ICPP_40(paddr_t pa)
152 {
153           register uint8_t *r_pa __asm("%a0") = (void *)pa;
154 
155           __asm volatile (" .word 0xf490;" : : "a" (r_pa)); /* cinvp ic,%a0@ */
156 }
157 
158 /* invalidate data physical cache line */
159 static __inline void __attribute__((__unused__))
DCPL_40(paddr_t pa)160 DCPL_40(paddr_t pa)
161 {
162           register uint8_t *r_pa __asm("%a0") = (void *)pa;
163 
164           __asm volatile (" .word 0xf448;" : : "a" (r_pa)); /* cinvl dc,%a0@ */
165 }
166 
167 /* invalidate data physical cache page */
168 static __inline void __attribute__((__unused__))
DCPP_40(paddr_t pa)169 DCPP_40(paddr_t pa)
170 {
171           register uint8_t *r_pa __asm("%a0") = (void *)pa;
172 
173           __asm volatile (" .word 0xf450;" : : "a" (r_pa)); /* cinvp dc,%a0@ */
174 }
175 
176 /* invalidate data physical all */
177 static __inline void __attribute__((__unused__))
DCPA_40(void)178 DCPA_40(void)
179 {
180           __asm volatile (" .word 0xf458;"); /* cinva dc */
181 }
182 
183 /* data cache flush line */
184 static __inline void __attribute__((__unused__))
DCFL_40(paddr_t pa)185 DCFL_40(paddr_t pa)
186 {
187           register uint8_t *r_pa __asm("%a0") = (void *)pa;
188 
189           __asm volatile (" .word 0xf468;" : : "a" (r_pa)); /* cpushl dc,%a0@ */
190 }
191 
192 /* data cache flush page */
193 static __inline void __attribute__((__unused__))
DCFP_40(paddr_t pa)194 DCFP_40(paddr_t pa)
195 {
196           register uint8_t *r_pa __asm("%a0") = (void *)pa;
197 
198           __asm volatile (" .word 0xf470;" : : "a" (r_pa)); /* cpushp dc,%a0@ */
199 }
200