1 /*        $NetBSD: intr.h,v 1.4 2023/07/12 06:45:24 mrg Exp $         */
2 /*        $OpenBSD: intr.h,v 1.26 2009/12/29 13:11:40 jsing Exp $     */
3 
4 /*-
5  * Copyright (c) 1998, 2001, 2002 The NetBSD Foundation, Inc.
6  * All rights reserved.
7  *
8  * This code is derived from software contributed to The NetBSD Foundation
9  * by Charles M. Hannum, and by Jason R. Thorpe, and by Matthew Fredette.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer.
16  * 2. Redistributions in binary form must reproduce the above copyright
17  *    notice, this list of conditions and the following disclaimer in the
18  *    documentation and/or other materials provided with the distribution.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30  * POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef _HPPA_INTR_H_
34 #define _HPPA_INTR_H_
35 
36 #include <machine/psl.h>
37 #include <machine/intrdefs.h>
38 
39 #include <sys/evcnt.h>
40 
41 #ifndef _LOCORE
42 
43 #if defined(_KERNEL) || defined(_KMEMUSER)
44 typedef int ipl_t;
45 typedef struct {
46           ipl_t _ipl;
47 } ipl_cookie_t;
48 #endif
49 
50 #ifdef _KERNEL
51 
52 struct cpu_info;
53 
54 /*
55  * The maximum number of bits in a cpl value/spl mask, the maximum number of
56  * bits in an interrupt request register, and the maximum number of interrupt
57  * registers.
58  */
59 #define   HPPA_INTERRUPT_BITS (32)
60 #define   CPU_NINTS           HPPA_INTERRUPT_BITS /* Use this one */
61 
62 /*
63  * This describes one HPPA interrupt register.
64  */
65 struct hppa_interrupt_register {
66           bool ir_iscpu;
67           const char *ir_name;                    /* name for this intr reg */
68           struct cpu_info *ir_ci;                 /* cpu this intr reg  */
69 
70           /*
71            * The virtual address of the mask, request and level
72            * registers.
73            */
74           volatile int *ir_mask;
75           volatile int *ir_req;
76           volatile int *ir_level;
77 
78           /*
79            * This array has one entry for each bit in the interrupt request
80            * register.
81            *
82            * If the 24 most significant bits are set, the low 8 bits are the
83            * index of the hppa_interrupt_register that this interrupt bit leads
84            * to, with zero meaning that the interrupt bit is unused.
85            *
86            * Otherwise these bits correspond to hppa_interrupt_bits. That is,
87            * these bits are ORed to ipending_new in hppa_intr_ipending() when
88            * an interrupt happens.
89            *
90            * Note that this array is indexed by HP bit number, *not* by "normal"
91            * bit number.  In other words, the least significant bit in the inter-
92            * rupt register corresponds to array index 31.
93            */
94 
95           unsigned int ir_bits_map[HPPA_INTERRUPT_BITS];
96 
97 #define   IR_BIT_MASK                   0xffffff00
98 #define   IR_BIT_REG(x)                 (IR_BIT_MASK | (x))
99 #define   IR_BIT_UNUSED                 IR_BIT_REG(0)
100 #define   IR_BIT_USED_P(x)    (((x) & IR_BIT_MASK) != IR_BIT_MASK)
101 #define   IR_BIT_NESTED_P(x)  (((x) & IR_BIT_MASK) == IR_BIT_MASK)
102 /* true if not used for interrupt or nested interrupt register */
103 #define   IR_BIT_UNUSED_P(x)  ((x) == IR_BIT_MASK)
104 
105           int ir_bits;                  /* mask of allocatable bit numbers */
106           int ir_rbits;                 /* mask of reserved (for lasi/asp) bit numbers */
107 };
108 
109 struct hppa_interrupt_bit {
110 
111           /*
112            * The interrupt register this bit is in.  Some handlers, e.g
113            * apic_intr, don't make use of an hppa_interrupt_register, but are
114            * nested.
115            */
116           struct hppa_interrupt_register *ib_reg;
117 
118           /*
119            * The priority level associated with this bit, e.g, IPL_BIO, IPL_NET,
120            * etc.
121            */
122           int ib_ipl;
123 
124           /*
125            * The spl mask for this bit.  This starts out as the spl bit assigned
126            * to this particular interrupt, and later gets fleshed out by the mask
127            * calculator to be the full mask that we need to raise spl to when we
128            * get this interrupt.
129            */
130           int ib_spl;
131 
132           /* The interrupt name. */
133           char ib_name[16];
134 
135           /* The interrupt event count. */
136           struct evcnt ib_evcnt;
137 
138           /*
139            * The interrupt handler and argument for this bit.  If the argument is
140            * NULL, the handler gets the trapframe.
141            */
142           int (*ib_handler)(void *);
143           void *ib_arg;
144 
145 };
146 
147 void      hppa_intr_bootstrap(void);
148 void      hppa_intr_initialise(struct cpu_info *);
149 void      hppa_interrupt_register_establish(struct cpu_info *,
150     struct hppa_interrupt_register *);
151 void *    hppa_intr_establish(int, int (*)(void *), void *,
152     struct hppa_interrupt_register *, int);
153 int       hppa_intr_allocate_bit(struct hppa_interrupt_register *, int);
154 void      hppa_intr_enable(void);
155 
156 /* splraise()/spllower() are in locore.S */
157 int splraise(int);
158 void spllower(int);
159 
160 /*
161  * Miscellaneous
162  */
163 #define   spl0()              spllower(0)
164 #define   splx(x)             spllower(x)
165 
166 static inline ipl_cookie_t
makeiplcookie(ipl_t ipl)167 makeiplcookie(ipl_t ipl)
168 {
169 
170           return (ipl_cookie_t){._ipl = ipl};
171 }
172 
173 static inline int
splraiseipl(ipl_cookie_t icookie)174 splraiseipl(ipl_cookie_t icookie)
175 {
176 
177           return splraise(icookie._ipl);
178 }
179 
180 #include <sys/spl.h>
181 #endif
182 
183 #define   setsoftast(l)       ((l)->l_md.md_astpending = 1)
184 
185 #ifdef MULTIPROCESSOR
186 
187 struct cpu_info;
188 
189 void       hppa_ipi_init(struct cpu_info *);
190 int        hppa_ipi_intr(void *arg);
191 int        hppa_ipi_send(struct cpu_info *, u_long);
192 int        hppa_ipi_broadcast(u_long);
193 #endif
194 
195 #endif /* !_LOCORE */
196 
197 #endif /* !_HPPA_INTR_H_ */
198