1 /* $NetBSD: it8368.c,v 1.28 2023/12/08 22:11:15 andvar Exp $ */
2
3 /*-
4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by UCHIYAMA Yasushi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: it8368.c,v 1.28 2023/12/08 22:11:15 andvar Exp $");
34
35 #undef WINCE_DEFAULT_SETTING /* for debug */
36 #undef IT8368DEBUG
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/device.h>
41
42 #include <machine/bus.h>
43
44 #include <dev/pcmcia/pcmciareg.h>
45 #include <dev/pcmcia/pcmciavar.h>
46 #include <dev/pcmcia/pcmciachip.h>
47
48 #include <hpcmips/tx/tx39var.h>
49 #include <hpcmips/tx/txcsbusvar.h>
50 #include <hpcmips/tx/tx39biureg.h> /* legacy mode requires BIU access */
51 #include <hpcmips/dev/it8368var.h>
52 #include <hpcmips/dev/it8368reg.h>
53
54 #ifdef IT8368DEBUG
55 int it8368debug = 1;
56 #define DPRINTF(arg) if (it8368debug) printf arg;
57 #define DPRINTFN(n, arg) if (it8368debug > (n)) printf arg;
58 #else
59 #define DPRINTF(arg)
60 #define DPRINTFN(n, arg)
61 #endif
62
63 int it8368e_match(device_t, cfdata_t, void *);
64 void it8368e_attach(device_t, device_t, void *);
65 int it8368_print(void *, const char *);
66
67 #define IT8368_LASTSTATE_PRESENT 0x0002
68 #define IT8368_LASTSTATE_HALF 0x0001
69 #define IT8368_LASTSTATE_EMPTY 0x0000
70
71 struct it8368e_softc {
72 device_t sc_dev;
73 device_t sc_pcmcia;
74 tx_chipset_tag_t sc_tc;
75
76 /* Register space */
77 bus_space_tag_t sc_csregt;
78 bus_space_handle_t sc_csregh;
79 /* I/O, attribute space */
80 bus_space_tag_t sc_csiot;
81 bus_addr_t sc_csiobase;
82 bus_size_t sc_csiosize;
83 /*
84 * XXX theses means attribute memory. not memory space.
85 * memory space is 0x64000000.
86 */
87 bus_space_tag_t sc_csmemt;
88 bus_addr_t sc_csmembase;
89 bus_size_t sc_csmemsize;
90
91 /* Separate I/O and attribute space mode */
92 int sc_fixattr;
93
94 /* Card interrupt handler */
95 int (*sc_card_fun)(void *);
96 void *sc_card_arg;
97 void *sc_card_ih;
98 int sc_card_irq;
99
100 /* Card status change */
101 int sc_irq;
102 void *sc_ih;
103 int sc_laststate;
104 };
105
106 void it8368_init_socket(struct it8368e_softc*);
107 void it8368_attach_socket(struct it8368e_softc *);
108 int it8368_intr(void *);
109 int it8368_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
110 struct pcmcia_mem_handle *);
111 void it8368_chip_mem_free(pcmcia_chipset_handle_t, struct pcmcia_mem_handle *);
112 int it8368_chip_mem_map(pcmcia_chipset_handle_t, int, bus_size_t, bus_size_t,
113 struct pcmcia_mem_handle *, bus_addr_t *, int *);
114 void it8368_chip_mem_unmap(pcmcia_chipset_handle_t, int);
115 int it8368_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, bus_size_t,
116 bus_size_t, struct pcmcia_io_handle *);
117 void it8368_chip_io_free(pcmcia_chipset_handle_t, struct pcmcia_io_handle *);
118 int it8368_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, bus_size_t,
119 struct pcmcia_io_handle *, int *);
120 void it8368_chip_io_unmap(pcmcia_chipset_handle_t, int);
121 void it8368_chip_socket_enable(pcmcia_chipset_handle_t);
122 void it8368_chip_socket_disable(pcmcia_chipset_handle_t);
123 void *it8368_chip_intr_establish(pcmcia_chipset_handle_t,
124 struct pcmcia_function *, int, int (*) (void *), void *);
125 void it8368_chip_intr_disestablish(pcmcia_chipset_handle_t, void *);
126
127 #ifdef IT8368DEBUG
128 void it8368_dump(struct it8368e_softc *);
129 #endif
130
131 static struct pcmcia_chip_functions it8368_functions = {
132 it8368_chip_mem_alloc,
133 it8368_chip_mem_free,
134 it8368_chip_mem_map,
135 it8368_chip_mem_unmap,
136 it8368_chip_io_alloc,
137 it8368_chip_io_free,
138 it8368_chip_io_map,
139 it8368_chip_io_unmap,
140 it8368_chip_intr_establish,
141 it8368_chip_intr_disestablish,
142 it8368_chip_socket_enable,
143 it8368_chip_socket_disable
144 };
145
146 CFATTACH_DECL_NEW(it8368e, sizeof(struct it8368e_softc),
147 it8368e_match, it8368e_attach, NULL, NULL);
148
149 /*
150 * IT8368 configuration register is big-endian.
151 */
152 static inline u_int16_t it8368_reg_read(bus_space_tag_t,
153 bus_space_handle_t, int);
154 static inline void it8368_reg_write(bus_space_tag_t, bus_space_handle_t,
155 int, u_int16_t);
156
157 #ifdef IT8368E_DESTRUCTIVE_CHECK
158 int it8368e_id_check(void *);
159
160 /*
161 * IT8368E don't have identification method. this is destructive check.
162 */
163 int
it8368e_id_check(void * aux)164 it8368e_id_check(void *aux)
165 {
166 struct cs_attach_args *ca = aux;
167 tx_chipset_tag_t tc;
168 bus_space_tag_t csregt;
169 bus_space_handle_t csregh;
170 u_int16_t oreg, reg;
171 int match = 0;
172
173 tc = ca->ca_tc;
174 csregt = ca->ca_csreg.cstag;
175
176 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize,
177 0, &csregh);
178 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
179 oreg = reg;
180 dbg_bit_print(reg);
181
182 reg &= ~IT8368_CTRL_BYTESWAP;
183 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
184 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
185 if (reg & IT8368_CTRL_BYTESWAP)
186 goto nomatch;
187
188 reg |= IT8368_CTRL_BYTESWAP;
189 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
190 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
191 if (!(reg & IT8368_CTRL_BYTESWAP))
192 goto nomatch;
193
194 match = 1;
195 nomatch:
196 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, oreg);
197 bus_space_unmap(csregt, csregh, ca->ca_csreg.cssize);
198
199 return (match);
200 }
201 #endif /* IT8368E_DESTRUCTIVE_CHECK */
202
203 int
it8368e_match(device_t parent,cfdata_t cf,void * aux)204 it8368e_match(device_t parent, cfdata_t cf, void *aux)
205 {
206 #ifdef IT8368E_DESTRUCTIVE_CHECK
207 return (it8368e_id_check(aux));
208 #else
209 return (1);
210 #endif
211 }
212
213 void
it8368e_attach(device_t parent,device_t self,void * aux)214 it8368e_attach(device_t parent, device_t self, void *aux)
215 {
216 struct cs_attach_args *ca = aux;
217 struct it8368e_softc *sc = device_private(self);
218 tx_chipset_tag_t tc;
219 bus_space_tag_t csregt;
220 bus_space_handle_t csregh;
221 u_int16_t reg;
222
223 sc->sc_dev = self;
224 sc->sc_tc = tc = ca->ca_tc;
225 sc->sc_csregt = csregt = ca->ca_csreg.cstag;
226
227 bus_space_map(csregt, ca->ca_csreg.csbase, ca->ca_csreg.cssize,
228 0, &sc->sc_csregh);
229 csregh = sc->sc_csregh;
230 sc->sc_csiot = ca->ca_csio.cstag;
231 sc->sc_csiobase = ca->ca_csio.csbase;
232 sc->sc_csiosize = ca->ca_csio.cssize;
233
234 #ifdef IT8368DEBUG
235 printf("\n\t[Windows CE setting]\n");
236 it8368_dump(sc); /* print WindowsCE setting */
237 #endif
238 /* LHA[14:13] <= HA[14:13] */
239 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
240 reg &= ~IT8368_CTRL_ADDRSEL;
241 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
242
243 /* Set all MFIO direction as LHA[23:13] output pins */
244 reg = it8368_reg_read(csregt, csregh, IT8368_MFIODIR_REG);
245 reg |= IT8368_MFIODIR_MASK;
246 it8368_reg_write(csregt, csregh, IT8368_MFIODIR_REG, reg);
247
248 /* Set all MFIO functions as LHA */
249 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOSEL_REG);
250 reg &= ~IT8368_MFIOSEL_MASK;
251 it8368_reg_write(csregt, csregh, IT8368_MFIOSEL_REG, reg);
252
253 /* Disable MFIO interrupt */
254 reg = it8368_reg_read(csregt, csregh, IT8368_MFIOPOSINTEN_REG);
255 reg &= ~IT8368_MFIOPOSINTEN_MASK;
256 it8368_reg_write(csregt, csregh, IT8368_MFIOPOSINTEN_REG, reg);
257 reg = it8368_reg_read(csregt, csregh, IT8368_MFIONEGINTEN_REG);
258 reg &= ~IT8368_MFIONEGINTEN_MASK;
259 it8368_reg_write(csregt, csregh, IT8368_MFIONEGINTEN_REG, reg);
260
261 /* Port direction */
262 reg = IT8368_PIN_CRDVCCON1 | IT8368_PIN_CRDVCCON0 |
263 IT8368_PIN_CRDVPPON1 | IT8368_PIN_CRDVPPON0 |
264 IT8368_PIN_BCRDRST;
265 it8368_reg_write(csregt, csregh, IT8368_GPIODIR_REG, reg);
266 printf("\n");
267
268 /*
269 * Separate I/O and attribute memory region
270 */
271 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
272
273 reg |= IT8368_CTRL_FIXATTRIO;
274 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
275
276 if (IT8368_CTRL_FIXATTRIO &
277 it8368_reg_read(csregt, csregh, IT8368_CTRL_REG)) {
278 sc->sc_fixattr = 1;
279 printf("%s: fix attr mode\n", device_xname(sc->sc_dev));
280 } else {
281 sc->sc_fixattr = 0;
282 printf("%s: legacy attr mode\n", device_xname(sc->sc_dev));
283 }
284
285 sc->sc_csmemt = sc->sc_csiot;
286 sc->sc_csiosize /= 2;
287 sc->sc_csmemsize = sc->sc_csiosize;
288 sc->sc_csmembase = sc->sc_csiosize;
289
290 #ifdef IT8368DEBUG
291 it8368_dump(sc);
292 #endif
293 /* Enable card and interrupt driving. */
294 reg = it8368_reg_read(csregt, csregh, IT8368_CTRL_REG);
295 reg |= (IT8368_CTRL_GLOBALEN | IT8368_CTRL_CARDEN);
296 if (sc->sc_fixattr)
297 reg |= IT8368_CTRL_FIXATTRIO;
298 it8368_reg_write(csregt, csregh, IT8368_CTRL_REG, reg);
299
300 sc->sc_irq = ca->ca_irq1;
301 sc->sc_card_irq = ca->ca_irq3;
302
303 it8368_attach_socket(sc);
304 }
305
306 inline u_int16_t
it8368_reg_read(bus_space_tag_t t,bus_space_handle_t h,int ofs)307 it8368_reg_read(bus_space_tag_t t, bus_space_handle_t h, int ofs)
308 {
309 u_int16_t val;
310
311 val = bus_space_read_2(t, h, ofs);
312 return (0xffff & (((val >> 8) & 0xff)|((val << 8) & 0xff00)));
313 }
314
315 inline void
it8368_reg_write(bus_space_tag_t t,bus_space_handle_t h,int ofs,u_int16_t v)316 it8368_reg_write(bus_space_tag_t t, bus_space_handle_t h, int ofs, u_int16_t v)
317 {
318 u_int16_t val;
319
320 val = 0xffff & (((v >> 8) & 0xff)|((v << 8) & 0xff00));
321 bus_space_write_2(t, h, ofs, val);
322 }
323
324 int
it8368_intr(void * arg)325 it8368_intr(void *arg)
326 {
327 struct it8368e_softc *sc = arg;
328 bus_space_tag_t csregt = sc->sc_csregt;
329 bus_space_handle_t csregh = sc->sc_csregh;
330 u_int16_t reg;
331
332 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTSTAT_REG);
333
334 if (reg & IT8368_PIN_BCRDRDY) {
335 if (sc->sc_card_fun) {
336 /* clear interrupt */
337 it8368_reg_write(csregt, csregh,
338 IT8368_GPIONEGINTSTAT_REG,
339 IT8368_PIN_BCRDRDY);
340
341 /* Dispatch card interrupt handler */
342 (*sc->sc_card_fun)(sc->sc_card_arg);
343 }
344 } else if (reg & IT8368_PIN_CRDDET2) {
345 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
346 IT8368_PIN_CRDDET2);
347 printf("[CSC]\n");
348 #ifdef IT8368DEBUG
349 it8368_dump(sc);
350 #endif
351 it8368_chip_socket_disable(sc);
352 } else {
353 #ifdef IT8368DEBUG
354 u_int16_t reg2;
355 reg2 = reg & ~(IT8368_PIN_BCRDRDY|IT8368_PIN_CRDDET2);
356 printf("unknown it8368 interrupt: ");
357 dbg_bit_print(reg2);
358 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTSTAT_REG,
359 reg);
360 #endif
361 }
362
363 return (0);
364 }
365
366 int
it8368_print(void * arg,const char * pnp)367 it8368_print(void *arg, const char *pnp)
368 {
369 if (pnp)
370 aprint_normal("pcmcia at %s", pnp);
371
372 return (UNCONF);
373 }
374
375 void
it8368_attach_socket(struct it8368e_softc * sc)376 it8368_attach_socket(struct it8368e_softc *sc)
377 {
378 struct pcmciabus_attach_args paa;
379
380 paa.paa_busname = "pcmcia";
381 paa.pct = (pcmcia_chipset_tag_t)&it8368_functions;
382 paa.pch = (pcmcia_chipset_handle_t)sc;
383
384 if ((sc->sc_pcmcia = config_found(sc->sc_dev, &paa, it8368_print,
385 CFARGS_NONE))) {
386 it8368_init_socket(sc);
387 }
388 }
389
390 void
it8368_init_socket(struct it8368e_softc * sc)391 it8368_init_socket(struct it8368e_softc *sc)
392 {
393 bus_space_tag_t csregt = sc->sc_csregt;
394 bus_space_handle_t csregh = sc->sc_csregh;
395 u_int16_t reg;
396
397 /*
398 * set up the card to interrupt on card detect
399 */
400 reg = IT8368_PIN_CRDDET2; /* CSC */
401 /* enable negative edge */
402 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
403 /* disable positive edge */
404 it8368_reg_write(csregt, csregh, IT8368_GPIOPOSINTEN_REG, 0);
405
406 sc->sc_ih = tx_intr_establish(sc->sc_tc, sc->sc_irq,
407 IST_EDGE, IPL_BIO, it8368_intr, sc);
408 if (sc->sc_ih == NULL) {
409 printf("%s: can't establish interrupt\n",
410 device_xname(sc->sc_dev));
411 return;
412 }
413
414 /*
415 * if there's a card there, then attach it.
416 */
417 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG);
418
419 if (reg & (IT8368_PIN_CRDDET2|IT8368_PIN_CRDDET1)) {
420 sc->sc_laststate = IT8368_LASTSTATE_EMPTY;
421 } else {
422 pcmcia_card_attach(sc->sc_pcmcia);
423 sc->sc_laststate = IT8368_LASTSTATE_PRESENT;
424 }
425 }
426
427 void *
it8368_chip_intr_establish(pcmcia_chipset_handle_t pch,struct pcmcia_function * pf,int ipl,int (* ih_fun)(void *),void * ih_arg)428 it8368_chip_intr_establish(pcmcia_chipset_handle_t pch,
429 struct pcmcia_function *pf, int ipl, int (*ih_fun)(void *), void *ih_arg)
430 {
431 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
432 bus_space_tag_t csregt = sc->sc_csregt;
433 bus_space_handle_t csregh = sc->sc_csregh;
434 u_int16_t reg;
435
436 if (sc->sc_card_fun)
437 panic("it8368_chip_intr_establish: "
438 "duplicate card interrupt handler.");
439
440 sc->sc_card_fun = ih_fun;
441 sc->sc_card_arg = ih_arg;
442
443 sc->sc_card_ih = tx_intr_establish(sc->sc_tc, sc->sc_card_irq,
444 IST_EDGE, IPL_BIO, it8368_intr,
445 sc);
446
447 /* enable card interrupt */
448 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);
449 reg |= IT8368_PIN_BCRDRDY;
450 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
451
452 return (sc->sc_card_ih);
453 }
454
455 void
it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch,void * ih)456 it8368_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih)
457 {
458 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
459 bus_space_tag_t csregt = sc->sc_csregt;
460 bus_space_handle_t csregh = sc->sc_csregh;
461 u_int16_t reg;
462
463 if (!sc->sc_card_fun)
464 panic("it8368_chip_intr_disestablish:"
465 "no handler established.");
466 assert(ih == sc->sc_card_ih);
467
468 sc->sc_card_fun = 0;
469 sc->sc_card_arg = 0;
470
471 /* disable card interrupt */
472 reg = it8368_reg_read(csregt, csregh, IT8368_GPIONEGINTEN_REG);
473 reg &= ~IT8368_PIN_BCRDRDY;
474 it8368_reg_write(csregt, csregh, IT8368_GPIONEGINTEN_REG, reg);
475
476 tx_intr_disestablish(sc->sc_tc, ih);
477 }
478
479 int
it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch,bus_size_t size,struct pcmcia_mem_handle * pcmhp)480 it8368_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size,
481 struct pcmcia_mem_handle *pcmhp)
482 {
483 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
484
485 if (bus_space_alloc(sc->sc_csmemt, sc->sc_csmembase,
486 sc->sc_csmembase + sc->sc_csmemsize, size,
487 size, 0, 0, 0, &pcmhp->memh)) {
488 DPRINTF(("it8368_chip_mem_alloc: failed\n"));
489 return (1);
490 }
491
492 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */
493 pcmhp->memh -= sc->sc_csmembase;
494
495 pcmhp->memt = sc->sc_csmemt;
496 pcmhp->addr = pcmhp->memh;
497 pcmhp->size = size;
498 pcmhp->realsize = size;
499
500 DPRINTF(("it8368_chip_mem_alloc: %#x+%#x\n",
501 (unsigned)pcmhp->memh, (unsigned)size));
502
503 return (0);
504 }
505
506 void
it8368_chip_mem_free(pcmcia_chipset_handle_t pch,struct pcmcia_mem_handle * pcmhp)507 it8368_chip_mem_free(pcmcia_chipset_handle_t pch,
508 struct pcmcia_mem_handle *pcmhp)
509 {
510 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
511
512 DPRINTF(("it8368_chip_mem_free: %#x+%#x\n",
513 (unsigned)pcmhp->memh, (unsigned)pcmhp->size));
514
515 if (!sc->sc_fixattr) /* XXX IT8368 brain damaged spec */
516 pcmhp->memh += sc->sc_csmembase;
517
518 bus_space_unmap(pcmhp->memt, pcmhp->memh, pcmhp->size);
519 }
520
521 int
it8368_chip_mem_map(pcmcia_chipset_handle_t pch,int kind,bus_addr_t card_addr,bus_size_t size,struct pcmcia_mem_handle * pcmhp,bus_size_t * offsetp,int * windowp)522 it8368_chip_mem_map(pcmcia_chipset_handle_t pch, int kind,
523 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp,
524 bus_size_t *offsetp, int *windowp)
525 {
526 /* attribute mode */
527 it8368_mode(pch, IT8368_ATTR_MODE, IT8368_WIDTH_16);
528
529 *offsetp = card_addr;
530 DPRINTF(("it8368_chip_mem_map %#x+%#x\n",
531 (unsigned)pcmhp->memh, (unsigned)size));
532
533 return (0);
534 }
535
536 void
it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch,int window)537 it8368_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window)
538 {
539 /* return to I/O mode */
540 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16);
541 }
542
543 void
it8368_mode(pcmcia_chipset_handle_t pch,int io,int width)544 it8368_mode(pcmcia_chipset_handle_t pch, int io, int width)
545 {
546 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
547 txreg_t reg32;
548
549 DPRINTF(("it8368_mode: change access space to "));
550 DPRINTF((io ? "I/O (%dbit)\n" : "attribute (%dbit)...\n",
551 width == IT8368_WIDTH_8 ? 8 : 16));
552
553 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
554
555 if (io) {
556 if (width == IT8368_WIDTH_8)
557 reg32 |= TX39_MEMCONFIG3_PORT8SEL;
558 else
559 reg32 &= ~TX39_MEMCONFIG3_PORT8SEL;
560 }
561
562 if (!sc->sc_fixattr) {
563 if (io)
564 reg32 |= TX39_MEMCONFIG3_CARD1IOEN;
565 else
566 reg32 &= ~TX39_MEMCONFIG3_CARD1IOEN;
567 }
568 tx_conf_write(sc->sc_tc, TX39_MEMCONFIG3_REG, reg32);
569
570 #ifdef IT8368DEBUG
571 if (sc->sc_fixattr)
572 return; /* No need to report BIU status */
573
574 /* check BIU status */
575 reg32 = tx_conf_read(sc->sc_tc, TX39_MEMCONFIG3_REG);
576 if (reg32 & TX39_MEMCONFIG3_CARD1IOEN) {
577 DPRINTF(("it8368_mode: I/O space (%dbit) enabled\n",
578 reg32 & TX39_MEMCONFIG3_PORT8SEL ? 8 : 16));
579 } else {
580 DPRINTF(("it8368_mode: attribute space enabled\n"));
581 }
582 #endif /* IT8368DEBUG */
583 }
584
585 int
it8368_chip_io_alloc(pcmcia_chipset_handle_t pch,bus_addr_t start,bus_size_t size,bus_size_t align,struct pcmcia_io_handle * pcihp)586 it8368_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start,
587 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp)
588 {
589 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
590
591 if (start) {
592 if (bus_space_map(sc->sc_csiot, start, size, 0,
593 &pcihp->ioh)) {
594 return (1);
595 }
596 DPRINTF(("it8368_chip_io_alloc map port %#x+%#x\n",
597 (unsigned)start, (unsigned)size));
598 } else {
599 if (bus_space_alloc(sc->sc_csiot, sc->sc_csiobase,
600 sc->sc_csiobase + sc->sc_csiosize,
601 size, align, 0, 0, &pcihp->addr,
602 &pcihp->ioh)) {
603
604 return (1);
605 }
606 pcihp->flags = PCMCIA_IO_ALLOCATED;
607 DPRINTF(("it8368_chip_io_alloc alloc %#x from %#x\n",
608 (unsigned)size, (unsigned)pcihp->addr));
609 }
610
611 pcihp->iot = sc->sc_csiot;
612 pcihp->size = size;
613
614 return (0);
615 }
616
617 int
it8368_chip_io_map(pcmcia_chipset_handle_t pch,int width,bus_addr_t offset,bus_size_t size,struct pcmcia_io_handle * pcihp,int * windowp)618 it8368_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset,
619 bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp)
620 {
621 /* I/O mode */
622 it8368_mode(pch, IT8368_IO_MODE, IT8368_WIDTH_16);
623
624 DPRINTF(("it8368_chip_io_map %#x:%#x+%#x\n",
625 (unsigned)pcihp->ioh, (unsigned)offset, (unsigned)size));
626
627 return (0);
628 }
629
630 void
it8368_chip_io_free(pcmcia_chipset_handle_t pch,struct pcmcia_io_handle * pcihp)631 it8368_chip_io_free(pcmcia_chipset_handle_t pch,
632 struct pcmcia_io_handle *pcihp)
633 {
634 if (pcihp->flags & PCMCIA_IO_ALLOCATED)
635 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size);
636 else
637 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size);
638
639 DPRINTF(("it8368_chip_io_free %#x+%#x\n",
640 (unsigned)pcihp->ioh, (unsigned)pcihp->size));
641 }
642
643 void
it8368_chip_io_unmap(pcmcia_chipset_handle_t pch,int window)644 it8368_chip_io_unmap(pcmcia_chipset_handle_t pch, int window)
645 {
646
647 }
648
649 void
it8368_chip_socket_enable(pcmcia_chipset_handle_t pch)650 it8368_chip_socket_enable(pcmcia_chipset_handle_t pch)
651 {
652 #ifndef WINCE_DEFAULT_SETTING
653 struct it8368e_softc *sc = (struct it8368e_softc*)pch;
654 bus_space_tag_t csregt = sc->sc_csregt;
655 bus_space_handle_t csregh = sc->sc_csregh;
656 volatile u_int16_t reg;
657
658 /* Power off */
659 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
660 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
661 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);
662 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
663 delay(20000);
664
665 /*
666 * wait 300ms until power fails (Tpf). Then, wait 100ms since
667 * we are changing Vcc (Toff).
668 */
669 delay((300 + 100) * 1000);
670
671 /* Supply Vcc */
672 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
673 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
674 reg |= IT8368_PIN_CRDVCC_5V; /* XXX */
675 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
676
677 /*
678 * wait 100ms until power raise (Tpr) and 20ms to become
679 * stable (Tsu(Vcc)).
680 *
681 * some machines require some more time to be settled
682 * (300ms is added here).
683 */
684 delay((100 + 20 + 300) * 1000);
685
686 /* Assert reset signal */
687 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
688 reg |= IT8368_PIN_BCRDRST;
689 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
690
691 /*
692 * hold RESET at least 10us.
693 */
694 delay(10);
695
696 /* deassert reset signal */
697 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
698 reg &= ~IT8368_PIN_BCRDRST;
699 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
700 delay(20000);
701
702 DPRINTF(("it8368_chip_socket_enable: socket enabled\n"));
703 #endif /* !WINCE_DEFAULT_SETTING */
704 }
705
706 void
it8368_chip_socket_disable(pcmcia_chipset_handle_t pch)707 it8368_chip_socket_disable(pcmcia_chipset_handle_t pch)
708 {
709 #ifndef WINCE_DEFAULT_SETTING
710 struct it8368e_softc *sc = (struct it8368e_softc*) pch;
711 bus_space_tag_t csregt = sc->sc_csregt;
712 bus_space_handle_t csregh = sc->sc_csregh;
713 u_int16_t reg;
714
715 /* Power down */
716 reg = it8368_reg_read(csregt, csregh, IT8368_GPIODATAOUT_REG);
717 reg &= ~(IT8368_PIN_CRDVCCMASK | IT8368_PIN_CRDVPPMASK);
718 reg |= (IT8368_PIN_CRDVCC_0V | IT8368_PIN_CRDVPP_0V);
719 it8368_reg_write(csregt, csregh, IT8368_GPIODATAOUT_REG, reg);
720 delay(20000);
721
722 /*
723 * wait 300ms until power fails (Tpf).
724 */
725 delay(300 * 1000);
726
727 DPRINTF(("it8368_chip_socket_disable: socket disabled\n"));
728 #endif /* !WINCE_DEFAULT_SETTING */
729 }
730
731 #ifdef IT8368DEBUG
732 #define PRINTGPIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \
733 IT8368_GPIO##m##_REG), 0, IT8368_GPIO_MAX, #m, DBG_BIT_PRINT_COUNT)
734 #define PRINTMFIO(m) __dbg_bit_print(it8368_reg_read(csregt, csregh, \
735 IT8368_MFIO##m##_REG), 0, IT8368_MFIO_MAX, #m, DBG_BIT_PRINT_COUNT)
736 void
it8368_dump(struct it8368e_softc * sc)737 it8368_dump(struct it8368e_softc *sc)
738 {
739 bus_space_tag_t csregt = sc->sc_csregt;
740 bus_space_handle_t csregh = sc->sc_csregh;
741
742 printf("[GPIO]\n");
743 PRINTGPIO(DIR);
744 PRINTGPIO(DATAIN);
745 PRINTGPIO(DATAOUT);
746 PRINTGPIO(POSINTEN);
747 PRINTGPIO(NEGINTEN);
748 PRINTGPIO(POSINTSTAT);
749 PRINTGPIO(NEGINTSTAT);
750 printf("[MFIO]\n");
751 PRINTMFIO(SEL);
752 PRINTMFIO(DIR);
753 PRINTMFIO(DATAIN);
754 PRINTMFIO(DATAOUT);
755 PRINTMFIO(POSINTEN);
756 PRINTMFIO(NEGINTEN);
757 PRINTMFIO(POSINTSTAT);
758 PRINTMFIO(NEGINTSTAT);
759 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_CTRL_REG), 0, 15,
760 "CTRL", DBG_BIT_PRINT_COUNT);
761 __dbg_bit_print(it8368_reg_read(csregt, csregh, IT8368_GPIODATAIN_REG),
762 8, 11, "]CRDDET/SENSE[", DBG_BIT_PRINT_COUNT);
763 }
764 #endif /* IT8368DEBUG */
765