1 /* $NetBSD: iq80310_timer.c,v 1.24 2024/07/20 20:36:33 andvar Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 * Timer/clock support for the Intel IQ80310.
40 *
41 * The IQ80310 has a 22-bit reloadable timer implemented in the CPLD.
42 * We use it to provide a hardclock interrupt. There is no RTC on
43 * the IQ80310.
44 *
45 * The timer uses the SPCI clock. The timer uses the 33MHz clock by
46 * reading the SPCI_66EN signal and dividing the clock if necessary.
47 */
48
49 #include <sys/cdefs.h>
50 __KERNEL_RCSID(0, "$NetBSD: iq80310_timer.c,v 1.24 2024/07/20 20:36:33 andvar Exp $");
51
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/kernel.h>
55 #include <sys/atomic.h>
56 #include <sys/time.h>
57 #include <sys/timetc.h>
58
59 #include <dev/clock_subr.h>
60
61 #include <sys/bus.h>
62 #include <arm/cpufunc.h>
63
64 #include <evbarm/iq80310/iq80310reg.h>
65 #include <evbarm/iq80310/iq80310var.h>
66 #include <evbarm/iq80310/obiovar.h>
67
68 /*
69 * Some IQ80310-based designs have fewer bits in the timer counter.
70 * Deal with them here.
71 */
72 #if defined(IOP310_TEAMASA_NPWR)
73 #define COUNTER_MASK 0x0007ffff
74 #else /* Default to stock IQ80310 */
75 #define COUNTER_MASK 0x003fffff
76 #endif /* list of IQ80310-based designs */
77
78 #define COUNTS_PER_SEC 33000000 /* 33MHz */
79 #define COUNTS_PER_USEC (COUNTS_PER_SEC / 1000000)
80
81 static void *clock_ih;
82
83 static uint32_t counts_per_hz;
84
85 static u_int iq80310_get_timecount(struct timecounter *);
86
87 static struct timecounter iq80310_timecounter = {
88 .tc_get_timecount = iq80310_get_timecount,
89 .tc_counter_mask = 0xffffffff,
90 .tc_frequency = COUNTS_PER_SEC,
91 .tc_name = "iq80310",
92 .tc_quality = 100,
93 };
94
95 static volatile uint32_t iq80310_base;
96
97 int clockhandler(void *);
98
99 static inline void
timer_enable(uint8_t bit)100 timer_enable(uint8_t bit)
101 {
102
103 CPLD_WRITE(IQ80310_TIMER_ENABLE,
104 CPLD_READ(IQ80310_TIMER_ENABLE) | bit);
105 }
106
107 static inline void
timer_disable(uint8_t bit)108 timer_disable(uint8_t bit)
109 {
110
111 CPLD_WRITE(IQ80310_TIMER_ENABLE,
112 CPLD_READ(IQ80310_TIMER_ENABLE) & ~bit);
113 }
114
115 static inline uint32_t
timer_read(void)116 timer_read(void)
117 {
118 uint32_t rv;
119 uint8_t la0, la1, la2, la3;
120
121 /*
122 * First read latches count.
123 *
124 * From RedBoot: hardware bug that causes invalid counts to be
125 * latched. The loop appears to work around the problem.
126 */
127 do {
128 la0 = CPLD_READ(IQ80310_TIMER_LA0);
129 } while (la0 == 0);
130 la1 = CPLD_READ(IQ80310_TIMER_LA1);
131 la2 = CPLD_READ(IQ80310_TIMER_LA2);
132 la3 = CPLD_READ(IQ80310_TIMER_LA3);
133
134 rv = ((la0 & 0x40) >> 1) | (la0 & 0x1f);
135 rv |= (((la1 & 0x40) >> 1) | (la1 & 0x1f)) << 6;
136 rv |= (((la2 & 0x40) >> 1) | (la2 & 0x1f)) << 12;
137 rv |= (la3 & 0x0f) << 18;
138
139 return (rv);
140 }
141
142 static inline void
timer_write(uint32_t x)143 timer_write(uint32_t x)
144 {
145
146 KASSERT((x & COUNTER_MASK) == x);
147
148 CPLD_WRITE(IQ80310_TIMER_LA0, x & 0xff);
149 CPLD_WRITE(IQ80310_TIMER_LA1, (x >> 8) & 0xff);
150 CPLD_WRITE(IQ80310_TIMER_LA2, (x >> 16) & 0x3f);
151 }
152
153 /*
154 * iq80310_calibrate_delay:
155 *
156 * Calibrate the delay loop.
157 */
158 void
iq80310_calibrate_delay(void)159 iq80310_calibrate_delay(void)
160 {
161
162 /*
163 * We'll use the CPLD timer for delay(), as well. We go
164 * ahead and start it up now, just don't enable interrupts
165 * until cpu_initclocks().
166 *
167 * Just use hz=100 for now -- we'll adjust it, if necessary,
168 * in cpu_initclocks().
169 */
170 counts_per_hz = COUNTS_PER_SEC / 100;
171
172 timer_disable(TIMER_ENABLE_INTEN);
173 timer_disable(TIMER_ENABLE_EN);
174
175 timer_write(counts_per_hz);
176
177 timer_enable(TIMER_ENABLE_EN);
178 }
179
180 /*
181 * cpu_initclocks:
182 *
183 * Initialize the clock and get them going.
184 */
185 void
cpu_initclocks(void)186 cpu_initclocks(void)
187 {
188 u_int oldirqstate;
189
190 if (hz < 50 || COUNTS_PER_SEC % hz) {
191 printf("Cannot get %d Hz clock; using 100 Hz\n", hz);
192 hz = 100;
193 }
194
195 /*
196 * We only have one timer available; stathz and profhz are
197 * always left as 0 (the upper-layer clock code deals with
198 * this situation).
199 */
200 if (stathz != 0)
201 printf("Cannot get %d Hz statclock\n", stathz);
202 stathz = 0;
203
204 if (profhz != 0)
205 printf("Cannot get %d Hz profclock\n", profhz);
206 profhz = 0;
207
208 /* Report the clock frequency. */
209 printf("clock: hz=%d stathz=%d profhz=%d\n", hz, stathz, profhz);
210
211 /* Hook up the clock interrupt handler. */
212 clock_ih = iq80310_intr_establish(XINT3_IRQ(XINT3_TIMER), IPL_CLOCK,
213 clockhandler, NULL);
214 if (clock_ih == NULL)
215 panic("cpu_initclocks: unable to register timer interrupt");
216
217 /* Set up the new clock parameters. */
218 oldirqstate = disable_interrupts(I32_bit);
219
220 timer_disable(TIMER_ENABLE_EN);
221
222 counts_per_hz = COUNTS_PER_SEC / hz;
223 timer_write(counts_per_hz);
224
225 timer_enable(TIMER_ENABLE_INTEN);
226 timer_enable(TIMER_ENABLE_EN);
227
228 restore_interrupts(oldirqstate);
229
230 tc_init(&iq80310_timecounter);
231 }
232
233 /*
234 * setstatclockrate:
235 *
236 * Set the rate of the statistics clock.
237 *
238 * We assume that hz is either stathz or profhz, and that neither
239 * will change after being set by cpu_initclocks(). We could
240 * recalculate the intervals here, but that would be a pain.
241 */
242 void
setstatclockrate(int newhz)243 setstatclockrate(int newhz)
244 {
245
246 /*
247 * Nothing to do, here; we can't change the statclock
248 * rate on the IQ80310.
249 */
250 }
251
252 static u_int
iq80310_get_timecount(struct timecounter * tc)253 iq80310_get_timecount(struct timecounter *tc)
254 {
255 u_int oldirqstate, base, counter;
256
257 oldirqstate = disable_interrupts(I32_bit);
258 base = iq80310_base;
259 counter = timer_read();
260 restore_interrupts(oldirqstate);
261
262 return base + counter;
263 }
264
265 /*
266 * delay:
267 *
268 * Delay for at least N microseconds.
269 */
270 void
delay(u_int n)271 delay(u_int n)
272 {
273 uint32_t cur, last, delta, usecs;
274
275 /*
276 * This works by polling the timer and counting the
277 * number of microseconds that go by.
278 */
279 last = timer_read();
280 delta = usecs = 0;
281
282 while (n > usecs) {
283 cur = timer_read();
284
285 /* Check to see if the timer has wrapped around. */
286 if (cur < last)
287 delta += ((counts_per_hz - last) + cur);
288 else
289 delta += (cur - last);
290
291 last = cur;
292
293 if (delta >= COUNTS_PER_USEC) {
294 usecs += delta / COUNTS_PER_USEC;
295 delta %= COUNTS_PER_USEC;
296 }
297 }
298 }
299
300 /*
301 * clockhandler:
302 *
303 * Handle the hardclock interrupt.
304 */
305 int
clockhandler(void * arg)306 clockhandler(void *arg)
307 {
308 struct clockframe *frame = arg;
309
310 timer_disable(TIMER_ENABLE_INTEN);
311 timer_enable(TIMER_ENABLE_INTEN);
312
313 atomic_add_32(&iq80310_base, counts_per_hz);
314
315 hardclock(frame);
316
317 /*
318 * Don't run the snake on IOP310-based systems that
319 * don't have the 7-segment display.
320 */
321 #if !defined(IOP310_TEAMASA_NPWR)
322 {
323 static int snakefreq;
324
325 if ((snakefreq++ & 15) == 0)
326 iq80310_7seg_snake();
327 }
328 #endif
329
330 return (1);
331 }
332