1/*        $NetBSD: intmmu.S,v 1.12 2013/08/12 17:41:51 matt Exp $ */
2
3/*
4 * Copyright (c) 2001 ARM Ltd
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. The name of the company may not be used to endorse or promote
16 *    products derived from this software without specific prior written
17 *    permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
20 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
21 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <machine/asm.h>
33#include <arm/armreg.h>
34#include "assym.h"
35
36          .section .start,"ax",%progbits
37
38ASENTRY_NP(integrator_start)
39          mov       r6, #0x16000000               /* UART0 Physical base*/
40#ifdef VERBOSE_INIT_ARM
41          mov       r3, #'A'
42          str       r3, [r6]            /* Let the world know we are alive */
43#endif
44/*
45 * Check that the processor has a CP15.  Some core modules do not.
46 * We can tell by reading CM_PROC.  If it is zero, then we're OK, otherwise
47 * let the user know why we've died.
48 */
49          mov       r7, #0x10000000
50          ldr       r3, [r7, #4]
51          cmp       r3, #0
52          bne       Lno_cp15
53/*
54 * Now read CP15 and check what sort of core we have.  We need to know
55 * if it has an MMU.  There's no simple test for this, but the following
56 * hack should be sufficient for all currently supported CM boards:
57 *  - Check that the product code has a '2' or '3' in bits 8-11
58 */
59          mrc       p15, 0, r3, c0, c0, 0
60          and       r0, r3, #0x00000f00
61          teq       r0, #0x00000200               /* ARM 920, 1020, 1026, etc */
62          teqne     r0, #0x00000300               /* ARM 1136 */
63          bne       Lno_mmu
64
65/*
66 * At this time the MMU is off.
67 * We build up an initial memory map at 0x8000 that we can use to get
68 * the kernel running from the top of memory.  All mappings in this table
69 * use L1 section maps.
70 */
71
72/*
73 * Set Virtual == Physical
74 */
75          mov       r3, #(L1_S_AP_KRW)
76          add       r3, r3, #(L1_TYPE_S)
77          mov       r2, #0x100000                 /* advance by 1MB */
78          mov       r1, #0x8000                   /* page table start */
79          mov       r0, #0x1000                   /* page table size */
80
81Lflat:
82          str       r3, [r1], #0x0004
83          add       r3, r3, r2
84          subs      r0, r0, #1
85          bgt       Lflat
86
87/*
88 * Map VA 0xc0000000->0xc03fffff to PA 0x00000000->0x003fffff
89 */
90          mov       r3, #(L1_S_AP_KRW)
91          add       r3, r3, #(L1_TYPE_S)
92          mov       r1, #0x8000                   /* page table start */
93          add       r1, r1, #(0xc00 * 4)          /* offset to 0xc00xxxxx */
94#         add       r1, r1, #(0x001 * 4)          /* offset to 0xc01xxxxx */
95          mov       r0, #63
96Lkern:
97          str       r3, [r1], #0x0004   /* 0xc000000-0xc03fffff */
98          add       r3, r3, r2
99          subs      r0, r0, #1
100          bgt       Lkern
101/*
102 * Mapping the peripheral register region (0x10000000->0x1fffffff) linearly
103 * would require 256MB of virtual memory (as much space as the entire kernel
104 * virtual space).  So we map the first 1M of each 16MB sub-space into the
105 * region VA 0xfd000000->0xfdffffff; this should map enough of the peripheral
106 * space to at least get us up and running.
107 */
108          mov       r3, #(L1_S_AP_KRW)
109          add       r3, r3, #L1_TYPE_S
110          add       r3, r3, #0x10000000 /* Peripherals base */
111          mov       r1, #0x8000                   /* page table start */
112          add       r1, r1, #(0xfd0 * 4)
113          mov       r2, #0x01000000               /* 16MB increment.  */
114          mov       r0, #16
115Lperiph:
116          str       r3, [r1], #4                  /* 0xfd000000-0xfdffffff */
117          add       r3, r3, r2
118          subs      r0, r0, #1
119          bgt       Lperiph
120
121/*
122 * We now have our page table ready, so load it up and light the blue
123 * touch paper.
124 */
125
126          /* set the location of the L1 page table */
127          mov       r1, #0x8000
128          mcr       p15, 0, r1, c2, c0, 0
129
130          /* Flush the old TLBs (just in case) */
131          mcr       p15, 0, r1, c8, c7, 0
132          /* And the caches */
133          mov       r0, #0
134          mcr       p15, 0, r1, c7, c6, 0
135
136#ifdef VERBOSE_INIT_ARM
137          mov       r2, #'B'
138          strb      r2, [r6]
139#endif
140
141          /* Set the Domain Access register.  Very important! */
142          mov       r1, #1
143          mcr       p15, 0, r1, c3, c0, 0
144
145          /*
146           * set mmu bit (don't set anything else for now, we don't know
147           * what sort of CPU we have yet.
148           */
149          mov       r1, #CPU_CONTROL_MMU_ENABLE
150
151/*
152 * This is where it might all start to go wrong if the CPU fitted to your
153 * integrator does not have an MMU.
154 */
155          /* fetch current control state */
156          mrc       p15, 0, r2, c1, c0, 0
157          orr       r2, r2, r1
158
159          /* set new control state */
160          mcr       p15, 0, r2, c1, c0, 0
161
162          mov       r0, r0
163          mov       r0, r0
164          mov       r0, r0
165
166#ifdef VERBOSE_INIT_ARM
167          /* emit a char.  Uart is now at 0xfd600000 */
168          mov       r6, #0xfd000000
169          add       r6, r6, #0x00600000
170          mov       r2, #'C'
171          strb      r2, [r6]
172#endif
173
174          /* jump to kernel space */
175          mov       r0, #0x0200
176
177          /* Switch to kernel VM and really set the ball rolling.  */
178          ldr       pc, Lstart
179
180Lstart:   .long     start
181
182Lmsg:
183          ldrb      r2, [r0], #1
184          cmp       r2, #0
185          strbne    r2, [r6]
186Lwait:
187          ldrb      r3, [r6, #0x18]
188          tst       r3, #0x80
189          beq       Lwait
190          cmp       r2, #0
191          bne       Lmsg
192          /* We're toast! */
193          b         .
194
195Lno_cp15:
196          adr       r0, Lcp15msg
197          b         Lmsg
198Lno_mmu:
199          adr       r0, Lmmumsg
200          b         Lmsg
201
202Lcp15msg:
203          .ascii "Core has no cp15\r\n\0"
204Lmmumsg:
205          .ascii "Core has no MMU\r\n\0"
206