1 /* $NetBSD: serreg.h,v 1.2 2008/04/28 20:23:15 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Leo Weppelman. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #define SER_FREQ 153600 /* XXX: Assumes UCR_CLKDIV set! */ 33 #define SER_TOLERANCE 30 /* Baud rate tolerance, in 0.1% units */ 34 35 /* Usart Control Register */ 36 #define UCR_PEVEN 0x02 /* Even parity */ 37 #define UCR_PENAB 0x04 /* Parity enable */ 38 #define UCR_SYNCH 0x00 /* Synchroneous mode */ 39 #define UCR_STOPB1 0x08 /* 1 stopbit */ 40 #define UCR_STOPB15 0x10 /* 1.5 stopbit */ 41 #define UCR_STOPB2 0x18 /* 2 stopbits */ 42 #define UCR_8BITS 0x00 /* 8 databits */ 43 #define UCR_7BITS 0x20 /* 7 databits */ 44 #define UCR_6BITS 0x40 /* 6 databits */ 45 #define UCR_5BITS 0x60 /* 5 databits */ 46 #define UCR_CLKDIV 0x80 /* Divide clock by 16 */ 47 48 /* Receiver Status Register */ 49 #define RSR_ENAB 0x01 /* Receiver enabled */ 50 #define RSR_SS 0x02 /* Synchroneous strip */ 51 #define RSR_CIP 0x04 /* Character in progress (async) */ 52 #define RSR_BREAK 0x08 /* Break (async) */ 53 #define RSR_MATCH 0x04 /* Character match (sync) */ 54 #define RSR_FS 0x08 /* Found/Search (sync) */ 55 #define RSR_FERR 0x10 /* Framing error */ 56 #define RSR_PERR 0x20 /* Parity error */ 57 #define RSR_OERR 0x40 /* Overrun error */ 58 #define RSR_BFULL 0x80 /* Buffer Full */ 59 60 /* Transmitter Status Register */ 61 #define TSR_ENAB 0x01 /* Transmitter Enable */ 62 #define TSR_SBREAK 0x08 /* Transmit Break */ 63 #define TSR_END 0x10 /* End of character */ 64 #define TSR_UE 0x40 /* Uart empty */ 65 #define TSR_BE 0x80 /* Buffer empty */ 66 67 /* 68 * These bits are a mixture of MFP.mf_gpip and PSG.ioa values. 69 * Luckily, they were all distinct. 70 */ 71 #define MCR_RTS 0x08 72 #define MCR_CTS 0x04 73 #define MCR_DCD 0x02 74 #define MCR_DTR 0x10 75 #define MCR_RI 0x40 76