1 /* $NetBSD: imx51_ccmreg.h,v 1.6 2021/07/24 21:31:32 andvar Exp $ */ 2 /* 3 * Copyright (c) 2011, 2012 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _IMX51_CCMREG_H 28 #define _IMX51_CCMREG_H 29 30 #include <sys/cdefs.h> 31 32 /* register offset address */ 33 34 #define CCMC_IMX6_BASE 0x020c4040 35 36 #define CCMC_CCR 0x0000 37 #define CCR_FPM_MULT __BIT(12) 38 #define CCR_COSC_EN __BIT(12) 39 #define CCMC_CCDR 0x0004 40 #define CCMC_CSR 0x0008 41 #define CCMC_CCSR 0x000c 42 #define CCSR_LP_APM __BIT(9) 43 #define CCSR_STEP_SEL __BITS(8, 7) 44 #define CCSR_PLL2_DIV_PODF __BITS(6, 5) 45 #define CCSR_PLL3_DIV_PODF __BITS(4, 3) 46 #define CCSR_PLL1_SW_CLK_SEL __BIT(2) 47 #define CCSR_PLL2_SW_CLK_SEL __BIT(1) 48 #define CCSR_PLL3_SW_CLK_SEL __BIT(0) 49 #define CCMC_CACRR 0x0010 50 #define CCMC_CBCDR 0x0014 51 #define CBCDR_DDR_HIGH_FREQ_CLK_SEL __BIT(30) 52 #define CBCDR_DDR_CLK_PODF __BITS(29, 27) 53 #ifdef IMX50 54 #define CBCDR_PERIPH_CLK_SEL __BITS(26, 25) 55 #else 56 #define CBCDR_EMI_CLK_SEL __BIT(26) 57 #define CBCDR_PERIPH_CLK_SEL __BIT(25) 58 #endif 59 #define CBCDR_EMI_SLOW_PODF __BITS(24, 22) 60 #define CBCDR_AXI_B_PODF __BITS(21, 19) 61 #define CBCDR_AXI_A_PODF __BITS(18, 16) 62 #define CBCDR_NFC_PODF __BITS(15, 13) 63 #define CBCDR_AHB_PODF __BITS(12, 10) 64 #define CBCDR_IPG_PODF __BITS(9, 8) 65 #define CBCDR_PERCLK_PRED1 __BITS(7, 6) 66 #define CBCDR_PERCLK_PRED2 __BITS(5, 3) 67 #define CBCDR_PERCLK_PODF __BITS(2, 0) 68 #define CCMC_CBCMR 0x0018 69 #define CBCMR_PERIPH_APM_SEL __BITS(13, 12) 70 #define CBCMR_IPU_HSP_CLK_SEL __BITS(7, 6) 71 #define CBCMR_PERCLK_LP_APM_SEL __BIT(1) 72 #define CBCMR_PERCLK_IPG_SEL __BIT(0) 73 #define CCMC_CSCMR1 0x001c 74 #define CSCMR1_UART_CLK_SEL __BITS(25, 24) 75 #ifdef IMX50 76 #define CSCMR1_ESDHC1_CLK_SEL __BITS(22, 21) 77 #define CSCMR1_ESDHC2_CLK_SEL __BIT(20) 78 #define CSCMR1_ESDHC4_CLK_SEL __BIT(19) 79 #define CSCMR1_ESDHC3_CLK_SEL __BITS(18, 16) 80 #else 81 #define CSCMR1_ESDHC1_CLK_SEL __BITS(21, 20) 82 #define CSCMR1_ESDHC3_CLK_SEL __BIT(19) 83 #define CSCMR1_ESDHC4_CLK_SEL __BIT(18) 84 #define CSCMR1_ESDHC2_CLK_SEL __BITS(17, 16) 85 #endif 86 #define CSCMR1_CSPI_CLK_SEL __BITS(5, 4) 87 #define CCMC_CSCMR2 0x0020 88 #define CCMC_CSCDR1 0x0024 89 #ifdef IMX50 90 #define CSCDR1_ESDHC3_CLK_PRED __BITS(24, 22) 91 #define CSCDR1_ESDHC3_CLK_PODF __BITS(21, 19) 92 #else 93 #define CSCDR1_ESDHC2_CLK_PRED __BITS(24, 22) 94 #define CSCDR1_ESDHC2_CLK_PODF __BITS(21, 19) 95 #endif 96 #define CSCDR1_ESDHC1_CLK_PRED __BITS(18, 16) 97 #define CSCDR1_ESDHC1_CLK_PODF __BITS(13, 11) 98 #define CSCDR1_UART_CLK_PRED __BITS(5, 3) 99 #define CSCDR1_UART_CLK_PODF __BITS(2, 0) 100 #define CCMC_CS1CDR 0x0028 101 #define CCMC_CS2CDR 0x002c 102 #define CCMC_CDCDR 0x0030 103 #define CDCDR_PERIPH_CLK2 __BITS(29, 27) 104 #define CCMC_CHSCCDR 0x0034 // i.MX6 105 #define CCMC_CSCDR2 0x0038 106 #define CSCDR2_ECSPI_CLK_PRED __BITS(27, 25) 107 #define CSCDR2_ECSPI_CLK_PODF __BITS(24, 19) 108 #define CCMC_CSCDR3 0x003c 109 #define CCMC_CSCDR4 0x0040 110 #define CCMC_CWDR 0x0044 111 #define CCMC_CDHIPR 0x0048 112 #define CCMC_CDCR 0x004c 113 #define CDCR_SW_PERIPH_CLK_DIV_REQ __BIT(6) 114 #define CDCR_PERIPH_CLK_DVFS_PODF __BITS(1, 0) 115 #define CCMC_CTOR 0x0050 116 #define CCMC_CLPCR 0x0054 117 #define CCMC_CISR 0x0058 118 #define CCMC_CIMR 0x005c 119 #define CCMC_CCOSR 0x0060 120 #define CCMC_CGPR 0x0064 121 #define CCMC_CCGR(n) (0x0068 + (n) * 4) 122 #define CCMC_CMEOR 0x0084 123 #ifdef IMX50 124 #define CCMC_CSR2 0x008C 125 #define CSR2_EPDC_ASM_ACTIVE __BIT(13) 126 #define CSR2_EPXP_ASM_ACTIVE __BIT(12) 127 #define CSR2_ELCDIF_ASM_ACTIVE __BIT(11) 128 #define CSR2_SYS_CLK_XTAL_ACTIVE __BIT(10) 129 #define CSR2_ELCDIF_PIX_BUSY __BIT(9) 130 #define CSR2_EPDC_PIX_BUSY __BIT(8) 131 #define CSR2_MSHC_XMSCKI_BUSY __BIT(7) 132 #define CSR2_BCH_BUSY __BIT(6) 133 #define CSR2_GPMI_BUSY __BIT(5) 134 #define CSR2_EPDC_AXI_BUSY __BIT(4) 135 #define CSR2_DISPLAY_AXI_BUSY __BIT(3) 136 #define CSR2_DDR_CLK_REF_PLL_BUSY __BIT(2) 137 #define CSR2_SYS_CLK_REF_PLL_BUSY __BIT(1) 138 #define CSR2_SYS_CLK_REF_XTAL_BUSY __BIT(0) 139 #define CCMC_CLKSEQ_BYPASS 0x0090 140 #define CLKSEQ_ELCDIF_PIX_CLK __BITS(15, 14) 141 #define CLKSEQ_EPDC_PIX_CLK __BITS(13, 12) 142 #define CLKSEQ_MSHC_XMSCKI_CLK __BITS(11, 10) 143 #define CLKSEQ_BCH_CLK __BITS(9, 8) 144 #define CLKSEQ_GPMI_CLK __BITS(7, 6) 145 #define CLKSEQ_EPDC_AXI_CLK __BITS(5, 4) 146 #define CLKSEQ_DISPLAY_AXI_CLK __BITS(3, 2) 147 #define CLKSEQ_SYS_CLK __BITS(1, 0) 148 #define CLKSEQ_XTAL 0 149 #define CLKSEQ_PFDx 1 150 #define CLKSEQ_PLL1 2 151 #define CLKSEQ_CAMP1 3 152 #define CCMC_EPDC_PIX 0x00A0 153 #define EPDC_PIX_CLKGATE __BITS(31, 30) 154 #define EPDC_PIX_CLKGATE_OFF __SHIFTIN(0, EPDC_AXI_CLKGATE) 155 #define EPDC_PIX_CLKGATE_RUNMODE __SHIFTIN(1, EPDC_AXI_CLKGATE) 156 #define EPDC_PIX_CLKGATE_ALWAYS __SHIFTIN(2, EPDC_AXI_CLKGATE) 157 #define EPDC_PIX_CLKGATE_EXCEPTSTOP __SHIFTIN(3, EPDC_AXI_CLKGATE) 158 #define EPDC_PIX_CLK_PRED __BITS(13, 12) 159 #define EPDC_PIX_CLK_PODF __BITS(11, 0) 160 #define CCMC_EPDC_AXI 0x00A8 161 #define EPDC_AXI_CLKGATE __BITS(31, 30) 162 #define EPDC_AXI_CLKGATE_OFF __SHIFTIN(0, EPDC_AXI_CLKGATE) 163 #define EPDC_AXI_CLKGATE_RUNMODE __SHIFTIN(1, EPDC_AXI_CLKGATE) 164 #define EPDC_AXI_CLKGATE_ALWAYS __SHIFTIN(2, EPDC_AXI_CLKGATE) 165 #define EPDC_AXI_CLKGATE_EXCEPTSTOP __SHIFTIN(3, EPDC_AXI_CLKGATE) 166 #define EPDC_ASM_EN __BIT(9) 167 #define EPDC_ASM_SLOW_DIV __BITS(8, 6) 168 #define EPDC_AXI_DIV __BITS(5, 0) 169 #endif 170 171 #define CCMC_SIZE 0x0100 172 173 /* CCGR Clock Gate Register */ 174 175 #define CCMR_CCGR_NSOURCE 16 176 #define CCMR_CCGR_NGROUPS 7 177 #define CCMR_CCGR_MODULE(clk) ((clk) / CCMR_CCGR_NSOURCE) 178 #define __CCGR_NUM(a, b) ((a) * 16 + (b)) 179 #define CCGR_MODE_CLKOFF 0x0 180 #define CCGR_MODE_CLKON 0x2 181 182 #ifdef IMX50 183 #define CCGR_USBOH1_CLK __CCGR_NUM(2, 13) 184 #define CCGR_USBPHY1_CLK __CCGR_NUM(4, 5) 185 #define CCGR_EPDC_PIX_CLK __CCGR_NUM(6, 5) 186 #define CCGR_EPDC_AXI_CLK __CCGR_NUM(6, 8) 187 #else 188 #define CCGR_ARM_BUS_CLK __CCGR_NUM(0, 0) 189 #define CCGR_ARM_AXI_CLK __CCGR_NUM(0, 1) 190 #define CCGR_ARM_DEBUG_CLK __CCGR_NUM(0, 2) 191 #define CCGR_TZIC_CLK __CCGR_NUM(0, 3) 192 #define CCGR_DAP_CLK __CCGR_NUM(0, 4) 193 #define CCGR_TPIU_CLK __CCGR_NUM(0, 5) 194 #define CCGR_CTI2_CLK __CCGR_NUM(0, 6) 195 #define CCGR_CTI3_CLK __CCGR_NUM(0, 7) 196 #define CCGR_AHBMUX1_CLK __CCGR_NUM(0, 8) 197 #define CCGR_AHBMUX2_CLK __CCGR_NUM(0, 9) 198 #define CCGR_ROMCP_CLK __CCGR_NUM(0, 10) 199 #define CCGR_ROM_CLK __CCGR_NUM(0, 11) 200 #define CCGR_AIPS_TZ1_CLK __CCGR_NUM(0, 12) 201 #define CCGR_AIPS_TZ2_CLK __CCGR_NUM(0, 13) 202 #define CCGR_AHB_MAX_CLK __CCGR_NUM(0, 14) 203 #define CCGR_IIM_CLK __CCGR_NUM(0, 15) 204 #define CCGR_TMAX1_CLK __CCGR_NUM(1, 0) 205 #define CCGR_TMAX2_CLK __CCGR_NUM(1, 1) 206 #define CCGR_TMAX3_CLK __CCGR_NUM(1, 2) 207 #define CCGR_UART1_CLK __CCGR_NUM(1, 3) 208 #define CCGR_UART1_SERIAL_CLK __CCGR_NUM(1, 4) 209 #define CCGR_UART2_CLK __CCGR_NUM(1, 5) 210 #define CCGR_UART2_SERIAL_CLK __CCGR_NUM(1, 6) 211 #define CCGR_UART3_CLK __CCGR_NUM(1, 7) 212 #define CCGR_UART3_SERIAL_CLK __CCGR_NUM(1, 8) 213 #define CCGR_I2C1_SERIAL_CLK __CCGR_NUM(1, 9) 214 #define CCGR_I2C2_SERIAL_CLK __CCGR_NUM(1, 10) 215 #define CCGR_HSI2C_CLK __CCGR_NUM(1, 11) 216 #define CCGR_HSI2C_SERIAL_CLK __CCGR_NUM(1, 12) 217 #define CCGR_FIRI_CLK __CCGR_NUM(1, 13) 218 #define CCGR_FIRI_SERIAL_CLK __CCGR_NUM(1, 14) 219 #define CCGR_SCC_CLK __CCGR_NUM(1, 15) 220 #define CCGR_USB_PHY_CLK __CCGR_NUM(2, 0) 221 #define CCGR_EPIT1_CLK __CCGR_NUM(2, 1) 222 #define CCGR_EPIT1_SERIAL_CLK __CCGR_NUM(2, 2) 223 #define CCGR_EPIT2_CLK __CCGR_NUM(2, 3) 224 #define CCGR_ESDHC1_CLK __CCGR_NUM(3, 0) 225 #define CCGR_ESDHC1_SERIAL_CLK __CCGR_NUM(3, 1) 226 #define CCGR_ESDHC2_CLK __CCGR_NUM(3, 2) 227 #define CCGR_ESDHC2_SERIAL_CLK __CCGR_NUM(3, 3) 228 #define CCGR_ESDHC3_CLK __CCGR_NUM(3, 4) 229 #define CCGR_ESDHC3_SERIAL_CLK __CCGR_NUM(3, 5) 230 #define CCGR_ESDHC4_CLK __CCGR_NUM(3, 6) 231 #define CCGR_ESDHC4_SERIAL_CLK __CCGR_NUM(3, 7) 232 #define CCGR_SSI1_CLK __CCGR_NUM(3, 8) 233 #define CCGR_SSI1_SERIAL_CLK __CCGR_NUM(3, 9) 234 #define CCGR_SSI2_CLK __CCGR_NUM(3, 10) 235 #define CCGR_SSI2_SERIAL_CLK __CCGR_NUM(3, 11) 236 #define CCGR_SSI3_CLK __CCGR_NUM(3, 12) 237 #define CCGR_SSI3_SERIAL_CLK __CCGR_NUM(3, 13) 238 #define CCGR_SSI_EXT1_CLK __CCGR_NUM(3, 14) 239 #define CCGR_SSI_EXT2_CLK __CCGR_NUM(3, 15) 240 #define CCGR_PATA_CLK __CCGR_NUM(4, 0) 241 #define CCGR_SIM_CLK __CCGR_NUM(4, 1) 242 #define CCGR_SIM_SERIAL_CLK __CCGR_NUM(4, 2) 243 #define CCGR_SAHARA_CLK __CCGR_NUM(4, 3) 244 #define CCGR_RTIC_CLK __CCGR_NUM(4, 4) 245 #define CCGR_ECSPI1_CLK __CCGR_NUM(4, 5) 246 #define CCGR_ECSPI1_SERIAL_CLK __CCGR_NUM(4, 6) 247 #define CCGR_ECSPI2_CLK __CCGR_NUM(4, 7) 248 #define CCGR_ECSPI2_SERIAL_CLK __CCGR_NUM(4, 8) 249 #define CCGR_CSPI_CLK __CCGR_NUM(4, 9) 250 #define CCGR_SRTC_CLK __CCGR_NUM(4, 10) 251 #define CCGR_SDMA_CLK __CCGR_NUM(4, 11) 252 #define CCGR_SPBA_CLK __CCGR_NUM(5, 0) 253 #define CCGR_GPU_CLK __CCGR_NUM(5, 1) 254 #define CCGR_GARB_CLK __CCGR_NUM(5, 2) 255 #define CCGR_VPU_CLK __CCGR_NUM(5, 3) 256 #define CCGR_VPU_SERIAL_CLK __CCGR_NUM(5, 4) 257 #define CCGR_IPU_CLK __CCGR_NUM(5, 5) 258 #define CCGR_EMI_GARB_CLK __CCGR_NUM(6, 0) 259 #define CCGR_IPU_DI0_CLK __CCGR_NUM(6, 1) 260 #define CCGR_IPU_DI1_CLK __CCGR_NUM(6, 2) 261 #define CCGR_GPU2D_CLK __CCGR_NUM(6, 3) 262 #define CCGR_SLIMBUS_CLK __CCGR_NUM(6, 4) 263 #define CCGR_SLIMBUS_SERIAL_CLK __CCGR_NUM(6, 5) 264 #endif 265 266 #endif /* _IMX51_CCMREG_H */ 267 268