1 /* $NetBSD: gicv3.h,v 1.11 2021/01/16 21:05:15 jmcneill Exp $ */
2 
3 /*-
4  * Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 
29 #ifndef _ARM_CORTEX_GICV3_H
30 #define _ARM_CORTEX_GICV3_H
31 
32 #include <sys/intr.h>
33 #include <sys/vmem.h>
34 
35 struct gicv3_dma {
36           bus_dma_segment_t   segs[1];
37           bus_dmamap_t                  map;
38           uint8_t                       *base;
39           bus_size_t                    len;
40 };
41 
42 struct gicv3_lpi_callback {
43           void                          (*cpu_init)(void *, struct cpu_info *);
44           void                          (*get_affinity)(void *, size_t, kcpuset_t *);
45           int                           (*set_affinity)(void *, size_t, const kcpuset_t *);
46 
47           void                          *priv;
48 
49           LIST_ENTRY(gicv3_lpi_callback) list;
50 };
51 
52 struct gicv3_softc {
53           struct pic_softc    sc_pic;             /* SGI/PPI/SGIs */
54           struct pic_softc    sc_lpi;             /* LPIs */
55           device_t            sc_dev;
56 
57           bus_space_tag_t               sc_bst;
58           bus_dma_tag_t                 sc_dmat;
59 
60           bus_space_handle_t  sc_bsh_d; /* GICD */
61           bus_space_handle_t  *sc_bsh_r;          /* GICR */
62           u_int                         sc_bsh_r_count;
63 
64           u_int                         sc_quirks;
65 #define   GICV3_QUIRK_RK3399  __BIT(0)  /* Rockchip RK3399 GIC-500 */
66 
67           uint32_t            sc_gicd_typer;
68 
69           u_int                         sc_priority_shift;
70           u_int                         sc_pmr_shift;
71 
72           uint32_t            sc_enabled_sgippi;
73           uint64_t            *sc_irouter;
74 
75           /* LPI configuration table */
76           struct gicv3_dma    sc_lpiconf;
77           bool                          sc_lpiconf_flush;
78 
79           /* LPI pending tables */
80           struct gicv3_dma    *sc_lpipend;
81 
82           /* LPI IDs */
83           vmem_t                        *sc_lpi_pool;
84 
85           /* Unique identifier for PEs */
86           u_int                         *sc_processor_id;
87 
88           /* Callbacks */
89           LIST_HEAD(, gicv3_lpi_callback) sc_lpi_callbacks;
90 };
91 
92 int       gicv3_init(struct gicv3_softc *);
93 void      gicv3_dma_alloc(struct gicv3_softc *, struct gicv3_dma *, bus_size_t, bus_size_t);
94 void      gicv3_irq_handler(void *);
95 
96 #endif /* _ARM_CORTEX_GICV3_H */
97