1 /* $NetBSD: bcm2835_aux.c,v 1.3 2021/01/27 03:10:19 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 2017 Jared D. McNeill <jmcneill@invisible.ca>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: bcm2835_aux.c,v 1.3 2021/01/27 03:10:19 thorpej Exp $");
31
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/device.h>
35 #include <sys/kmem.h>
36 #include <sys/bus.h>
37
38 #include <dev/clk/clk_backend.h>
39
40 #include <dev/fdt/fdtvar.h>
41
42 /* Registers */
43 #define BCMAUX_AUXIRQ_REG 0x00
44 #define BCMAUX_AUXENB_REG 0x04
45
46 /* Clock IDs */
47 #define BCMAUX_CLOCK_UART 0
48 #define BCMAUX_CLOCK_SPI1 1
49 #define BCMAUX_CLOCK_SPI2 2
50 #define BCMAUX_NCLOCK 3
51
52 static int bcmaux_match(device_t, cfdata_t, void *);
53 static void bcmaux_attach(device_t, device_t, void *);
54
55 static struct clk *bcmaux_decode(device_t, int, const void *, size_t);
56
57 static const struct fdtbus_clock_controller_func bcmaux_fdt_funcs = {
58 .decode = bcmaux_decode
59 };
60
61 static struct clk *bcmaux_get(void *, const char *);
62 static void bcmaux_put(void *, struct clk *);
63 static u_int bcmaux_get_rate(void *, struct clk *);
64 static int bcmaux_enable(void *, struct clk *);
65 static int bcmaux_disable(void *, struct clk *);
66
67 static const struct clk_funcs bcmaux_clk_funcs = {
68 .get = bcmaux_get,
69 .put = bcmaux_put,
70 .get_rate = bcmaux_get_rate,
71 .enable = bcmaux_enable,
72 .disable = bcmaux_disable,
73 };
74
75 struct bcmaux_clk {
76 struct clk base;
77 uint32_t mask;
78 };
79
80 struct bcmaux_softc {
81 device_t sc_dev;
82 int sc_phandle;
83 bus_space_tag_t sc_bst;
84 bus_space_handle_t sc_bsh;
85
86 struct clk *sc_pclk;
87
88 struct clk_domain sc_clkdom;
89 struct bcmaux_clk sc_clk[BCMAUX_NCLOCK];
90 };
91
92 #define BCMAUX_READ(sc, reg) \
93 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
94 #define BCMAUX_WRITE(sc, reg, val) \
95 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
96
97 CFATTACH_DECL_NEW(bcmaux_fdt, sizeof(struct bcmaux_softc),
98 bcmaux_match, bcmaux_attach, NULL, NULL);
99
100 static const struct device_compatible_entry compat_data[] = {
101 { .compat = "brcm,bcm2835-aux" },
102 DEVICE_COMPAT_EOL
103 };
104
105 static int
bcmaux_match(device_t parent,cfdata_t cf,void * aux)106 bcmaux_match(device_t parent, cfdata_t cf, void *aux)
107 {
108 const struct fdt_attach_args *faa = aux;
109
110 return of_compatible_match(faa->faa_phandle, compat_data);
111 }
112
113 static void
bcmaux_attach(device_t parent,device_t self,void * aux)114 bcmaux_attach(device_t parent, device_t self, void *aux)
115 {
116 struct bcmaux_softc * const sc = device_private(self);
117 const struct fdt_attach_args *faa = aux;
118 const int phandle = faa->faa_phandle;
119 bus_addr_t addr;
120 bus_size_t size;
121
122 if (fdtbus_get_reg(phandle, 0, &addr, &size) != 0) {
123 aprint_error(": couldn't get registers\n");
124 return;
125 }
126
127 sc->sc_dev = self;
128 sc->sc_phandle = phandle;
129 sc->sc_clkdom.funcs = &bcmaux_clk_funcs;
130 sc->sc_clkdom.priv = sc;
131 sc->sc_pclk = fdtbus_clock_get_index(phandle, 0);
132 if (sc->sc_pclk == NULL) {
133 aprint_error(": couldn't get parent clock\n");
134 return;
135 }
136 sc->sc_bst = faa->faa_bst;
137 if (bus_space_map(sc->sc_bst, addr, size, 0, &sc->sc_bsh) != 0) {
138 aprint_error(": couldn't map registers\n");
139 return;
140 }
141
142 sc->sc_clk[BCMAUX_CLOCK_UART].base.domain = &sc->sc_clkdom;
143 sc->sc_clk[BCMAUX_CLOCK_UART].base.name = "aux_uart";
144 sc->sc_clk[BCMAUX_CLOCK_UART].mask = __BIT(0);
145
146 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.domain = &sc->sc_clkdom;
147 sc->sc_clk[BCMAUX_CLOCK_SPI1].base.name = "aux_spi1";
148 sc->sc_clk[BCMAUX_CLOCK_SPI1].mask = __BIT(1);
149
150 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.domain = &sc->sc_clkdom;
151 sc->sc_clk[BCMAUX_CLOCK_SPI2].base.name = "aux_spi2";
152 sc->sc_clk[BCMAUX_CLOCK_SPI2].mask = __BIT(2);
153
154 aprint_naive("\n");
155 aprint_normal("\n");
156
157 fdtbus_register_clock_controller(self, phandle, &bcmaux_fdt_funcs);
158 }
159
160 static struct clk *
bcmaux_decode(device_t dev,int cc_phandle,const void * data,size_t len)161 bcmaux_decode(device_t dev, int cc_phandle, const void *data, size_t len)
162 {
163 struct bcmaux_softc * const sc = device_private(dev);
164 u_int clkid;
165
166 if (len != 4)
167 return NULL;
168
169 clkid = be32dec(data);
170 if (clkid >= BCMAUX_NCLOCK)
171 return NULL;
172
173 return &sc->sc_clk[clkid].base;
174 }
175
176 static struct clk *
bcmaux_get(void * priv,const char * name)177 bcmaux_get(void *priv, const char *name)
178 {
179 struct bcmaux_softc * const sc = priv;
180
181 for (size_t i = 0; i < BCMAUX_NCLOCK; i++) {
182 if (strcmp(name, sc->sc_clk[i].base.name) == 0)
183 return &sc->sc_clk[i].base;
184 }
185
186 return NULL;
187 }
188
189 static void
bcmaux_put(void * priv,struct clk * clk)190 bcmaux_put(void *priv, struct clk *clk)
191 {
192 }
193
194 static u_int
bcmaux_get_rate(void * priv,struct clk * clk)195 bcmaux_get_rate(void *priv, struct clk *clk)
196 {
197 struct bcmaux_softc * const sc = priv;
198
199 return clk_get_rate(sc->sc_pclk);
200 }
201
202 static int
bcmaux_enable(void * priv,struct clk * clk)203 bcmaux_enable(void *priv, struct clk *clk)
204 {
205 struct bcmaux_softc * const sc = priv;
206 struct bcmaux_clk *auxclk = (struct bcmaux_clk *)clk;
207 uint32_t val;
208
209 val = BCMAUX_READ(sc, BCMAUX_AUXENB_REG);
210 val |= auxclk->mask;
211 BCMAUX_WRITE(sc, BCMAUX_AUXENB_REG, val);
212
213 return 0;
214 }
215
216 static int
bcmaux_disable(void * priv,struct clk * clk)217 bcmaux_disable(void *priv, struct clk *clk)
218 {
219 struct bcmaux_softc * const sc = priv;
220 struct bcmaux_clk *auxclk = (struct bcmaux_clk *)clk;
221 uint32_t val;
222
223 val = BCMAUX_READ(sc, BCMAUX_AUXENB_REG);
224 val &= ~auxclk->mask;
225 BCMAUX_WRITE(sc, BCMAUX_AUXENB_REG, val);
226
227 return 0;
228 }
229