1 /* $OpenBSD: ehci.c,v 1.48 2005/04/11 08:09:32 dlg Exp $ */
2 /* $NetBSD: ehci.c,v 1.66 2004/06/30 03:11:56 mycroft Exp $ */
3
4 /*
5 * Copyright (c) 2004 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Lennart Augustsson (lennart@augustsson.net) and by Charles M. Hannum.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * USB Enhanced Host Controller Driver, a.k.a. USB 2.0 controller.
42 *
43 * The EHCI 1.0 spec can be found at
44 * http://developer.intel.com/technology/usb/download/ehci-r10.pdf
45 * and the USB 2.0 spec at
46 * http://www.usb.org/developers/docs/usb_20.zip
47 */
48
49 /*
50 * TODO:
51 * 1) The meaty part to implement is isochronous transactions. They are
52 * needed for USB 1 devices below USB 2.0 hubs. They are quite complicated
53 * since they need to be able to do "transaction translation", ie,
54 * converting to/from USB 2 and USB 1.
55 * So the hub driver needs to handle and schedule these things, to
56 * assign place in frame where different devices get to go. See chapter
57 * on hubs in USB 2.0 for details.
58 *
59 * 2) Command failures are not recovered correctly.
60 */
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/kernel.h>
65 #include <sys/malloc.h>
66 #include <sys/device.h>
67 #include <sys/select.h>
68 #include <sys/proc.h>
69 #include <sys/queue.h>
70
71 #include <machine/bus.h>
72 #include <machine/endian.h>
73
74 #include <dev/usb/usb.h>
75 #include <dev/usb/usbdi.h>
76 #include <dev/usb/usbdivar.h>
77 #include <dev/usb/usb_mem.h>
78 #include <dev/usb/usb_quirks.h>
79
80 #include <dev/usb/ehcireg.h>
81 #include <dev/usb/ehcivar.h>
82
83 #include <dev/rndvar.h>
84
85 #if defined(__OpenBSD__)
86 struct cfdriver ehci_cd = {
87 NULL, "ehci", DV_DULL
88 };
89 #endif
90
91 #ifdef USB_DEBUG
92 #define EHCI_DEBUG
93 #endif
94
95 #ifdef EHCI_DEBUG
96 #define DPRINTF(x) do { if (ehcidebug) printf x; } while(0)
97 #define DPRINTFN(n,x) do { if (ehcidebug>(n)) printf x; } while (0)
98 int ehcidebug = 0;
99 #ifndef __NetBSD__
100 #define bitmask_snprintf(q,f,b,l) snprintf((b), (l), "%b", (q), (f))
101 #endif
102 #else
103 #define DPRINTF(x)
104 #define DPRINTFN(n,x)
105 #endif
106
107 struct ehci_pipe {
108 struct usbd_pipe pipe;
109 int nexttoggle;
110
111 ehci_soft_qh_t *sqh;
112 union {
113 ehci_soft_qtd_t *qtd;
114 /* ehci_soft_itd_t *itd; */
115 } tail;
116 union {
117 /* Control pipe */
118 struct {
119 usb_dma_t reqdma;
120 u_int length;
121 /*ehci_soft_qtd_t *setup, *data, *stat;*/
122 } ctl;
123 /* Interrupt pipe */
124 struct {
125 u_int length;
126 } intr;
127 /* Bulk pipe */
128 struct {
129 u_int length;
130 } bulk;
131 /* Iso pipe */
132 /* XXX */
133 } u;
134 };
135
136 Static u_int8_t ehci_reverse_bits(u_int8_t, int);
137
138 Static void ehci_power(int, void *);
139
140 Static usbd_status ehci_open(usbd_pipe_handle);
141 Static void ehci_poll(struct usbd_bus *);
142 Static void ehci_softintr(void *);
143 Static int ehci_intr1(ehci_softc_t *);
144 Static void ehci_waitintr(ehci_softc_t *, usbd_xfer_handle);
145 Static void ehci_check_intr(ehci_softc_t *, struct ehci_xfer *);
146 Static void ehci_idone(struct ehci_xfer *);
147 Static void ehci_timeout(void *);
148 Static void ehci_timeout_task(void *);
149 Static void ehci_intrlist_timeout(void *);
150
151 Static usbd_status ehci_allocm(struct usbd_bus *, usb_dma_t *, u_int32_t);
152 Static void ehci_freem(struct usbd_bus *, usb_dma_t *);
153
154 Static usbd_xfer_handle ehci_allocx(struct usbd_bus *);
155 Static void ehci_freex(struct usbd_bus *, usbd_xfer_handle);
156
157 Static usbd_status ehci_root_ctrl_transfer(usbd_xfer_handle);
158 Static usbd_status ehci_root_ctrl_start(usbd_xfer_handle);
159 Static void ehci_root_ctrl_abort(usbd_xfer_handle);
160 Static void ehci_root_ctrl_close(usbd_pipe_handle);
161 Static void ehci_root_ctrl_done(usbd_xfer_handle);
162
163 Static usbd_status ehci_root_intr_transfer(usbd_xfer_handle);
164 Static usbd_status ehci_root_intr_start(usbd_xfer_handle);
165 Static void ehci_root_intr_abort(usbd_xfer_handle);
166 Static void ehci_root_intr_close(usbd_pipe_handle);
167 Static void ehci_root_intr_done(usbd_xfer_handle);
168
169 Static usbd_status ehci_device_ctrl_transfer(usbd_xfer_handle);
170 Static usbd_status ehci_device_ctrl_start(usbd_xfer_handle);
171 Static void ehci_device_ctrl_abort(usbd_xfer_handle);
172 Static void ehci_device_ctrl_close(usbd_pipe_handle);
173 Static void ehci_device_ctrl_done(usbd_xfer_handle);
174
175 Static usbd_status ehci_device_bulk_transfer(usbd_xfer_handle);
176 Static usbd_status ehci_device_bulk_start(usbd_xfer_handle);
177 Static void ehci_device_bulk_abort(usbd_xfer_handle);
178 Static void ehci_device_bulk_close(usbd_pipe_handle);
179 Static void ehci_device_bulk_done(usbd_xfer_handle);
180
181 Static usbd_status ehci_device_intr_transfer(usbd_xfer_handle);
182 Static usbd_status ehci_device_intr_start(usbd_xfer_handle);
183 Static void ehci_device_intr_abort(usbd_xfer_handle);
184 Static void ehci_device_intr_close(usbd_pipe_handle);
185 Static void ehci_device_intr_done(usbd_xfer_handle);
186
187 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle);
188 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle);
189 Static void ehci_device_isoc_abort(usbd_xfer_handle);
190 Static void ehci_device_isoc_close(usbd_pipe_handle);
191 Static void ehci_device_isoc_done(usbd_xfer_handle);
192
193 Static void ehci_device_clear_toggle(usbd_pipe_handle pipe);
194 Static void ehci_noop(usbd_pipe_handle pipe);
195
196 Static int ehci_str(usb_string_descriptor_t *, int, char *);
197 Static void ehci_pcd(ehci_softc_t *, usbd_xfer_handle);
198 Static void ehci_pcd_able(ehci_softc_t *, int);
199 Static void ehci_pcd_enable(void *);
200 Static void ehci_disown(ehci_softc_t *, int, int);
201
202 Static ehci_soft_qh_t *ehci_alloc_sqh(ehci_softc_t *);
203 Static void ehci_free_sqh(ehci_softc_t *, ehci_soft_qh_t *);
204
205 Static ehci_soft_qtd_t *ehci_alloc_sqtd(ehci_softc_t *);
206 Static void ehci_free_sqtd(ehci_softc_t *, ehci_soft_qtd_t *);
207 Static usbd_status ehci_alloc_sqtd_chain(struct ehci_pipe *,
208 ehci_softc_t *, int, int, usbd_xfer_handle,
209 ehci_soft_qtd_t **, ehci_soft_qtd_t **);
210 Static void ehci_free_sqtd_chain(ehci_softc_t *, ehci_soft_qtd_t *,
211 ehci_soft_qtd_t *);
212
213 Static usbd_status ehci_device_request(usbd_xfer_handle xfer);
214
215 Static usbd_status ehci_device_setintr(ehci_softc_t *, ehci_soft_qh_t *,
216 int ival);
217
218 Static void ehci_add_qh(ehci_soft_qh_t *, ehci_soft_qh_t *);
219 Static void ehci_rem_qh(ehci_softc_t *, ehci_soft_qh_t *,
220 ehci_soft_qh_t *);
221 Static void ehci_set_qh_qtd(ehci_soft_qh_t *, ehci_soft_qtd_t *);
222 Static void ehci_sync_hc(ehci_softc_t *);
223
224 Static void ehci_close_pipe(usbd_pipe_handle, ehci_soft_qh_t *);
225 Static void ehci_abort_xfer(usbd_xfer_handle, usbd_status);
226
227 #ifdef EHCI_DEBUG
228 Static void ehci_dump_regs(ehci_softc_t *);
229 Static void ehci_dump(void);
230 Static ehci_softc_t *theehci;
231 Static void ehci_dump_link(ehci_link_t, int);
232 Static void ehci_dump_sqtds(ehci_soft_qtd_t *);
233 Static void ehci_dump_sqtd(ehci_soft_qtd_t *);
234 Static void ehci_dump_qtd(ehci_qtd_t *);
235 Static void ehci_dump_sqh(ehci_soft_qh_t *);
236 #ifdef DIAGNOSTIC
237 Static void ehci_dump_exfer(struct ehci_xfer *);
238 #endif
239 #endif
240
241 #define EHCI_NULL htole32(EHCI_LINK_TERMINATE)
242
243 #define EHCI_INTR_ENDPT 1
244
245 #define ehci_add_intr_list(sc, ex) \
246 LIST_INSERT_HEAD(&(sc)->sc_intrhead, (ex), inext);
247 #define ehci_del_intr_list(ex) \
248 do { \
249 LIST_REMOVE((ex), inext); \
250 (ex)->inext.le_prev = NULL; \
251 } while (0)
252 #define ehci_active_intr_list(ex) ((ex)->inext.le_prev != NULL)
253
254 Static struct usbd_bus_methods ehci_bus_methods = {
255 ehci_open,
256 ehci_softintr,
257 ehci_poll,
258 ehci_allocm,
259 ehci_freem,
260 ehci_allocx,
261 ehci_freex,
262 };
263
264 Static struct usbd_pipe_methods ehci_root_ctrl_methods = {
265 ehci_root_ctrl_transfer,
266 ehci_root_ctrl_start,
267 ehci_root_ctrl_abort,
268 ehci_root_ctrl_close,
269 ehci_noop,
270 ehci_root_ctrl_done,
271 };
272
273 Static struct usbd_pipe_methods ehci_root_intr_methods = {
274 ehci_root_intr_transfer,
275 ehci_root_intr_start,
276 ehci_root_intr_abort,
277 ehci_root_intr_close,
278 ehci_noop,
279 ehci_root_intr_done,
280 };
281
282 Static struct usbd_pipe_methods ehci_device_ctrl_methods = {
283 ehci_device_ctrl_transfer,
284 ehci_device_ctrl_start,
285 ehci_device_ctrl_abort,
286 ehci_device_ctrl_close,
287 ehci_noop,
288 ehci_device_ctrl_done,
289 };
290
291 Static struct usbd_pipe_methods ehci_device_intr_methods = {
292 ehci_device_intr_transfer,
293 ehci_device_intr_start,
294 ehci_device_intr_abort,
295 ehci_device_intr_close,
296 ehci_device_clear_toggle,
297 ehci_device_intr_done,
298 };
299
300 Static struct usbd_pipe_methods ehci_device_bulk_methods = {
301 ehci_device_bulk_transfer,
302 ehci_device_bulk_start,
303 ehci_device_bulk_abort,
304 ehci_device_bulk_close,
305 ehci_device_clear_toggle,
306 ehci_device_bulk_done,
307 };
308
309 Static struct usbd_pipe_methods ehci_device_isoc_methods = {
310 ehci_device_isoc_transfer,
311 ehci_device_isoc_start,
312 ehci_device_isoc_abort,
313 ehci_device_isoc_close,
314 ehci_noop,
315 ehci_device_isoc_done,
316 };
317
318 /*
319 * Reverse a number with nbits bits. Used to evenly distribute lower-level
320 * interrupt heads in the periodic schedule.
321 * Suitable for use with EHCI_IPOLLRATES <= 9.
322 */
323 Static u_int8_t
ehci_reverse_bits(u_int8_t c,int nbits)324 ehci_reverse_bits(u_int8_t c, int nbits)
325 {
326 c = ((c >> 1) & 0x55) | ((c << 1) & 0xaa);
327 c = ((c >> 2) & 0x33) | ((c << 2) & 0xcc);
328 c = ((c >> 4) & 0x0f) | ((c << 4) & 0xf0);
329
330 return c >> (8 - nbits);
331 }
332
333 usbd_status
ehci_init(ehci_softc_t * sc)334 ehci_init(ehci_softc_t *sc)
335 {
336 u_int32_t sparams, cparams, hcr;
337 u_int i, j;
338 usbd_status err;
339 ehci_soft_qh_t *sqh;
340
341 #ifdef EHCI_DEBUG
342 u_int32_t version;
343 theehci = sc;
344
345 DPRINTF(("ehci_init: start\n"));
346
347 version = EREAD2(sc, EHCI_HCIVERSION);
348 DPRINTF(("%s: EHCI version %x.%x\n", USBDEVNAME(sc->sc_bus.bdev),
349 version >> 8, version & 0xff));
350 #endif
351
352 sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
353
354 sparams = EREAD4(sc, EHCI_HCSPARAMS);
355 DPRINTF(("ehci_init: sparams=0x%x\n", sparams));
356 sc->sc_noport = EHCI_HCS_N_PORTS(sparams);
357 cparams = EREAD4(sc, EHCI_HCCPARAMS);
358 DPRINTF(("ehci_init: cparams=0x%x\n", cparams));
359
360 /* MUST clear segment register if 64 bit capable. */
361 if (EHCI_HCC_64BIT(cparams))
362 EWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
363
364 sc->sc_bus.usbrev = USBREV_2_0;
365
366 /* Reset the controller */
367 DPRINTF(("%s: resetting\n", USBDEVNAME(sc->sc_bus.bdev)));
368 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
369 usb_delay_ms(&sc->sc_bus, 1);
370 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
371 for (i = 0; i < 100; i++) {
372 usb_delay_ms(&sc->sc_bus, 1);
373 hcr = EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_HCRESET;
374 if (!hcr)
375 break;
376 }
377 if (hcr) {
378 printf("%s: reset timeout\n",
379 USBDEVNAME(sc->sc_bus.bdev));
380 return (USBD_IOERROR);
381 }
382
383 /* XXX need proper intr scheduling */
384 sc->sc_rand = 96;
385
386 /* frame list size at default, read back what we got and use that */
387 switch (EHCI_CMD_FLS(EOREAD4(sc, EHCI_USBCMD))) {
388 case 0: sc->sc_flsize = 1024; break;
389 case 1: sc->sc_flsize = 512; break;
390 case 2: sc->sc_flsize = 256; break;
391 case 3: return (USBD_IOERROR);
392 }
393 err = usb_allocmem(&sc->sc_bus, sc->sc_flsize * sizeof(ehci_link_t),
394 EHCI_FLALIGN_ALIGN, &sc->sc_fldma);
395 if (err)
396 return (err);
397 DPRINTF(("%s: flsize=%d\n", USBDEVNAME(sc->sc_bus.bdev),sc->sc_flsize));
398 sc->sc_flist = KERNADDR(&sc->sc_fldma, 0);
399 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
400
401 /* Set up the bus struct. */
402 sc->sc_bus.methods = &ehci_bus_methods;
403 sc->sc_bus.pipe_size = sizeof(struct ehci_pipe);
404
405 sc->sc_powerhook = powerhook_establish(ehci_power, sc);
406
407 sc->sc_eintrs = EHCI_NORMAL_INTRS;
408
409 /*
410 * Allocate the interrupt dummy QHs. These are arranged to give poll
411 * intervals that are powers of 2 times 1ms.
412 */
413 for (i = 0; i < EHCI_INTRQHS; i++) {
414 sqh = ehci_alloc_sqh(sc);
415 if (sqh == NULL) {
416 err = USBD_NOMEM;
417 goto bad1;
418 }
419 sc->sc_islots[i].sqh = sqh;
420 }
421 for (i = 0; i < EHCI_INTRQHS; i++) {
422 sqh = sc->sc_islots[i].sqh;
423 if (i == 0) {
424 /* The last (1ms) QH terminates. */
425 sqh->qh.qh_link = EHCI_NULL;
426 sqh->next = NULL;
427 } else {
428 /* Otherwise the next QH has half the poll interval */
429 sqh->next = sc->sc_islots[(i + 1) / 2 - 1].sqh;
430 sqh->qh.qh_link = htole32(sqh->next->physaddr |
431 EHCI_LINK_QH);
432 }
433 sqh->qh.qh_endp = htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH));
434 sqh->qh.qh_endphub = htole32(EHCI_QH_SET_MULT(1));
435 sqh->qh.qh_curqtd = EHCI_NULL;
436 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
437 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
438 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
439 sqh->sqtd = NULL;
440 }
441 /* Point the frame list at the last level (128ms). */
442 for (i = 0; i < (1 << (EHCI_IPOLLRATES - 1)); i++)
443 for (j = i; j < sc->sc_flsize; j += 1 << (EHCI_IPOLLRATES - 1))
444 sc->sc_flist[j] = htole32(EHCI_LINK_QH | sc->sc_islots[
445 EHCI_IQHIDX(EHCI_IPOLLRATES - 1, ehci_reverse_bits(
446 i, EHCI_IPOLLRATES - 1))].sqh->physaddr);
447
448 /* Allocate dummy QH that starts the async list. */
449 sqh = ehci_alloc_sqh(sc);
450 if (sqh == NULL) {
451 err = USBD_NOMEM;
452 goto bad1;
453 }
454 /* Fill the QH */
455 sqh->qh.qh_endp =
456 htole32(EHCI_QH_SET_EPS(EHCI_QH_SPEED_HIGH) | EHCI_QH_HRECL);
457 sqh->qh.qh_link =
458 htole32(sqh->physaddr | EHCI_LINK_QH);
459 sqh->qh.qh_curqtd = EHCI_NULL;
460 sqh->next = NULL;
461 /* Fill the overlay qTD */
462 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
463 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
464 sqh->qh.qh_qtd.qtd_status = htole32(EHCI_QTD_HALTED);
465 sqh->sqtd = NULL;
466 #ifdef EHCI_DEBUG
467 if (ehcidebug)
468 ehci_dump_sqh(sqh);
469 #endif
470
471 /* Point to async list */
472 sc->sc_async_head = sqh;
473 EOWRITE4(sc, EHCI_ASYNCLISTADDR, sqh->physaddr | EHCI_LINK_QH);
474
475 usb_callout_init(sc->sc_tmo_pcd);
476 usb_callout_init(sc->sc_tmo_intrlist);
477
478 lockinit(&sc->sc_doorbell_lock, PZERO, "ehcidb", 0, 0);
479
480 /* Enable interrupts */
481 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
482
483 /* Turn on controller */
484 EOWRITE4(sc, EHCI_USBCMD,
485 EHCI_CMD_ITC_2 | /* 2 microframes */
486 (EOREAD4(sc, EHCI_USBCMD) & EHCI_CMD_FLS_M) |
487 EHCI_CMD_ASE |
488 EHCI_CMD_PSE |
489 EHCI_CMD_RS);
490
491 /* Take over port ownership */
492 EOWRITE4(sc, EHCI_CONFIGFLAG, EHCI_CONF_CF);
493
494 for (i = 0; i < 100; i++) {
495 usb_delay_ms(&sc->sc_bus, 1);
496 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
497 if (!hcr)
498 break;
499 }
500 if (hcr) {
501 printf("%s: run timeout\n", USBDEVNAME(sc->sc_bus.bdev));
502 return (USBD_IOERROR);
503 }
504
505 return (USBD_NORMAL_COMPLETION);
506
507 #if 0
508 bad2:
509 ehci_free_sqh(sc, sc->sc_async_head);
510 #endif
511 bad1:
512 usb_freemem(&sc->sc_bus, &sc->sc_fldma);
513 return (err);
514 }
515
516 int
ehci_intr(void * v)517 ehci_intr(void *v)
518 {
519 ehci_softc_t *sc = v;
520
521 if (sc == NULL || sc->sc_dying)
522 return (0);
523
524 /* If we get an interrupt while polling, then just ignore it. */
525 if (sc->sc_bus.use_polling) {
526 u_int32_t intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
527
528 if (intrs)
529 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
530 return (0);
531 }
532
533 return (ehci_intr1(sc));
534 }
535
536 Static int
ehci_intr1(ehci_softc_t * sc)537 ehci_intr1(ehci_softc_t *sc)
538 {
539 u_int32_t intrs, eintrs;
540
541 DPRINTFN(20,("ehci_intr1: enter\n"));
542
543 /* In case the interrupt occurs before initialization has completed. */
544 if (sc == NULL) {
545 #ifdef DIAGNOSTIC
546 printf("ehci_intr1: sc == NULL\n");
547 #endif
548 return (0);
549 }
550
551 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
552 if (!intrs)
553 return (0);
554
555 eintrs = intrs & sc->sc_eintrs;
556 DPRINTFN(7, ("ehci_intr1: sc=%p intrs=0x%x(0x%x) eintrs=0x%x\n",
557 sc, (u_int)intrs, EOREAD4(sc, EHCI_USBSTS), (u_int)eintrs));
558 if (!eintrs)
559 return (0);
560
561 EOWRITE4(sc, EHCI_USBSTS, intrs); /* Acknowledge */
562 sc->sc_bus.intr_context++;
563 sc->sc_bus.no_intrs++;
564 if (eintrs & EHCI_STS_IAA) {
565 DPRINTF(("ehci_intr1: door bell\n"));
566 wakeup(&sc->sc_async_head);
567 eintrs &= ~EHCI_STS_IAA;
568 }
569 if (eintrs & (EHCI_STS_INT | EHCI_STS_ERRINT)) {
570 DPRINTFN(5,("ehci_intr1: %s %s\n",
571 eintrs & EHCI_STS_INT ? "INT" : "",
572 eintrs & EHCI_STS_ERRINT ? "ERRINT" : ""));
573 usb_schedsoftintr(&sc->sc_bus);
574 eintrs &= ~(EHCI_STS_INT | EHCI_STS_ERRINT);
575 }
576 if (eintrs & EHCI_STS_HSE) {
577 printf("%s: unrecoverable error, controller halted\n",
578 USBDEVNAME(sc->sc_bus.bdev));
579 /* XXX what else */
580 }
581 if (eintrs & EHCI_STS_PCD) {
582 ehci_pcd(sc, sc->sc_intrxfer);
583 /*
584 * Disable PCD interrupt for now, because it will be
585 * on until the port has been reset.
586 */
587 ehci_pcd_able(sc, 0);
588 /* Do not allow RHSC interrupts > 1 per second */
589 usb_callout(sc->sc_tmo_pcd, hz, ehci_pcd_enable, sc);
590 eintrs &= ~EHCI_STS_PCD;
591 }
592
593 sc->sc_bus.intr_context--;
594
595 if (eintrs != 0) {
596 /* Block unprocessed interrupts. */
597 sc->sc_eintrs &= ~eintrs;
598 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
599 printf("%s: blocking intrs 0x%x\n",
600 USBDEVNAME(sc->sc_bus.bdev), eintrs);
601 }
602
603 return (1);
604 }
605
606 void
ehci_pcd_able(ehci_softc_t * sc,int on)607 ehci_pcd_able(ehci_softc_t *sc, int on)
608 {
609 DPRINTFN(4, ("ehci_pcd_able: on=%d\n", on));
610 if (on)
611 sc->sc_eintrs |= EHCI_STS_PCD;
612 else
613 sc->sc_eintrs &= ~EHCI_STS_PCD;
614 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
615 }
616
617 void
ehci_pcd_enable(void * v_sc)618 ehci_pcd_enable(void *v_sc)
619 {
620 ehci_softc_t *sc = v_sc;
621
622 ehci_pcd_able(sc, 1);
623 }
624
625 void
ehci_pcd(ehci_softc_t * sc,usbd_xfer_handle xfer)626 ehci_pcd(ehci_softc_t *sc, usbd_xfer_handle xfer)
627 {
628 usbd_pipe_handle pipe;
629 u_char *p;
630 int i, m;
631
632 if (xfer == NULL) {
633 /* Just ignore the change. */
634 return;
635 }
636
637 pipe = xfer->pipe;
638
639 p = KERNADDR(&xfer->dmabuf, 0);
640 m = min(sc->sc_noport, xfer->length * 8 - 1);
641 memset(p, 0, xfer->length);
642 for (i = 1; i <= m; i++) {
643 /* Pick out CHANGE bits from the status reg. */
644 if (EOREAD4(sc, EHCI_PORTSC(i)) & EHCI_PS_CLEAR)
645 p[i/8] |= 1 << (i%8);
646 }
647 DPRINTF(("ehci_pcd: change=0x%02x\n", *p));
648 xfer->actlen = xfer->length;
649 xfer->status = USBD_NORMAL_COMPLETION;
650
651 usb_transfer_complete(xfer);
652 }
653
654 void
ehci_softintr(void * v)655 ehci_softintr(void *v)
656 {
657 ehci_softc_t *sc = v;
658 struct ehci_xfer *ex, *nextex;
659
660 DPRINTFN(10,("%s: ehci_softintr (%d)\n", USBDEVNAME(sc->sc_bus.bdev),
661 sc->sc_bus.intr_context));
662
663 sc->sc_bus.intr_context++;
664
665 /*
666 * The only explanation I can think of for why EHCI is as brain dead
667 * as UHCI interrupt-wise is that Intel was involved in both.
668 * An interrupt just tells us that something is done, we have no
669 * clue what, so we need to scan through all active transfers. :-(
670 */
671 for (ex = LIST_FIRST(&sc->sc_intrhead); ex; ex = nextex) {
672 nextex = LIST_NEXT(ex, inext);
673 ehci_check_intr(sc, ex);
674 }
675
676 /* Schedule a callout to catch any dropped transactions. */
677 if ((sc->sc_flags & EHCIF_DROPPED_INTR_WORKAROUND) &&
678 !LIST_EMPTY(&sc->sc_intrhead))
679 usb_callout(sc->sc_tmo_intrlist, hz,
680 ehci_intrlist_timeout, sc);
681
682 #ifdef USB_USE_SOFTINTR
683 if (sc->sc_softwake) {
684 sc->sc_softwake = 0;
685 wakeup(&sc->sc_softwake);
686 }
687 #endif /* USB_USE_SOFTINTR */
688
689 sc->sc_bus.intr_context--;
690 }
691
692 /* Check for an interrupt. */
693 void
ehci_check_intr(ehci_softc_t * sc,struct ehci_xfer * ex)694 ehci_check_intr(ehci_softc_t *sc, struct ehci_xfer *ex)
695 {
696 ehci_soft_qtd_t *sqtd, *lsqtd;
697 u_int32_t status;
698
699 DPRINTFN(/*15*/2, ("ehci_check_intr: ex=%p\n", ex));
700
701 if (ex->sqtdstart == NULL) {
702 printf("ehci_check_intr: sqtdstart=NULL\n");
703 return;
704 }
705 lsqtd = ex->sqtdend;
706 #ifdef DIAGNOSTIC
707 if (lsqtd == NULL) {
708 printf("ehci_check_intr: lsqtd==0\n");
709 return;
710 }
711 #endif
712 /*
713 * If the last TD is still active we need to check whether there
714 * is a an error somewhere in the middle, or whether there was a
715 * short packet (SPD and not ACTIVE).
716 */
717 if (le32toh(lsqtd->qtd.qtd_status) & EHCI_QTD_ACTIVE) {
718 DPRINTFN(12, ("ehci_check_intr: active ex=%p\n", ex));
719 for (sqtd = ex->sqtdstart; sqtd != lsqtd; sqtd=sqtd->nextqtd) {
720 status = le32toh(sqtd->qtd.qtd_status);
721 /* If there's an active QTD the xfer isn't done. */
722 if (status & EHCI_QTD_ACTIVE)
723 break;
724 /* Any kind of error makes the xfer done. */
725 if (status & EHCI_QTD_HALTED)
726 goto done;
727 /* We want short packets, and it is short: it's done */
728 if (EHCI_QTD_GET_BYTES(status) != 0)
729 goto done;
730 }
731 DPRINTFN(12, ("ehci_check_intr: ex=%p std=%p still active\n",
732 ex, ex->sqtdstart));
733 return;
734 }
735 done:
736 DPRINTFN(12, ("ehci_check_intr: ex=%p done\n", ex));
737 usb_uncallout(ex->xfer.timeout_handle, ehci_timeout, ex);
738 ehci_idone(ex);
739 }
740
741 void
ehci_idone(struct ehci_xfer * ex)742 ehci_idone(struct ehci_xfer *ex)
743 {
744 usbd_xfer_handle xfer = &ex->xfer;
745 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
746 ehci_soft_qtd_t *sqtd, *lsqtd;
747 u_int32_t status = 0, nstatus = 0;
748 int actlen, cerr;
749 uint pkts_left;
750
751 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p\n", ex));
752 #ifdef DIAGNOSTIC
753 {
754 int s = splhigh();
755 if (ex->isdone) {
756 splx(s);
757 #ifdef EHCI_DEBUG
758 printf("ehci_idone: ex is done!\n ");
759 ehci_dump_exfer(ex);
760 #else
761 printf("ehci_idone: ex=%p is done!\n", ex);
762 #endif
763 return;
764 }
765 ex->isdone = 1;
766 splx(s);
767 }
768 #endif
769
770 if (xfer->status == USBD_CANCELLED ||
771 xfer->status == USBD_TIMEOUT) {
772 DPRINTF(("ehci_idone: aborted xfer=%p\n", xfer));
773 return;
774 }
775
776 #ifdef EHCI_DEBUG
777 DPRINTFN(/*10*/2, ("ehci_idone: xfer=%p, pipe=%p ready\n", xfer, epipe));
778 if (ehcidebug > 10)
779 ehci_dump_sqtds(ex->sqtdstart);
780 #endif
781
782 /* The transfer is done, compute actual length and status. */
783 lsqtd = ex->sqtdend;
784 actlen = 0;
785 for (sqtd = ex->sqtdstart; sqtd != lsqtd->nextqtd;
786 sqtd = sqtd->nextqtd) {
787 nstatus = le32toh(sqtd->qtd.qtd_status);
788 if (nstatus & EHCI_QTD_ACTIVE)
789 break;
790
791 status = nstatus;
792 /* halt is ok if descriptor is last, and complete */
793 if (sqtd->qtd.qtd_next == EHCI_NULL &&
794 EHCI_QTD_GET_BYTES(status) == 0)
795 status &= ~EHCI_QTD_HALTED;
796 if (EHCI_QTD_GET_PID(status) != EHCI_QTD_PID_SETUP)
797 actlen += sqtd->len - EHCI_QTD_GET_BYTES(status);
798 }
799
800 /*
801 * If there are left over TDs we need to update the toggle.
802 * The default pipe doesn't need it since control transfers
803 * start the toggle at 0 every time.
804 */
805 if (sqtd != lsqtd->nextqtd &&
806 xfer->pipe->device->default_pipe != xfer->pipe) {
807 DPRINTF(("ehci_idone: need toggle update status=%08x "
808 "nstatus=%08x\n", status, nstatus));
809 epipe->nexttoggle = EHCI_QTD_GET_TOGGLE(nstatus);
810 }
811
812 /*
813 * For a short transfer we need to update the toggle for the missing
814 * packets within the qTD.
815 */
816 pkts_left = EHCI_QTD_GET_BYTES(status) /
817 UGETW(xfer->pipe->endpoint->edesc->wMaxPacketSize);
818 epipe->nexttoggle ^= pkts_left % 2;
819
820 cerr = EHCI_QTD_GET_CERR(status);
821 DPRINTFN(/*10*/2, ("ehci_idone: len=%d, actlen=%d, cerr=%d, "
822 "status=0x%x\n", xfer->length, actlen, cerr, status));
823 xfer->actlen = actlen;
824 if ((status & EHCI_QTD_HALTED) != 0) {
825 #ifdef EHCI_DEBUG
826 char sbuf[128];
827
828 bitmask_snprintf((u_int32_t)status,
829 "\20\7HALTED\6BUFERR\5BABBLE\4XACTERR"
830 "\3MISSED\2SPLIT\1PING", sbuf, sizeof(sbuf));
831
832 DPRINTFN(2,
833 ("ehci_idone: error, addr=%d, endpt=0x%02x, "
834 "status 0x%s\n",
835 xfer->pipe->device->address,
836 xfer->pipe->endpoint->edesc->bEndpointAddress,
837 sbuf));
838 if (ehcidebug > 2) {
839 ehci_dump_sqh(epipe->sqh);
840 ehci_dump_sqtds(ex->sqtdstart);
841 }
842 #endif
843 if ((status & EHCI_QTD_BABBLE) == 0 && cerr > 0)
844 xfer->status = USBD_STALLED;
845 else
846 xfer->status = USBD_IOERROR; /* more info XXX */
847 } else
848 xfer->status = USBD_NORMAL_COMPLETION;
849
850 usb_transfer_complete(xfer);
851 DPRINTFN(/*12*/2, ("ehci_idone: ex=%p done\n", ex));
852 }
853
854 /*
855 * Wait here until controller claims to have an interrupt.
856 * Then call ehci_intr and return. Use timeout to avoid waiting
857 * too long.
858 */
859 void
ehci_waitintr(ehci_softc_t * sc,usbd_xfer_handle xfer)860 ehci_waitintr(ehci_softc_t *sc, usbd_xfer_handle xfer)
861 {
862 int timo;
863 u_int32_t intrs;
864
865 xfer->status = USBD_IN_PROGRESS;
866 for (timo = xfer->timeout; timo >= 0; timo--) {
867 usb_delay_ms(&sc->sc_bus, 1);
868 if (sc->sc_dying)
869 break;
870 intrs = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS)) &
871 sc->sc_eintrs;
872 DPRINTFN(15,("ehci_waitintr: 0x%04x\n", intrs));
873 #ifdef EHCI_DEBUG
874 if (ehcidebug > 15)
875 ehci_dump_regs(sc);
876 #endif
877 if (intrs) {
878 ehci_intr1(sc);
879 if (xfer->status != USBD_IN_PROGRESS)
880 return;
881 }
882 }
883
884 /* Timeout */
885 DPRINTF(("ehci_waitintr: timeout\n"));
886 xfer->status = USBD_TIMEOUT;
887 usb_transfer_complete(xfer);
888 /* XXX should free TD */
889 }
890
891 void
ehci_poll(struct usbd_bus * bus)892 ehci_poll(struct usbd_bus *bus)
893 {
894 ehci_softc_t *sc = (ehci_softc_t *)bus;
895 #ifdef EHCI_DEBUG
896 static int last;
897 int new;
898 new = EHCI_STS_INTRS(EOREAD4(sc, EHCI_USBSTS));
899 if (new != last) {
900 DPRINTFN(10,("ehci_poll: intrs=0x%04x\n", new));
901 last = new;
902 }
903 #endif
904
905 if (EOREAD4(sc, EHCI_USBSTS) & sc->sc_eintrs)
906 ehci_intr1(sc);
907 }
908
909 int
ehci_detach(struct ehci_softc * sc,int flags)910 ehci_detach(struct ehci_softc *sc, int flags)
911 {
912 int rv = 0;
913
914 if (sc->sc_child != NULL)
915 rv = config_detach(sc->sc_child, flags);
916
917 if (rv != 0)
918 return (rv);
919
920 usb_uncallout(sc->sc_tmo_intrlist, ehci_intrlist_timeout, sc);
921 usb_uncallout(sc->sc_tmo_pcd, ehci_pcd_enable, sc);
922
923 if (sc->sc_powerhook != NULL)
924 powerhook_disestablish(sc->sc_powerhook);
925 if (sc->sc_shutdownhook != NULL)
926 shutdownhook_disestablish(sc->sc_shutdownhook);
927
928 usb_delay_ms(&sc->sc_bus, 300); /* XXX let stray task complete */
929
930 /* XXX free other data structures XXX */
931
932 return (rv);
933 }
934
935
936 int
ehci_activate(device_ptr_t self,enum devact act)937 ehci_activate(device_ptr_t self, enum devact act)
938 {
939 struct ehci_softc *sc = (struct ehci_softc *)self;
940 int rv = 0;
941
942 switch (act) {
943 case DVACT_ACTIVATE:
944 return (EOPNOTSUPP);
945
946 case DVACT_DEACTIVATE:
947 if (sc->sc_child != NULL)
948 rv = config_deactivate(sc->sc_child);
949 sc->sc_dying = 1;
950 break;
951 }
952 return (rv);
953 }
954
955 /*
956 * Handle suspend/resume.
957 *
958 * We need to switch to polling mode here, because this routine is
959 * called from an interrupt context. This is all right since we
960 * are almost suspended anyway.
961 */
962 void
ehci_power(int why,void * v)963 ehci_power(int why, void *v)
964 {
965 ehci_softc_t *sc = v;
966 u_int32_t cmd, hcr;
967 int s, i;
968
969 #ifdef EHCI_DEBUG
970 DPRINTF(("ehci_power: sc=%p, why=%d\n", sc, why));
971 if (ehcidebug > 0)
972 ehci_dump_regs(sc);
973 #endif
974
975 s = splhardusb();
976 switch (why) {
977 case PWR_SUSPEND:
978 case PWR_STANDBY:
979 sc->sc_bus.use_polling++;
980
981 for (i = 1; i <= sc->sc_noport; i++) {
982 cmd = EOREAD4(sc, EHCI_PORTSC(i));
983 if ((cmd & (EHCI_PS_PO|EHCI_PS_PE)) == EHCI_PS_PE)
984 EOWRITE4(sc, EHCI_PORTSC(i),
985 cmd | EHCI_PS_SUSP);
986 }
987
988 sc->sc_cmd = EOREAD4(sc, EHCI_USBCMD);
989 cmd = sc->sc_cmd & ~(EHCI_CMD_ASE | EHCI_CMD_PSE);
990 EOWRITE4(sc, EHCI_USBCMD, cmd);
991
992 for (i = 0; i < 100; i++) {
993 hcr = EOREAD4(sc, EHCI_USBSTS) &
994 (EHCI_STS_ASS | EHCI_STS_PSS);
995 if (hcr == 0)
996 break;
997
998 usb_delay_ms(&sc->sc_bus, 1);
999 }
1000 if (hcr != 0)
1001 printf("%s: reset timeout\n",
1002 USBDEVNAME(sc->sc_bus.bdev));
1003
1004 cmd &= ~EHCI_CMD_RS;
1005 EOWRITE4(sc, EHCI_USBCMD, cmd);
1006
1007 for (i = 0; i < 100; i++) {
1008 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1009 if (hcr == EHCI_STS_HCH)
1010 break;
1011
1012 usb_delay_ms(&sc->sc_bus, 1);
1013 }
1014 if (hcr != EHCI_STS_HCH)
1015 printf("%s: config timeout\n",
1016 USBDEVNAME(sc->sc_bus.bdev));
1017
1018 sc->sc_bus.use_polling--;
1019 break;
1020
1021 case PWR_RESUME:
1022 sc->sc_bus.use_polling++;
1023
1024 /* restore things in case the bios sucks */
1025 EOWRITE4(sc, EHCI_CTRLDSSEGMENT, 0);
1026 EOWRITE4(sc, EHCI_PERIODICLISTBASE, DMAADDR(&sc->sc_fldma, 0));
1027 EOWRITE4(sc, EHCI_ASYNCLISTADDR,
1028 sc->sc_async_head->physaddr | EHCI_LINK_QH);
1029 EOWRITE4(sc, EHCI_USBINTR, sc->sc_eintrs);
1030
1031 hcr = 0;
1032 for (i = 1; i <= sc->sc_noport; i++) {
1033 cmd = EOREAD4(sc, EHCI_PORTSC(i));
1034 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) == EHCI_PS_SUSP)
1035 EOWRITE4(sc, EHCI_PORTSC(i),
1036 cmd | EHCI_PS_FPR);
1037 hcr = 1;
1038 }
1039
1040 if (hcr) {
1041 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1042 for (i = 1; i <= sc->sc_noport; i++) {
1043 cmd = EOREAD4(sc, EHCI_PORTSC(i));
1044 if ((cmd & (EHCI_PS_PO|EHCI_PS_SUSP)) ==
1045 EHCI_PS_SUSP)
1046 EOWRITE4(sc, EHCI_PORTSC(i),
1047 cmd & ~EHCI_PS_FPR);
1048 }
1049 }
1050
1051
1052 EOWRITE4(sc, EHCI_USBCMD, sc->sc_cmd);
1053
1054 for (i = 0; i < 100; i++) {
1055 hcr = EOREAD4(sc, EHCI_USBSTS) & EHCI_STS_HCH;
1056 if (hcr != EHCI_STS_HCH)
1057 break;
1058
1059 usb_delay_ms(&sc->sc_bus, 1);
1060 }
1061 if (hcr == EHCI_STS_HCH)
1062 printf("%s: config timeout\n",
1063 USBDEVNAME(sc->sc_bus.bdev));
1064
1065 usb_delay_ms(&sc->sc_bus, USB_RESUME_WAIT);
1066
1067 sc->sc_bus.use_polling--;
1068 break;
1069 #if defined(__NetBSD__)
1070 case PWR_SOFTSUSPEND:
1071 case PWR_SOFTSTANDBY:
1072 case PWR_SOFTRESUME:
1073 break;
1074 #endif
1075 }
1076 splx(s);
1077
1078 #ifdef EHCI_DEBUG
1079 DPRINTF(("ehci_power: sc=%p\n", sc));
1080 if (ehcidebug > 0)
1081 ehci_dump_regs(sc);
1082 #endif
1083 }
1084
1085 /*
1086 * Shut down the controller when the system is going down.
1087 */
1088 void
ehci_shutdown(void * v)1089 ehci_shutdown(void *v)
1090 {
1091 ehci_softc_t *sc = v;
1092
1093 DPRINTF(("ehci_shutdown: stopping the HC\n"));
1094 EOWRITE4(sc, EHCI_USBCMD, 0); /* Halt controller */
1095 EOWRITE4(sc, EHCI_USBCMD, EHCI_CMD_HCRESET);
1096 }
1097
1098 usbd_status
ehci_allocm(struct usbd_bus * bus,usb_dma_t * dma,u_int32_t size)1099 ehci_allocm(struct usbd_bus *bus, usb_dma_t *dma, u_int32_t size)
1100 {
1101 struct ehci_softc *sc = (struct ehci_softc *)bus;
1102 usbd_status err;
1103
1104 err = usb_allocmem(&sc->sc_bus, size, 0, dma);
1105 #ifdef EHCI_DEBUG
1106 if (err)
1107 printf("ehci_allocm: usb_allocmem()=%d\n", err);
1108 #endif
1109 return (err);
1110 }
1111
1112 void
ehci_freem(struct usbd_bus * bus,usb_dma_t * dma)1113 ehci_freem(struct usbd_bus *bus, usb_dma_t *dma)
1114 {
1115 struct ehci_softc *sc = (struct ehci_softc *)bus;
1116
1117 usb_freemem(&sc->sc_bus, dma);
1118 }
1119
1120 usbd_xfer_handle
ehci_allocx(struct usbd_bus * bus)1121 ehci_allocx(struct usbd_bus *bus)
1122 {
1123 struct ehci_softc *sc = (struct ehci_softc *)bus;
1124 usbd_xfer_handle xfer;
1125
1126 xfer = SIMPLEQ_FIRST(&sc->sc_free_xfers);
1127 if (xfer != NULL) {
1128 SIMPLEQ_REMOVE_HEAD(&sc->sc_free_xfers, next);
1129 #ifdef DIAGNOSTIC
1130 if (xfer->busy_free != XFER_FREE)
1131 printf("ehci_allocx: xfer=%p not free, 0x%08x\n",
1132 xfer, xfer->busy_free);
1133 #endif
1134 } else
1135 xfer = malloc(sizeof(struct ehci_xfer), M_USB, M_NOWAIT);
1136
1137 if (xfer != NULL) {
1138 memset(xfer, 0, sizeof(struct ehci_xfer));
1139 #ifdef DIAGNOSTIC
1140 EXFER(xfer)->isdone = 1;
1141 xfer->busy_free = XFER_BUSY;
1142 #endif
1143 }
1144 return (xfer);
1145 }
1146
1147 void
ehci_freex(struct usbd_bus * bus,usbd_xfer_handle xfer)1148 ehci_freex(struct usbd_bus *bus, usbd_xfer_handle xfer)
1149 {
1150 struct ehci_softc *sc = (struct ehci_softc *)bus;
1151
1152 #ifdef DIAGNOSTIC
1153 if (xfer->busy_free != XFER_BUSY) {
1154 printf("ehci_freex: xfer=%p not busy, 0x%08x\n", xfer,
1155 xfer->busy_free);
1156 return;
1157 }
1158 xfer->busy_free = XFER_FREE;
1159 if (!EXFER(xfer)->isdone) {
1160 printf("ehci_freex: !isdone\n");
1161 return;
1162 }
1163 #endif
1164 SIMPLEQ_INSERT_HEAD(&sc->sc_free_xfers, xfer, next);
1165 }
1166
1167 Static void
ehci_device_clear_toggle(usbd_pipe_handle pipe)1168 ehci_device_clear_toggle(usbd_pipe_handle pipe)
1169 {
1170 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1171
1172 DPRINTF(("ehci_device_clear_toggle: epipe=%p status=0x%x\n",
1173 epipe, epipe->sqh->qh.qh_qtd.qtd_status));
1174 #ifdef USB_DEBUG
1175 if (ehcidebug)
1176 usbd_dump_pipe(pipe);
1177 #endif
1178 epipe->nexttoggle = 0;
1179 }
1180
1181 Static void
ehci_noop(usbd_pipe_handle pipe)1182 ehci_noop(usbd_pipe_handle pipe)
1183 {
1184 }
1185
1186 #ifdef EHCI_DEBUG
1187 void
ehci_dump_regs(ehci_softc_t * sc)1188 ehci_dump_regs(ehci_softc_t *sc)
1189 {
1190 int i;
1191
1192 printf("cmd=0x%08x, sts=0x%08x, ien=0x%08x\n",
1193 EOREAD4(sc, EHCI_USBCMD),
1194 EOREAD4(sc, EHCI_USBSTS),
1195 EOREAD4(sc, EHCI_USBINTR));
1196 printf("frindex=0x%08x ctrdsegm=0x%08x periodic=0x%08x async=0x%08x\n",
1197 EOREAD4(sc, EHCI_FRINDEX),
1198 EOREAD4(sc, EHCI_CTRLDSSEGMENT),
1199 EOREAD4(sc, EHCI_PERIODICLISTBASE),
1200 EOREAD4(sc, EHCI_ASYNCLISTADDR));
1201 for (i = 1; i <= sc->sc_noport; i++)
1202 printf("port %d status=0x%08x\n", i,
1203 EOREAD4(sc, EHCI_PORTSC(i)));
1204 }
1205
1206 /*
1207 * Unused function - this is meant to be called from a kernel
1208 * debugger.
1209 */
1210 void
ehci_dump()1211 ehci_dump()
1212 {
1213 ehci_dump_regs(theehci);
1214 }
1215
1216 void
ehci_dump_link(ehci_link_t link,int type)1217 ehci_dump_link(ehci_link_t link, int type)
1218 {
1219 link = le32toh(link);
1220 printf("0x%08x", link);
1221 if (link & EHCI_LINK_TERMINATE)
1222 printf("<T>");
1223 else {
1224 printf("<");
1225 if (type) {
1226 switch (EHCI_LINK_TYPE(link)) {
1227 case EHCI_LINK_ITD: printf("ITD"); break;
1228 case EHCI_LINK_QH: printf("QH"); break;
1229 case EHCI_LINK_SITD: printf("SITD"); break;
1230 case EHCI_LINK_FSTN: printf("FSTN"); break;
1231 }
1232 }
1233 printf(">");
1234 }
1235 }
1236
1237 void
ehci_dump_sqtds(ehci_soft_qtd_t * sqtd)1238 ehci_dump_sqtds(ehci_soft_qtd_t *sqtd)
1239 {
1240 int i;
1241 u_int32_t stop;
1242
1243 stop = 0;
1244 for (i = 0; sqtd && i < 20 && !stop; sqtd = sqtd->nextqtd, i++) {
1245 ehci_dump_sqtd(sqtd);
1246 stop = sqtd->qtd.qtd_next & htole32(EHCI_LINK_TERMINATE);
1247 }
1248 if (!stop)
1249 printf("dump aborted, too many TDs\n");
1250 }
1251
1252 void
ehci_dump_sqtd(ehci_soft_qtd_t * sqtd)1253 ehci_dump_sqtd(ehci_soft_qtd_t *sqtd)
1254 {
1255 printf("QTD(%p) at 0x%08x:\n", sqtd, sqtd->physaddr);
1256 ehci_dump_qtd(&sqtd->qtd);
1257 }
1258
1259 void
ehci_dump_qtd(ehci_qtd_t * qtd)1260 ehci_dump_qtd(ehci_qtd_t *qtd)
1261 {
1262 u_int32_t s;
1263 char sbuf[128];
1264
1265 printf(" next="); ehci_dump_link(qtd->qtd_next, 0);
1266 printf(" altnext="); ehci_dump_link(qtd->qtd_altnext, 0);
1267 printf("\n");
1268 s = le32toh(qtd->qtd_status);
1269 bitmask_snprintf(EHCI_QTD_GET_STATUS(s), "\20\10ACTIVE\7HALTED"
1270 "\6BUFERR\5BABBLE\4XACTERR\3MISSED\2SPLIT\1PING",
1271 sbuf, sizeof(sbuf));
1272 printf(" status=0x%08x: toggle=%d bytes=0x%x ioc=%d c_page=0x%x\n",
1273 s, EHCI_QTD_GET_TOGGLE(s), EHCI_QTD_GET_BYTES(s),
1274 EHCI_QTD_GET_IOC(s), EHCI_QTD_GET_C_PAGE(s));
1275 printf(" cerr=%d pid=%d stat=0x%s\n", EHCI_QTD_GET_CERR(s),
1276 EHCI_QTD_GET_PID(s), sbuf);
1277 for (s = 0; s < 5; s++)
1278 printf(" buffer[%d]=0x%08x\n", s, le32toh(qtd->qtd_buffer[s]));
1279 }
1280
1281 void
ehci_dump_sqh(ehci_soft_qh_t * sqh)1282 ehci_dump_sqh(ehci_soft_qh_t *sqh)
1283 {
1284 ehci_qh_t *qh = &sqh->qh;
1285 u_int32_t endp, endphub;
1286
1287 printf("QH(%p) at 0x%08x:\n", sqh, sqh->physaddr);
1288 printf(" link="); ehci_dump_link(qh->qh_link, 1); printf("\n");
1289 endp = le32toh(qh->qh_endp);
1290 printf(" endp=0x%08x\n", endp);
1291 printf(" addr=0x%02x inact=%d endpt=%d eps=%d dtc=%d hrecl=%d\n",
1292 EHCI_QH_GET_ADDR(endp), EHCI_QH_GET_INACT(endp),
1293 EHCI_QH_GET_ENDPT(endp), EHCI_QH_GET_EPS(endp),
1294 EHCI_QH_GET_DTC(endp), EHCI_QH_GET_HRECL(endp));
1295 printf(" mpl=0x%x ctl=%d nrl=%d\n",
1296 EHCI_QH_GET_MPL(endp), EHCI_QH_GET_CTL(endp),
1297 EHCI_QH_GET_NRL(endp));
1298 endphub = le32toh(qh->qh_endphub);
1299 printf(" endphub=0x%08x\n", endphub);
1300 printf(" smask=0x%02x cmask=0x%02x huba=0x%02x port=%d mult=%d\n",
1301 EHCI_QH_GET_SMASK(endphub), EHCI_QH_GET_CMASK(endphub),
1302 EHCI_QH_GET_HUBA(endphub), EHCI_QH_GET_PORT(endphub),
1303 EHCI_QH_GET_MULT(endphub));
1304 printf(" curqtd="); ehci_dump_link(qh->qh_curqtd, 0); printf("\n");
1305 printf("Overlay qTD:\n");
1306 ehci_dump_qtd(&qh->qh_qtd);
1307 }
1308
1309 #ifdef DIAGNOSTIC
1310 Static void
ehci_dump_exfer(struct ehci_xfer * ex)1311 ehci_dump_exfer(struct ehci_xfer *ex)
1312 {
1313 printf("ehci_dump_exfer: ex=%p\n", ex);
1314 }
1315 #endif
1316 #endif /* EHCI_DEBUG */
1317
1318 usbd_status
ehci_open(usbd_pipe_handle pipe)1319 ehci_open(usbd_pipe_handle pipe)
1320 {
1321 usbd_device_handle dev = pipe->device;
1322 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
1323 usb_endpoint_descriptor_t *ed = pipe->endpoint->edesc;
1324 u_int8_t addr = dev->address;
1325 u_int8_t xfertype = ed->bmAttributes & UE_XFERTYPE;
1326 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
1327 ehci_soft_qh_t *sqh;
1328 usbd_status err;
1329 int s;
1330 int ival, speed, naks;
1331 int hshubaddr, hshubport;
1332
1333 DPRINTFN(1, ("ehci_open: pipe=%p, addr=%d, endpt=%d (%d)\n",
1334 pipe, addr, ed->bEndpointAddress, sc->sc_addr));
1335
1336 if (sc->sc_dying)
1337 return (USBD_IOERROR);
1338
1339 if (dev->myhsport) {
1340 hshubaddr = dev->myhsport->parent->address;
1341 hshubport = dev->myhsport->portno;
1342 } else {
1343 hshubaddr = 0;
1344 hshubport = 0;
1345 }
1346
1347 epipe->nexttoggle = 0;
1348
1349 if (addr == sc->sc_addr) {
1350 switch (ed->bEndpointAddress) {
1351 case USB_CONTROL_ENDPOINT:
1352 pipe->methods = &ehci_root_ctrl_methods;
1353 break;
1354 case UE_DIR_IN | EHCI_INTR_ENDPT:
1355 pipe->methods = &ehci_root_intr_methods;
1356 break;
1357 default:
1358 return (USBD_INVAL);
1359 }
1360 return (USBD_NORMAL_COMPLETION);
1361 }
1362
1363 /* XXX All this stuff is only valid for async. */
1364 switch (dev->speed) {
1365 case USB_SPEED_LOW: speed = EHCI_QH_SPEED_LOW; break;
1366 case USB_SPEED_FULL: speed = EHCI_QH_SPEED_FULL; break;
1367 case USB_SPEED_HIGH: speed = EHCI_QH_SPEED_HIGH; break;
1368 default: panic("ehci_open: bad device speed %d", dev->speed);
1369 }
1370 if (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_ISOCHRONOUS) {
1371 printf("%s: *** WARNING: opening low/full speed isochronous "
1372 "device, this does not work yet.\n",
1373 USBDEVNAME(sc->sc_bus.bdev));
1374 DPRINTFN(1,("ehci_open: hshubaddr=%d hshubport=%d\n",
1375 hshubaddr, hshubport));
1376 return (USBD_INVAL);
1377 }
1378
1379 naks = 8; /* XXX */
1380 sqh = ehci_alloc_sqh(sc);
1381 if (sqh == NULL)
1382 goto bad0;
1383 /* qh_link filled when the QH is added */
1384 sqh->qh.qh_endp = htole32(
1385 EHCI_QH_SET_ADDR(addr) |
1386 EHCI_QH_SET_ENDPT(UE_GET_ADDR(ed->bEndpointAddress)) |
1387 EHCI_QH_SET_EPS(speed) |
1388 EHCI_QH_DTC |
1389 EHCI_QH_SET_MPL(UGETW(ed->wMaxPacketSize)) |
1390 (speed != EHCI_QH_SPEED_HIGH && xfertype == UE_CONTROL ?
1391 EHCI_QH_CTL : 0) |
1392 EHCI_QH_SET_NRL(naks));
1393 sqh->qh.qh_endphub = htole32(
1394 EHCI_QH_SET_MULT(1) |
1395 EHCI_QH_SET_HUBA(hshubaddr) |
1396 EHCI_QH_SET_PORT(hshubport) |
1397 EHCI_QH_SET_CMASK(0x1c) | /* XXX */
1398 EHCI_QH_SET_SMASK(xfertype == UE_INTERRUPT ? 0x01 : 0));
1399 sqh->qh.qh_curqtd = EHCI_NULL;
1400 /* Fill the overlay qTD */
1401 sqh->qh.qh_qtd.qtd_next = EHCI_NULL;
1402 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1403 sqh->qh.qh_qtd.qtd_status = htole32(0);
1404
1405 epipe->sqh = sqh;
1406
1407 switch (xfertype) {
1408 case UE_CONTROL:
1409 err = usb_allocmem(&sc->sc_bus, sizeof(usb_device_request_t),
1410 0, &epipe->u.ctl.reqdma);
1411 #ifdef EHCI_DEBUG
1412 if (err)
1413 printf("ehci_open: usb_allocmem()=%d\n", err);
1414 #endif
1415 if (err)
1416 goto bad1;
1417 pipe->methods = &ehci_device_ctrl_methods;
1418 s = splusb();
1419 ehci_add_qh(sqh, sc->sc_async_head);
1420 splx(s);
1421 break;
1422 case UE_BULK:
1423 pipe->methods = &ehci_device_bulk_methods;
1424 s = splusb();
1425 ehci_add_qh(sqh, sc->sc_async_head);
1426 splx(s);
1427 break;
1428 case UE_INTERRUPT:
1429 pipe->methods = &ehci_device_intr_methods;
1430 ival = pipe->interval;
1431 if (ival == USBD_DEFAULT_INTERVAL)
1432 ival = ed->bInterval;
1433 return (ehci_device_setintr(sc, sqh, ival));
1434 case UE_ISOCHRONOUS:
1435 pipe->methods = &ehci_device_isoc_methods;
1436 return (USBD_INVAL);
1437 default:
1438 return (USBD_INVAL);
1439 }
1440 return (USBD_NORMAL_COMPLETION);
1441
1442 bad1:
1443 ehci_free_sqh(sc, sqh);
1444 bad0:
1445 return (USBD_NOMEM);
1446 }
1447
1448 /*
1449 * Add an ED to the schedule. Called at splusb().
1450 */
1451 void
ehci_add_qh(ehci_soft_qh_t * sqh,ehci_soft_qh_t * head)1452 ehci_add_qh(ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1453 {
1454 SPLUSBCHECK;
1455
1456 sqh->next = head->next;
1457 sqh->qh.qh_link = head->qh.qh_link;
1458 head->next = sqh;
1459 head->qh.qh_link = htole32(sqh->physaddr | EHCI_LINK_QH);
1460
1461 #ifdef EHCI_DEBUG
1462 if (ehcidebug > 5) {
1463 printf("ehci_add_qh:\n");
1464 ehci_dump_sqh(sqh);
1465 }
1466 #endif
1467 }
1468
1469 /*
1470 * Remove an ED from the schedule. Called at splusb().
1471 */
1472 void
ehci_rem_qh(ehci_softc_t * sc,ehci_soft_qh_t * sqh,ehci_soft_qh_t * head)1473 ehci_rem_qh(ehci_softc_t *sc, ehci_soft_qh_t *sqh, ehci_soft_qh_t *head)
1474 {
1475 ehci_soft_qh_t *p;
1476
1477 SPLUSBCHECK;
1478 /* XXX */
1479 for (p = head; p != NULL && p->next != sqh; p = p->next)
1480 ;
1481 if (p == NULL)
1482 panic("ehci_rem_qh: ED not found");
1483 p->next = sqh->next;
1484 p->qh.qh_link = sqh->qh.qh_link;
1485
1486 ehci_sync_hc(sc);
1487 }
1488
1489 void
ehci_set_qh_qtd(ehci_soft_qh_t * sqh,ehci_soft_qtd_t * sqtd)1490 ehci_set_qh_qtd(ehci_soft_qh_t *sqh, ehci_soft_qtd_t *sqtd)
1491 {
1492 int i;
1493 u_int32_t status;
1494
1495 /* Save toggle bit and ping status. */
1496 status = sqh->qh.qh_qtd.qtd_status &
1497 htole32(EHCI_QTD_TOGGLE_MASK |
1498 EHCI_QTD_SET_STATUS(EHCI_QTD_PINGSTATE));
1499 /* Set HALTED to make hw leave it alone. */
1500 sqh->qh.qh_qtd.qtd_status =
1501 htole32(EHCI_QTD_SET_STATUS(EHCI_QTD_HALTED));
1502 sqh->qh.qh_curqtd = 0;
1503 sqh->qh.qh_qtd.qtd_next = htole32(sqtd->physaddr);
1504 sqh->qh.qh_qtd.qtd_altnext = EHCI_NULL;
1505 for (i = 0; i < EHCI_QTD_NBUFFERS; i++)
1506 sqh->qh.qh_qtd.qtd_buffer[i] = 0;
1507 sqh->sqtd = sqtd;
1508 /* Set !HALTED && !ACTIVE to start execution, preserve some fields */
1509 sqh->qh.qh_qtd.qtd_status = status;
1510 }
1511
1512 /*
1513 * Ensure that the HC has released all references to the QH. We do this
1514 * by asking for a Async Advance Doorbell interrupt and then we wait for
1515 * the interrupt.
1516 * To make this easier we first obtain exclusive use of the doorbell.
1517 */
1518 void
ehci_sync_hc(ehci_softc_t * sc)1519 ehci_sync_hc(ehci_softc_t *sc)
1520 {
1521 int s, error;
1522
1523 if (sc->sc_dying) {
1524 DPRINTFN(2,("ehci_sync_hc: dying\n"));
1525 return;
1526 }
1527 DPRINTFN(2,("ehci_sync_hc: enter\n"));
1528 /* get doorbell */
1529 usb_lockmgr(&sc->sc_doorbell_lock, LK_EXCLUSIVE, NULL, curproc);
1530 s = splhardusb();
1531 /* ask for doorbell */
1532 EOWRITE4(sc, EHCI_USBCMD, EOREAD4(sc, EHCI_USBCMD) | EHCI_CMD_IAAD);
1533 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1534 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1535 error = tsleep(&sc->sc_async_head, PZERO, "ehcidi", hz); /* bell wait */
1536 DPRINTFN(1,("ehci_sync_hc: cmd=0x%08x sts=0x%08x\n",
1537 EOREAD4(sc, EHCI_USBCMD), EOREAD4(sc, EHCI_USBSTS)));
1538 splx(s);
1539 /* release doorbell */
1540 usb_lockmgr(&sc->sc_doorbell_lock, LK_RELEASE, NULL, curproc);
1541 #ifdef DIAGNOSTIC
1542 if (error)
1543 printf("ehci_sync_hc: tsleep() = %d\n", error);
1544 #endif
1545 DPRINTFN(2,("ehci_sync_hc: exit\n"));
1546 }
1547
1548 /***********/
1549
1550 /*
1551 * Data structures and routines to emulate the root hub.
1552 */
1553 Static usb_device_descriptor_t ehci_devd = {
1554 USB_DEVICE_DESCRIPTOR_SIZE,
1555 UDESC_DEVICE, /* type */
1556 {0x00, 0x02}, /* USB version */
1557 UDCLASS_HUB, /* class */
1558 UDSUBCLASS_HUB, /* subclass */
1559 UDPROTO_HSHUBSTT, /* protocol */
1560 64, /* max packet */
1561 {0},{0},{0x00,0x01}, /* device id */
1562 1,2,0, /* string indicies */
1563 1 /* # of configurations */
1564 };
1565
1566 Static usb_device_qualifier_t ehci_odevd = {
1567 USB_DEVICE_DESCRIPTOR_SIZE,
1568 UDESC_DEVICE_QUALIFIER, /* type */
1569 {0x00, 0x02}, /* USB version */
1570 UDCLASS_HUB, /* class */
1571 UDSUBCLASS_HUB, /* subclass */
1572 UDPROTO_FSHUB, /* protocol */
1573 64, /* max packet */
1574 1, /* # of configurations */
1575 0
1576 };
1577
1578 Static usb_config_descriptor_t ehci_confd = {
1579 USB_CONFIG_DESCRIPTOR_SIZE,
1580 UDESC_CONFIG,
1581 {USB_CONFIG_DESCRIPTOR_SIZE +
1582 USB_INTERFACE_DESCRIPTOR_SIZE +
1583 USB_ENDPOINT_DESCRIPTOR_SIZE},
1584 1,
1585 1,
1586 0,
1587 UC_SELF_POWERED,
1588 0 /* max power */
1589 };
1590
1591 Static usb_interface_descriptor_t ehci_ifcd = {
1592 USB_INTERFACE_DESCRIPTOR_SIZE,
1593 UDESC_INTERFACE,
1594 0,
1595 0,
1596 1,
1597 UICLASS_HUB,
1598 UISUBCLASS_HUB,
1599 UIPROTO_HSHUBSTT,
1600 0
1601 };
1602
1603 Static usb_endpoint_descriptor_t ehci_endpd = {
1604 USB_ENDPOINT_DESCRIPTOR_SIZE,
1605 UDESC_ENDPOINT,
1606 UE_DIR_IN | EHCI_INTR_ENDPT,
1607 UE_INTERRUPT,
1608 {8, 0}, /* max packet */
1609 255
1610 };
1611
1612 Static usb_hub_descriptor_t ehci_hubd = {
1613 USB_HUB_DESCRIPTOR_SIZE,
1614 UDESC_HUB,
1615 0,
1616 {0,0},
1617 0,
1618 0,
1619 {0},
1620 };
1621
1622 Static int
ehci_str(usb_string_descriptor_t * p,int l,char * s)1623 ehci_str(usb_string_descriptor_t *p, int l, char *s)
1624 {
1625 int i;
1626
1627 if (l == 0)
1628 return (0);
1629 p->bLength = 2 * strlen(s) + 2;
1630 if (l == 1)
1631 return (1);
1632 p->bDescriptorType = UDESC_STRING;
1633 l -= 2;
1634 for (i = 0; s[i] && l > 1; i++, l -= 2)
1635 USETW2(p->bString[i], 0, s[i]);
1636 return (2*i+2);
1637 }
1638
1639 /*
1640 * Simulate a hardware hub by handling all the necessary requests.
1641 */
1642 Static usbd_status
ehci_root_ctrl_transfer(usbd_xfer_handle xfer)1643 ehci_root_ctrl_transfer(usbd_xfer_handle xfer)
1644 {
1645 usbd_status err;
1646
1647 /* Insert last in queue. */
1648 err = usb_insert_transfer(xfer);
1649 if (err)
1650 return (err);
1651
1652 /* Pipe isn't running, start first */
1653 return (ehci_root_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
1654 }
1655
1656 Static usbd_status
ehci_root_ctrl_start(usbd_xfer_handle xfer)1657 ehci_root_ctrl_start(usbd_xfer_handle xfer)
1658 {
1659 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
1660 usb_device_request_t *req;
1661 void *buf = NULL;
1662 int port, i;
1663 int s, len, value, index, l, totlen = 0;
1664 usb_port_status_t ps;
1665 usb_hub_descriptor_t hubd;
1666 usbd_status err;
1667 u_int32_t v;
1668
1669 if (sc->sc_dying)
1670 return (USBD_IOERROR);
1671
1672 #ifdef DIAGNOSTIC
1673 if (!(xfer->rqflags & URQ_REQUEST))
1674 /* XXX panic */
1675 return (USBD_INVAL);
1676 #endif
1677 req = &xfer->request;
1678
1679 DPRINTFN(4,("ehci_root_ctrl_start: type=0x%02x request=%02x\n",
1680 req->bmRequestType, req->bRequest));
1681
1682 len = UGETW(req->wLength);
1683 value = UGETW(req->wValue);
1684 index = UGETW(req->wIndex);
1685
1686 if (len != 0)
1687 buf = KERNADDR(&xfer->dmabuf, 0);
1688
1689 #define C(x,y) ((x) | ((y) << 8))
1690 switch(C(req->bRequest, req->bmRequestType)) {
1691 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
1692 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
1693 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
1694 /*
1695 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
1696 * for the integrated root hub.
1697 */
1698 break;
1699 case C(UR_GET_CONFIG, UT_READ_DEVICE):
1700 if (len > 0) {
1701 *(u_int8_t *)buf = sc->sc_conf;
1702 totlen = 1;
1703 }
1704 break;
1705 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
1706 DPRINTFN(8,("ehci_root_ctrl_start: wValue=0x%04x\n", value));
1707 switch(value >> 8) {
1708 case UDESC_DEVICE:
1709 if ((value & 0xff) != 0) {
1710 err = USBD_IOERROR;
1711 goto ret;
1712 }
1713 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1714 USETW(ehci_devd.idVendor, sc->sc_id_vendor);
1715 memcpy(buf, &ehci_devd, l);
1716 break;
1717 /*
1718 * We can't really operate at another speed, but the spec says
1719 * we need this descriptor.
1720 */
1721 case UDESC_DEVICE_QUALIFIER:
1722 if ((value & 0xff) != 0) {
1723 err = USBD_IOERROR;
1724 goto ret;
1725 }
1726 totlen = l = min(len, USB_DEVICE_DESCRIPTOR_SIZE);
1727 memcpy(buf, &ehci_odevd, l);
1728 break;
1729 /*
1730 * We can't really operate at another speed, but the spec says
1731 * we need this descriptor.
1732 */
1733 case UDESC_OTHER_SPEED_CONFIGURATION:
1734 case UDESC_CONFIG:
1735 if ((value & 0xff) != 0) {
1736 err = USBD_IOERROR;
1737 goto ret;
1738 }
1739 totlen = l = min(len, USB_CONFIG_DESCRIPTOR_SIZE);
1740 memcpy(buf, &ehci_confd, l);
1741 ((usb_config_descriptor_t *)buf)->bDescriptorType =
1742 value >> 8;
1743 buf = (char *)buf + l;
1744 len -= l;
1745 l = min(len, USB_INTERFACE_DESCRIPTOR_SIZE);
1746 totlen += l;
1747 memcpy(buf, &ehci_ifcd, l);
1748 buf = (char *)buf + l;
1749 len -= l;
1750 l = min(len, USB_ENDPOINT_DESCRIPTOR_SIZE);
1751 totlen += l;
1752 memcpy(buf, &ehci_endpd, l);
1753 break;
1754 case UDESC_STRING:
1755 if (len == 0)
1756 break;
1757 *(u_int8_t *)buf = 0;
1758 totlen = 1;
1759 switch (value & 0xff) {
1760 case 1: /* Vendor */
1761 totlen = ehci_str(buf, len, sc->sc_vendor);
1762 break;
1763 case 2: /* Product */
1764 totlen = ehci_str(buf, len, "EHCI root hub");
1765 break;
1766 }
1767 break;
1768 default:
1769 err = USBD_IOERROR;
1770 goto ret;
1771 }
1772 break;
1773 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
1774 if (len > 0) {
1775 *(u_int8_t *)buf = 0;
1776 totlen = 1;
1777 }
1778 break;
1779 case C(UR_GET_STATUS, UT_READ_DEVICE):
1780 if (len > 1) {
1781 USETW(((usb_status_t *)buf)->wStatus,UDS_SELF_POWERED);
1782 totlen = 2;
1783 }
1784 break;
1785 case C(UR_GET_STATUS, UT_READ_INTERFACE):
1786 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
1787 if (len > 1) {
1788 USETW(((usb_status_t *)buf)->wStatus, 0);
1789 totlen = 2;
1790 }
1791 break;
1792 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
1793 if (value >= USB_MAX_DEVICES) {
1794 err = USBD_IOERROR;
1795 goto ret;
1796 }
1797 sc->sc_addr = value;
1798 break;
1799 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
1800 if (value != 0 && value != 1) {
1801 err = USBD_IOERROR;
1802 goto ret;
1803 }
1804 sc->sc_conf = value;
1805 break;
1806 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
1807 break;
1808 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
1809 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
1810 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
1811 err = USBD_IOERROR;
1812 goto ret;
1813 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
1814 break;
1815 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
1816 break;
1817 /* Hub requests */
1818 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
1819 break;
1820 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
1821 DPRINTFN(8, ("ehci_root_ctrl_start: UR_CLEAR_PORT_FEATURE "
1822 "port=%d feature=%d\n", index, value));
1823 if (index < 1 || index > sc->sc_noport) {
1824 err = USBD_IOERROR;
1825 goto ret;
1826 }
1827 port = EHCI_PORTSC(index);
1828 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1829 switch(value) {
1830 case UHF_PORT_ENABLE:
1831 EOWRITE4(sc, port, v &~ EHCI_PS_PE);
1832 break;
1833 case UHF_PORT_SUSPEND:
1834 EOWRITE4(sc, port, v &~ EHCI_PS_SUSP);
1835 break;
1836 case UHF_PORT_POWER:
1837 EOWRITE4(sc, port, v &~ EHCI_PS_PP);
1838 break;
1839 case UHF_PORT_TEST:
1840 DPRINTFN(2,("ehci_root_ctrl_start: "
1841 "clear port test %d\n", index));
1842 break;
1843 case UHF_PORT_INDICATOR:
1844 DPRINTFN(2,("ehci_root_ctrl_start: "
1845 "clear port index %d\n", index));
1846 EOWRITE4(sc, port, v &~ EHCI_PS_PIC);
1847 break;
1848 case UHF_C_PORT_CONNECTION:
1849 EOWRITE4(sc, port, v | EHCI_PS_CSC);
1850 break;
1851 case UHF_C_PORT_ENABLE:
1852 EOWRITE4(sc, port, v | EHCI_PS_PEC);
1853 break;
1854 case UHF_C_PORT_SUSPEND:
1855 /* how? */
1856 break;
1857 case UHF_C_PORT_OVER_CURRENT:
1858 EOWRITE4(sc, port, v | EHCI_PS_OCC);
1859 break;
1860 case UHF_C_PORT_RESET:
1861 sc->sc_isreset = 0;
1862 break;
1863 default:
1864 err = USBD_IOERROR;
1865 goto ret;
1866 }
1867 #if 0
1868 switch(value) {
1869 case UHF_C_PORT_CONNECTION:
1870 case UHF_C_PORT_ENABLE:
1871 case UHF_C_PORT_SUSPEND:
1872 case UHF_C_PORT_OVER_CURRENT:
1873 case UHF_C_PORT_RESET:
1874 /* Enable RHSC interrupt if condition is cleared. */
1875 if ((OREAD4(sc, port) >> 16) == 0)
1876 ehci_pcd_able(sc, 1);
1877 break;
1878 default:
1879 break;
1880 }
1881 #endif
1882 break;
1883 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
1884 if ((value & 0xff) != 0) {
1885 err = USBD_IOERROR;
1886 goto ret;
1887 }
1888 hubd = ehci_hubd;
1889 hubd.bNbrPorts = sc->sc_noport;
1890 v = EOREAD4(sc, EHCI_HCSPARAMS);
1891 USETW(hubd.wHubCharacteristics,
1892 EHCI_HCS_PPC(v) ? UHD_PWR_INDIVIDUAL : UHD_PWR_NO_SWITCH |
1893 EHCI_HCS_P_INDICATOR(EREAD4(sc, EHCI_HCSPARAMS))
1894 ? UHD_PORT_IND : 0);
1895 hubd.bPwrOn2PwrGood = 200; /* XXX can't find out? */
1896 for (i = 0, l = sc->sc_noport; l > 0; i++, l -= 8, v >>= 8)
1897 hubd.DeviceRemovable[i++] = 0; /* XXX can't find out? */
1898 hubd.bDescLength = USB_HUB_DESCRIPTOR_SIZE + i;
1899 l = min(len, hubd.bDescLength);
1900 totlen = l;
1901 memcpy(buf, &hubd, l);
1902 break;
1903 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
1904 if (len != 4) {
1905 err = USBD_IOERROR;
1906 goto ret;
1907 }
1908 memset(buf, 0, len); /* ? XXX */
1909 totlen = len;
1910 break;
1911 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
1912 DPRINTFN(8,("ehci_root_ctrl_start: get port status i=%d\n",
1913 index));
1914 if (index < 1 || index > sc->sc_noport) {
1915 err = USBD_IOERROR;
1916 goto ret;
1917 }
1918 if (len != 4) {
1919 err = USBD_IOERROR;
1920 goto ret;
1921 }
1922 v = EOREAD4(sc, EHCI_PORTSC(index));
1923 DPRINTFN(8,("ehci_root_ctrl_start: port status=0x%04x\n", v));
1924 i = UPS_HIGH_SPEED;
1925 if (v & EHCI_PS_CS) i |= UPS_CURRENT_CONNECT_STATUS;
1926 if (v & EHCI_PS_PE) i |= UPS_PORT_ENABLED;
1927 if (v & EHCI_PS_SUSP) i |= UPS_SUSPEND;
1928 if (v & EHCI_PS_OCA) i |= UPS_OVERCURRENT_INDICATOR;
1929 if (v & EHCI_PS_PR) i |= UPS_RESET;
1930 if (v & EHCI_PS_PP) i |= UPS_PORT_POWER;
1931 USETW(ps.wPortStatus, i);
1932 i = 0;
1933 if (v & EHCI_PS_CSC) i |= UPS_C_CONNECT_STATUS;
1934 if (v & EHCI_PS_PEC) i |= UPS_C_PORT_ENABLED;
1935 if (v & EHCI_PS_OCC) i |= UPS_C_OVERCURRENT_INDICATOR;
1936 if (sc->sc_isreset) i |= UPS_C_PORT_RESET;
1937 USETW(ps.wPortChange, i);
1938 l = min(len, sizeof(ps));
1939 memcpy(buf, &ps, l);
1940 totlen = l;
1941 break;
1942 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
1943 err = USBD_IOERROR;
1944 goto ret;
1945 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
1946 break;
1947 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
1948 if (index < 1 || index > sc->sc_noport) {
1949 err = USBD_IOERROR;
1950 goto ret;
1951 }
1952 port = EHCI_PORTSC(index);
1953 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
1954 switch(value) {
1955 case UHF_PORT_ENABLE:
1956 EOWRITE4(sc, port, v | EHCI_PS_PE);
1957 break;
1958 case UHF_PORT_SUSPEND:
1959 EOWRITE4(sc, port, v | EHCI_PS_SUSP);
1960 break;
1961 case UHF_PORT_RESET:
1962 DPRINTFN(5,("ehci_root_ctrl_start: reset port %d\n",
1963 index));
1964 if (EHCI_PS_IS_LOWSPEED(v)) {
1965 /* Low speed device, give up ownership. */
1966 ehci_disown(sc, index, 1);
1967 break;
1968 }
1969 /* Start reset sequence. */
1970 v &= ~ (EHCI_PS_PE | EHCI_PS_PR);
1971 EOWRITE4(sc, port, v | EHCI_PS_PR);
1972 /* Wait for reset to complete. */
1973 usb_delay_ms(&sc->sc_bus, USB_PORT_ROOT_RESET_DELAY);
1974 if (sc->sc_dying) {
1975 err = USBD_IOERROR;
1976 goto ret;
1977 }
1978 /* Terminate reset sequence. */
1979 EOWRITE4(sc, port, v);
1980 /* Wait for HC to complete reset. */
1981 usb_delay_ms(&sc->sc_bus, EHCI_PORT_RESET_COMPLETE);
1982 if (sc->sc_dying) {
1983 err = USBD_IOERROR;
1984 goto ret;
1985 }
1986 v = EOREAD4(sc, port);
1987 DPRINTF(("ehci after reset, status=0x%08x\n", v));
1988 if (v & EHCI_PS_PR) {
1989 printf("%s: port reset timeout\n",
1990 USBDEVNAME(sc->sc_bus.bdev));
1991 return (USBD_TIMEOUT);
1992 }
1993 if (!(v & EHCI_PS_PE)) {
1994 /* Not a high speed device, give up ownership.*/
1995 ehci_disown(sc, index, 0);
1996 break;
1997 }
1998 sc->sc_isreset = 1;
1999 DPRINTF(("ehci port %d reset, status = 0x%08x\n",
2000 index, v));
2001 break;
2002 case UHF_PORT_POWER:
2003 DPRINTFN(2,("ehci_root_ctrl_start: "
2004 "set port power %d\n", index));
2005 EOWRITE4(sc, port, v | EHCI_PS_PP);
2006 break;
2007 case UHF_PORT_TEST:
2008 DPRINTFN(2,("ehci_root_ctrl_start: "
2009 "set port test %d\n", index));
2010 break;
2011 case UHF_PORT_INDICATOR:
2012 DPRINTFN(2,("ehci_root_ctrl_start: "
2013 "set port ind %d\n", index));
2014 EOWRITE4(sc, port, v | EHCI_PS_PIC);
2015 break;
2016 default:
2017 err = USBD_IOERROR;
2018 goto ret;
2019 }
2020 break;
2021 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
2022 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
2023 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
2024 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
2025 break;
2026 default:
2027 err = USBD_IOERROR;
2028 goto ret;
2029 }
2030 xfer->actlen = totlen;
2031 err = USBD_NORMAL_COMPLETION;
2032 ret:
2033 xfer->status = err;
2034 s = splusb();
2035 usb_transfer_complete(xfer);
2036 splx(s);
2037 return (USBD_IN_PROGRESS);
2038 }
2039
2040 void
ehci_disown(ehci_softc_t * sc,int index,int lowspeed)2041 ehci_disown(ehci_softc_t *sc, int index, int lowspeed)
2042 {
2043 int port;
2044 u_int32_t v;
2045
2046 DPRINTF(("ehci_disown: index=%d lowspeed=%d\n", index, lowspeed));
2047
2048 port = EHCI_PORTSC(index);
2049 v = EOREAD4(sc, port) &~ EHCI_PS_CLEAR;
2050 EOWRITE4(sc, port, v | EHCI_PS_PO);
2051 }
2052
2053 /* Abort a root control request. */
2054 Static void
ehci_root_ctrl_abort(usbd_xfer_handle xfer)2055 ehci_root_ctrl_abort(usbd_xfer_handle xfer)
2056 {
2057 /* Nothing to do, all transfers are synchronous. */
2058 }
2059
2060 /* Close the root pipe. */
2061 Static void
ehci_root_ctrl_close(usbd_pipe_handle pipe)2062 ehci_root_ctrl_close(usbd_pipe_handle pipe)
2063 {
2064 DPRINTF(("ehci_root_ctrl_close\n"));
2065 /* Nothing to do. */
2066 }
2067
2068 void
ehci_root_intr_done(usbd_xfer_handle xfer)2069 ehci_root_intr_done(usbd_xfer_handle xfer)
2070 {
2071 }
2072
2073 Static usbd_status
ehci_root_intr_transfer(usbd_xfer_handle xfer)2074 ehci_root_intr_transfer(usbd_xfer_handle xfer)
2075 {
2076 usbd_status err;
2077
2078 /* Insert last in queue. */
2079 err = usb_insert_transfer(xfer);
2080 if (err)
2081 return (err);
2082
2083 /* Pipe isn't running, start first */
2084 return (ehci_root_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2085 }
2086
2087 Static usbd_status
ehci_root_intr_start(usbd_xfer_handle xfer)2088 ehci_root_intr_start(usbd_xfer_handle xfer)
2089 {
2090 usbd_pipe_handle pipe = xfer->pipe;
2091 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2092
2093 if (sc->sc_dying)
2094 return (USBD_IOERROR);
2095
2096 sc->sc_intrxfer = xfer;
2097
2098 return (USBD_IN_PROGRESS);
2099 }
2100
2101 /* Abort a root interrupt request. */
2102 Static void
ehci_root_intr_abort(usbd_xfer_handle xfer)2103 ehci_root_intr_abort(usbd_xfer_handle xfer)
2104 {
2105 int s;
2106
2107 if (xfer->pipe->intrxfer == xfer) {
2108 DPRINTF(("ehci_root_intr_abort: remove\n"));
2109 xfer->pipe->intrxfer = NULL;
2110 }
2111 xfer->status = USBD_CANCELLED;
2112 s = splusb();
2113 usb_transfer_complete(xfer);
2114 splx(s);
2115 }
2116
2117 /* Close the root pipe. */
2118 Static void
ehci_root_intr_close(usbd_pipe_handle pipe)2119 ehci_root_intr_close(usbd_pipe_handle pipe)
2120 {
2121 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2122
2123 DPRINTF(("ehci_root_intr_close\n"));
2124
2125 sc->sc_intrxfer = NULL;
2126 }
2127
2128 void
ehci_root_ctrl_done(usbd_xfer_handle xfer)2129 ehci_root_ctrl_done(usbd_xfer_handle xfer)
2130 {
2131 }
2132
2133 /************************/
2134
2135 ehci_soft_qh_t *
ehci_alloc_sqh(ehci_softc_t * sc)2136 ehci_alloc_sqh(ehci_softc_t *sc)
2137 {
2138 ehci_soft_qh_t *sqh;
2139 usbd_status err;
2140 int i, offs;
2141 usb_dma_t dma;
2142
2143 if (sc->sc_freeqhs == NULL) {
2144 DPRINTFN(2, ("ehci_alloc_sqh: allocating chunk\n"));
2145 err = usb_allocmem(&sc->sc_bus, EHCI_SQH_SIZE * EHCI_SQH_CHUNK,
2146 EHCI_PAGE_SIZE, &dma);
2147 #ifdef EHCI_DEBUG
2148 if (err)
2149 printf("ehci_alloc_sqh: usb_allocmem()=%d\n", err);
2150 #endif
2151 if (err)
2152 return (NULL);
2153 for(i = 0; i < EHCI_SQH_CHUNK; i++) {
2154 offs = i * EHCI_SQH_SIZE;
2155 sqh = KERNADDR(&dma, offs);
2156 sqh->physaddr = DMAADDR(&dma, offs);
2157 sqh->next = sc->sc_freeqhs;
2158 sc->sc_freeqhs = sqh;
2159 }
2160 }
2161 sqh = sc->sc_freeqhs;
2162 sc->sc_freeqhs = sqh->next;
2163 memset(&sqh->qh, 0, sizeof(ehci_qh_t));
2164 sqh->next = NULL;
2165 return (sqh);
2166 }
2167
2168 void
ehci_free_sqh(ehci_softc_t * sc,ehci_soft_qh_t * sqh)2169 ehci_free_sqh(ehci_softc_t *sc, ehci_soft_qh_t *sqh)
2170 {
2171 sqh->next = sc->sc_freeqhs;
2172 sc->sc_freeqhs = sqh;
2173 }
2174
2175 ehci_soft_qtd_t *
ehci_alloc_sqtd(ehci_softc_t * sc)2176 ehci_alloc_sqtd(ehci_softc_t *sc)
2177 {
2178 ehci_soft_qtd_t *sqtd;
2179 usbd_status err;
2180 int i, offs;
2181 usb_dma_t dma;
2182 int s;
2183
2184 if (sc->sc_freeqtds == NULL) {
2185 DPRINTFN(2, ("ehci_alloc_sqtd: allocating chunk\n"));
2186 err = usb_allocmem(&sc->sc_bus, EHCI_SQTD_SIZE*EHCI_SQTD_CHUNK,
2187 EHCI_PAGE_SIZE, &dma);
2188 #ifdef EHCI_DEBUG
2189 if (err)
2190 printf("ehci_alloc_sqtd: usb_allocmem()=%d\n", err);
2191 #endif
2192 if (err)
2193 return (NULL);
2194 s = splusb();
2195 for(i = 0; i < EHCI_SQTD_CHUNK; i++) {
2196 offs = i * EHCI_SQTD_SIZE;
2197 sqtd = KERNADDR(&dma, offs);
2198 sqtd->physaddr = DMAADDR(&dma, offs);
2199 sqtd->nextqtd = sc->sc_freeqtds;
2200 sc->sc_freeqtds = sqtd;
2201 }
2202 splx(s);
2203 }
2204
2205 s = splusb();
2206 sqtd = sc->sc_freeqtds;
2207 sc->sc_freeqtds = sqtd->nextqtd;
2208 memset(&sqtd->qtd, 0, sizeof(ehci_qtd_t));
2209 sqtd->nextqtd = NULL;
2210 sqtd->xfer = NULL;
2211 splx(s);
2212
2213 return (sqtd);
2214 }
2215
2216 void
ehci_free_sqtd(ehci_softc_t * sc,ehci_soft_qtd_t * sqtd)2217 ehci_free_sqtd(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd)
2218 {
2219 int s;
2220
2221 s = splusb();
2222 sqtd->nextqtd = sc->sc_freeqtds;
2223 sc->sc_freeqtds = sqtd;
2224 splx(s);
2225 }
2226
2227 usbd_status
ehci_alloc_sqtd_chain(struct ehci_pipe * epipe,ehci_softc_t * sc,int alen,int rd,usbd_xfer_handle xfer,ehci_soft_qtd_t ** sp,ehci_soft_qtd_t ** ep)2228 ehci_alloc_sqtd_chain(struct ehci_pipe *epipe, ehci_softc_t *sc, int alen,
2229 int rd, usbd_xfer_handle xfer, ehci_soft_qtd_t **sp, ehci_soft_qtd_t **ep)
2230 {
2231 ehci_soft_qtd_t *next, *cur;
2232 ehci_physaddr_t dataphys, dataphyspage, dataphyslastpage, nextphys;
2233 u_int32_t qtdstatus;
2234 int len, curlen, mps;
2235 int i, tog;
2236 usb_dma_t *dma = &xfer->dmabuf;
2237
2238 DPRINTFN(alen<4*4096,("ehci_alloc_sqtd_chain: start len=%d\n", alen));
2239
2240 len = alen;
2241 dataphys = DMAADDR(dma, 0);
2242 dataphyslastpage = EHCI_PAGE(dataphys + len - 1);
2243 qtdstatus = EHCI_QTD_ACTIVE |
2244 EHCI_QTD_SET_PID(rd ? EHCI_QTD_PID_IN : EHCI_QTD_PID_OUT) |
2245 EHCI_QTD_SET_CERR(3); /* IOC and BYTES set below */
2246 mps = UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize);
2247 tog = epipe->nexttoggle;
2248 qtdstatus |= EHCI_QTD_SET_TOGGLE(tog);
2249
2250 cur = ehci_alloc_sqtd(sc);
2251 *sp = cur;
2252 if (cur == NULL)
2253 goto nomem;
2254 for (;;) {
2255 dataphyspage = EHCI_PAGE(dataphys);
2256 /* The EHCI hardware can handle at most 5 pages. */
2257 if (dataphyslastpage - dataphyspage <
2258 EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE) {
2259 /* we can handle it in this QTD */
2260 curlen = len;
2261 } else {
2262 /* must use multiple TDs, fill as much as possible. */
2263 curlen = EHCI_QTD_NBUFFERS * EHCI_PAGE_SIZE -
2264 EHCI_PAGE_OFFSET(dataphys);
2265 #ifdef DIAGNOSTIC
2266 if (curlen > len) {
2267 printf("ehci_alloc_sqtd_chain: curlen=0x%x "
2268 "len=0x%x offs=0x%x\n", curlen, len,
2269 EHCI_PAGE_OFFSET(dataphys));
2270 printf("lastpage=0x%x page=0x%x phys=0x%x\n",
2271 dataphyslastpage, dataphyspage, dataphys);
2272 curlen = len;
2273 }
2274 #endif
2275 /* the length must be a multiple of the max size */
2276 curlen -= curlen % mps;
2277 DPRINTFN(1,("ehci_alloc_sqtd_chain: multiple QTDs, "
2278 "curlen=%d\n", curlen));
2279 #ifdef DIAGNOSTIC
2280 if (curlen == 0)
2281 panic("ehci_alloc_std: curlen == 0");
2282 #endif
2283 }
2284 DPRINTFN(4,("ehci_alloc_sqtd_chain: dataphys=0x%08x "
2285 "dataphyslastpage=0x%08x len=%d curlen=%d\n",
2286 dataphys, dataphyslastpage, len, curlen));
2287 len -= curlen;
2288
2289 if (len != 0) {
2290 next = ehci_alloc_sqtd(sc);
2291 if (next == NULL)
2292 goto nomem;
2293 nextphys = htole32(next->physaddr);
2294 } else {
2295 next = NULL;
2296 nextphys = EHCI_NULL;
2297 }
2298
2299 for (i = 0; i * EHCI_PAGE_SIZE < curlen; i++) {
2300 ehci_physaddr_t a = dataphys + i * EHCI_PAGE_SIZE;
2301 if (i != 0) /* use offset only in first buffer */
2302 a = EHCI_PAGE(a);
2303 cur->qtd.qtd_buffer[i] = htole32(a);
2304 cur->qtd.qtd_buffer_hi[i] = 0;
2305 #ifdef DIAGNOSTIC
2306 if (i >= EHCI_QTD_NBUFFERS) {
2307 printf("ehci_alloc_sqtd_chain: i=%d\n", i);
2308 goto nomem;
2309 }
2310 #endif
2311 }
2312 cur->nextqtd = next;
2313 cur->qtd.qtd_next = cur->qtd.qtd_altnext = nextphys;
2314 cur->qtd.qtd_status = htole32(qtdstatus |
2315 EHCI_QTD_SET_BYTES(curlen));
2316 cur->xfer = xfer;
2317 cur->len = curlen;
2318 DPRINTFN(10,("ehci_alloc_sqtd_chain: cbp=0x%08x end=0x%08x\n",
2319 dataphys, dataphys + curlen));
2320 /* adjust the toggle based on the number of packets in this
2321 qtd */
2322 if (((curlen + mps - 1) / mps) & 1) {
2323 tog ^= 1;
2324 qtdstatus ^= EHCI_QTD_TOGGLE_MASK;
2325 }
2326 if (len == 0)
2327 break;
2328 DPRINTFN(10,("ehci_alloc_sqtd_chain: extend chain\n"));
2329 dataphys += curlen;
2330 cur = next;
2331 }
2332 cur->qtd.qtd_status |= htole32(EHCI_QTD_IOC);
2333 *ep = cur;
2334 epipe->nexttoggle = tog;
2335
2336 DPRINTFN(10,("ehci_alloc_sqtd_chain: return sqtd=%p sqtdend=%p\n",
2337 *sp, *ep));
2338
2339 return (USBD_NORMAL_COMPLETION);
2340
2341 nomem:
2342 /* XXX free chain */
2343 DPRINTFN(-1,("ehci_alloc_sqtd_chain: no memory\n"));
2344 return (USBD_NOMEM);
2345 }
2346
2347 Static void
ehci_free_sqtd_chain(ehci_softc_t * sc,ehci_soft_qtd_t * sqtd,ehci_soft_qtd_t * sqtdend)2348 ehci_free_sqtd_chain(ehci_softc_t *sc, ehci_soft_qtd_t *sqtd,
2349 ehci_soft_qtd_t *sqtdend)
2350 {
2351 ehci_soft_qtd_t *p;
2352 int i;
2353
2354 DPRINTFN(10,("ehci_free_sqtd_chain: sqtd=%p sqtdend=%p\n",
2355 sqtd, sqtdend));
2356
2357 for (i = 0; sqtd != sqtdend; sqtd = p, i++) {
2358 p = sqtd->nextqtd;
2359 ehci_free_sqtd(sc, sqtd);
2360 }
2361 }
2362
2363 /****************/
2364
2365 /*
2366 * Close a reqular pipe.
2367 * Assumes that there are no pending transactions.
2368 */
2369 void
ehci_close_pipe(usbd_pipe_handle pipe,ehci_soft_qh_t * head)2370 ehci_close_pipe(usbd_pipe_handle pipe, ehci_soft_qh_t *head)
2371 {
2372 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
2373 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2374 ehci_soft_qh_t *sqh = epipe->sqh;
2375 int s;
2376
2377 s = splusb();
2378 ehci_rem_qh(sc, sqh, head);
2379 splx(s);
2380 ehci_free_sqh(sc, epipe->sqh);
2381 }
2382
2383 /*
2384 * Abort a device request.
2385 * If this routine is called at splusb() it guarantees that the request
2386 * will be removed from the hardware scheduling and that the callback
2387 * for it will be called with USBD_CANCELLED status.
2388 * It's impossible to guarantee that the requested transfer will not
2389 * have happened since the hardware runs concurrently.
2390 * If the transaction has already happened we rely on the ordinary
2391 * interrupt processing to process it.
2392 * XXX This is most probably wrong.
2393 */
2394 void
ehci_abort_xfer(usbd_xfer_handle xfer,usbd_status status)2395 ehci_abort_xfer(usbd_xfer_handle xfer, usbd_status status)
2396 {
2397 #define exfer EXFER(xfer)
2398 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2399 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2400 ehci_soft_qh_t *sqh = epipe->sqh;
2401 ehci_soft_qtd_t *sqtd;
2402 ehci_physaddr_t cur;
2403 u_int32_t qhstatus;
2404 int s;
2405 int hit;
2406
2407 DPRINTF(("ehci_abort_xfer: xfer=%p pipe=%p\n", xfer, epipe));
2408
2409 if (sc->sc_dying) {
2410 /* If we're dying, just do the software part. */
2411 s = splusb();
2412 xfer->status = status; /* make software ignore it */
2413 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
2414 usb_transfer_complete(xfer);
2415 splx(s);
2416 return;
2417 }
2418
2419 if (xfer->device->bus->intr_context || !curproc)
2420 panic("ehci_abort_xfer: not in process context");
2421
2422 /*
2423 * Step 1: Make interrupt routine and hardware ignore xfer.
2424 */
2425 s = splusb();
2426 xfer->status = status; /* make software ignore it */
2427 usb_uncallout(xfer->timeout_handle, ehci_timeout, xfer);
2428 qhstatus = sqh->qh.qh_qtd.qtd_status;
2429 sqh->qh.qh_qtd.qtd_status = qhstatus | htole32(EHCI_QTD_HALTED);
2430 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2431 sqtd->qtd.qtd_status |= htole32(EHCI_QTD_HALTED);
2432 if (sqtd == exfer->sqtdend)
2433 break;
2434 }
2435 splx(s);
2436
2437 /*
2438 * Step 2: Wait until we know hardware has finished any possible
2439 * use of the xfer. Also make sure the soft interrupt routine
2440 * has run.
2441 */
2442 ehci_sync_hc(sc);
2443 s = splusb();
2444 #ifdef USB_USE_SOFTINTR
2445 sc->sc_softwake = 1;
2446 #endif /* USB_USE_SOFTINTR */
2447 usb_schedsoftintr(&sc->sc_bus);
2448 #ifdef USB_USE_SOFTINTR
2449 tsleep(&sc->sc_softwake, PZERO, "ehciab", 0);
2450 #endif /* USB_USE_SOFTINTR */
2451 splx(s);
2452
2453 /*
2454 * Step 3: Remove any vestiges of the xfer from the hardware.
2455 * The complication here is that the hardware may have executed
2456 * beyond the xfer we're trying to abort. So as we're scanning
2457 * the TDs of this xfer we check if the hardware points to
2458 * any of them.
2459 */
2460 s = splusb(); /* XXX why? */
2461 cur = EHCI_LINK_ADDR(le32toh(sqh->qh.qh_curqtd));
2462 hit = 0;
2463 for (sqtd = exfer->sqtdstart; ; sqtd = sqtd->nextqtd) {
2464 hit |= cur == sqtd->physaddr;
2465 if (sqtd == exfer->sqtdend)
2466 break;
2467 }
2468 sqtd = sqtd->nextqtd;
2469 /* Zap curqtd register if hardware pointed inside the xfer. */
2470 if (hit && sqtd != NULL) {
2471 DPRINTFN(1,("ehci_abort_xfer: cur=0x%08x\n", sqtd->physaddr));
2472 sqh->qh.qh_curqtd = htole32(sqtd->physaddr); /* unlink qTDs */
2473 sqh->qh.qh_qtd.qtd_status = qhstatus;
2474 } else {
2475 DPRINTFN(1,("ehci_abort_xfer: no hit\n"));
2476 }
2477
2478 /*
2479 * Step 4: Execute callback.
2480 */
2481 #ifdef DIAGNOSTIC
2482 exfer->isdone = 1;
2483 #endif
2484 usb_transfer_complete(xfer);
2485
2486 splx(s);
2487 #undef exfer
2488 }
2489
2490 void
ehci_timeout(void * addr)2491 ehci_timeout(void *addr)
2492 {
2493 struct ehci_xfer *exfer = addr;
2494 struct ehci_pipe *epipe = (struct ehci_pipe *)exfer->xfer.pipe;
2495 ehci_softc_t *sc = (ehci_softc_t *)epipe->pipe.device->bus;
2496
2497 DPRINTF(("ehci_timeout: exfer=%p\n", exfer));
2498 #ifdef USB_DEBUG
2499 if (ehcidebug > 1)
2500 usbd_dump_pipe(exfer->xfer.pipe);
2501 #endif
2502
2503 if (sc->sc_dying) {
2504 ehci_abort_xfer(&exfer->xfer, USBD_TIMEOUT);
2505 return;
2506 }
2507
2508 /* Execute the abort in a process context. */
2509 usb_init_task(&exfer->abort_task, ehci_timeout_task, addr);
2510 usb_add_task(exfer->xfer.pipe->device, &exfer->abort_task);
2511 }
2512
2513 void
ehci_timeout_task(void * addr)2514 ehci_timeout_task(void *addr)
2515 {
2516 usbd_xfer_handle xfer = addr;
2517 int s;
2518
2519 DPRINTF(("ehci_timeout_task: xfer=%p\n", xfer));
2520
2521 s = splusb();
2522 ehci_abort_xfer(xfer, USBD_TIMEOUT);
2523 splx(s);
2524 }
2525
2526 /*
2527 * Some EHCI chips from VIA seem to trigger interrupts before writing back the
2528 * qTD status, or miss signalling occasionally under heavy load. If the host
2529 * machine is too fast, we we can miss transaction completion - when we scan
2530 * the active list the transaction still seems to be active. This generally
2531 * exhibits itself as a umass stall that never recovers.
2532 *
2533 * We work around this behaviour by setting up this callback after any softintr
2534 * that completes with transactions still pending, giving us another chance to
2535 * check for completion after the writeback has taken place.
2536 */
2537 void
ehci_intrlist_timeout(void * arg)2538 ehci_intrlist_timeout(void *arg)
2539 {
2540 ehci_softc_t *sc = arg;
2541 int s = splusb();
2542
2543 DPRINTFN(1, ("ehci_intrlist_timeout\n"));
2544 usb_schedsoftintr(&sc->sc_bus);
2545
2546 splx(s);
2547 }
2548
2549 /************************/
2550
2551 Static usbd_status
ehci_device_ctrl_transfer(usbd_xfer_handle xfer)2552 ehci_device_ctrl_transfer(usbd_xfer_handle xfer)
2553 {
2554 usbd_status err;
2555
2556 /* Insert last in queue. */
2557 err = usb_insert_transfer(xfer);
2558 if (err)
2559 return (err);
2560
2561 /* Pipe isn't running, start first */
2562 return (ehci_device_ctrl_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2563 }
2564
2565 Static usbd_status
ehci_device_ctrl_start(usbd_xfer_handle xfer)2566 ehci_device_ctrl_start(usbd_xfer_handle xfer)
2567 {
2568 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2569 usbd_status err;
2570
2571 if (sc->sc_dying)
2572 return (USBD_IOERROR);
2573
2574 #ifdef DIAGNOSTIC
2575 if (!(xfer->rqflags & URQ_REQUEST)) {
2576 /* XXX panic */
2577 printf("ehci_device_ctrl_transfer: not a request\n");
2578 return (USBD_INVAL);
2579 }
2580 #endif
2581
2582 err = ehci_device_request(xfer);
2583 if (err)
2584 return (err);
2585
2586 if (sc->sc_bus.use_polling)
2587 ehci_waitintr(sc, xfer);
2588 return (USBD_IN_PROGRESS);
2589 }
2590
2591 void
ehci_device_ctrl_done(usbd_xfer_handle xfer)2592 ehci_device_ctrl_done(usbd_xfer_handle xfer)
2593 {
2594 struct ehci_xfer *ex = EXFER(xfer);
2595 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2596 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2597
2598 DPRINTFN(10,("ehci_ctrl_done: xfer=%p\n", xfer));
2599
2600 #ifdef DIAGNOSTIC
2601 if (!(xfer->rqflags & URQ_REQUEST)) {
2602 panic("ehci_ctrl_done: not a request");
2603 }
2604 #endif
2605
2606 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
2607 ehci_del_intr_list(ex); /* remove from active list */
2608 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2609 }
2610
2611 DPRINTFN(5, ("ehci_ctrl_done: length=%d\n", xfer->actlen));
2612 }
2613
2614 /* Abort a device control request. */
2615 Static void
ehci_device_ctrl_abort(usbd_xfer_handle xfer)2616 ehci_device_ctrl_abort(usbd_xfer_handle xfer)
2617 {
2618 DPRINTF(("ehci_device_ctrl_abort: xfer=%p\n", xfer));
2619 ehci_abort_xfer(xfer, USBD_CANCELLED);
2620 }
2621
2622 /* Close a device control pipe. */
2623 Static void
ehci_device_ctrl_close(usbd_pipe_handle pipe)2624 ehci_device_ctrl_close(usbd_pipe_handle pipe)
2625 {
2626 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2627 /*struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;*/
2628
2629 DPRINTF(("ehci_device_ctrl_close: pipe=%p\n", pipe));
2630 ehci_close_pipe(pipe, sc->sc_async_head);
2631 }
2632
2633 usbd_status
ehci_device_request(usbd_xfer_handle xfer)2634 ehci_device_request(usbd_xfer_handle xfer)
2635 {
2636 #define exfer EXFER(xfer)
2637 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2638 usb_device_request_t *req = &xfer->request;
2639 usbd_device_handle dev = epipe->pipe.device;
2640 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2641 int addr = dev->address;
2642 ehci_soft_qtd_t *setup, *stat, *next;
2643 ehci_soft_qh_t *sqh;
2644 int isread;
2645 int len;
2646 usbd_status err;
2647 int s;
2648
2649 isread = req->bmRequestType & UT_READ;
2650 len = UGETW(req->wLength);
2651
2652 DPRINTFN(3,("ehci_device_request: type=0x%02x, request=0x%02x, "
2653 "wValue=0x%04x, wIndex=0x%04x len=%d, addr=%d, endpt=%d\n",
2654 req->bmRequestType, req->bRequest, UGETW(req->wValue),
2655 UGETW(req->wIndex), len, addr,
2656 epipe->pipe.endpoint->edesc->bEndpointAddress));
2657
2658 setup = ehci_alloc_sqtd(sc);
2659 if (setup == NULL) {
2660 err = USBD_NOMEM;
2661 goto bad1;
2662 }
2663 stat = ehci_alloc_sqtd(sc);
2664 if (stat == NULL) {
2665 err = USBD_NOMEM;
2666 goto bad2;
2667 }
2668
2669 sqh = epipe->sqh;
2670 epipe->u.ctl.length = len;
2671
2672 /* Update device address and length since they may have changed
2673 during the setup of the control pipe in usbd_new_device(). */
2674 /* XXX This only needs to be done once, but it's too early in open. */
2675 /* XXXX Should not touch ED here! */
2676 sqh->qh.qh_endp =
2677 (sqh->qh.qh_endp & htole32(~(EHCI_QH_ADDRMASK | EHCI_QH_MPLMASK))) |
2678 htole32(
2679 EHCI_QH_SET_ADDR(addr) |
2680 EHCI_QH_SET_MPL(UGETW(epipe->pipe.endpoint->edesc->wMaxPacketSize))
2681 );
2682
2683 /* Set up data transaction */
2684 if (len != 0) {
2685 ehci_soft_qtd_t *end;
2686
2687 /* Start toggle at 1. */
2688 epipe->nexttoggle = 1;
2689 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
2690 &next, &end);
2691 if (err)
2692 goto bad3;
2693 end->qtd.qtd_status &= htole32(~EHCI_QTD_IOC);
2694 end->nextqtd = stat;
2695 end->qtd.qtd_next =
2696 end->qtd.qtd_altnext = htole32(stat->physaddr);
2697 } else {
2698 next = stat;
2699 }
2700
2701 memcpy(KERNADDR(&epipe->u.ctl.reqdma, 0), req, sizeof(*req));
2702
2703 /* Clear toggle */
2704 setup->qtd.qtd_status = htole32(
2705 EHCI_QTD_ACTIVE |
2706 EHCI_QTD_SET_PID(EHCI_QTD_PID_SETUP) |
2707 EHCI_QTD_SET_CERR(3) |
2708 EHCI_QTD_SET_TOGGLE(0) |
2709 EHCI_QTD_SET_BYTES(sizeof(*req)));
2710 setup->qtd.qtd_buffer[0] = htole32(DMAADDR(&epipe->u.ctl.reqdma, 0));
2711 setup->qtd.qtd_buffer_hi[0] = 0;
2712 setup->nextqtd = next;
2713 setup->qtd.qtd_next = setup->qtd.qtd_altnext = htole32(next->physaddr);
2714 setup->xfer = xfer;
2715 setup->len = sizeof(*req);
2716
2717 stat->qtd.qtd_status = htole32(
2718 EHCI_QTD_ACTIVE |
2719 EHCI_QTD_SET_PID(isread ? EHCI_QTD_PID_OUT : EHCI_QTD_PID_IN) |
2720 EHCI_QTD_SET_CERR(3) |
2721 EHCI_QTD_SET_TOGGLE(1) |
2722 EHCI_QTD_IOC);
2723 stat->qtd.qtd_buffer[0] = 0; /* XXX not needed? */
2724 stat->qtd.qtd_buffer_hi[0] = 0; /* XXX not needed? */
2725 stat->nextqtd = NULL;
2726 stat->qtd.qtd_next = stat->qtd.qtd_altnext = EHCI_NULL;
2727 stat->xfer = xfer;
2728 stat->len = 0;
2729
2730 #ifdef EHCI_DEBUG
2731 if (ehcidebug > 5) {
2732 DPRINTF(("ehci_device_request:\n"));
2733 ehci_dump_sqh(sqh);
2734 ehci_dump_sqtds(setup);
2735 }
2736 #endif
2737
2738 exfer->sqtdstart = setup;
2739 exfer->sqtdend = stat;
2740 #ifdef DIAGNOSTIC
2741 if (!exfer->isdone) {
2742 printf("ehci_device_request: not done, exfer=%p\n", exfer);
2743 }
2744 exfer->isdone = 0;
2745 #endif
2746
2747 /* Insert qTD in QH list. */
2748 s = splusb();
2749 ehci_set_qh_qtd(sqh, setup);
2750 if (xfer->timeout && !sc->sc_bus.use_polling) {
2751 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout),
2752 ehci_timeout, xfer);
2753 }
2754 ehci_add_intr_list(sc, exfer);
2755 xfer->status = USBD_IN_PROGRESS;
2756 splx(s);
2757
2758 #ifdef EHCI_DEBUG
2759 if (ehcidebug > 10) {
2760 DPRINTF(("ehci_device_request: status=%x\n",
2761 EOREAD4(sc, EHCI_USBSTS)));
2762 delay(10000);
2763 ehci_dump_regs(sc);
2764 ehci_dump_sqh(sc->sc_async_head);
2765 ehci_dump_sqh(sqh);
2766 ehci_dump_sqtds(setup);
2767 }
2768 #endif
2769
2770 return (USBD_NORMAL_COMPLETION);
2771
2772 bad3:
2773 ehci_free_sqtd(sc, stat);
2774 bad2:
2775 ehci_free_sqtd(sc, setup);
2776 bad1:
2777 DPRINTFN(-1,("ehci_device_request: no memory\n"));
2778 xfer->status = err;
2779 usb_transfer_complete(xfer);
2780 return (err);
2781 #undef exfer
2782 }
2783
2784 /************************/
2785
2786 Static usbd_status
ehci_device_bulk_transfer(usbd_xfer_handle xfer)2787 ehci_device_bulk_transfer(usbd_xfer_handle xfer)
2788 {
2789 usbd_status err;
2790
2791 /* Insert last in queue. */
2792 err = usb_insert_transfer(xfer);
2793 if (err)
2794 return (err);
2795
2796 /* Pipe isn't running, start first */
2797 return (ehci_device_bulk_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2798 }
2799
2800 usbd_status
ehci_device_bulk_start(usbd_xfer_handle xfer)2801 ehci_device_bulk_start(usbd_xfer_handle xfer)
2802 {
2803 #define exfer EXFER(xfer)
2804 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2805 usbd_device_handle dev = epipe->pipe.device;
2806 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2807 ehci_soft_qtd_t *data, *dataend;
2808 ehci_soft_qh_t *sqh;
2809 usbd_status err;
2810 int len, isread, endpt;
2811 int s;
2812
2813 DPRINTFN(2, ("ehci_device_bulk_start: xfer=%p len=%d flags=%d\n",
2814 xfer, xfer->length, xfer->flags));
2815
2816 if (sc->sc_dying)
2817 return (USBD_IOERROR);
2818
2819 #ifdef DIAGNOSTIC
2820 if (xfer->rqflags & URQ_REQUEST)
2821 panic("ehci_device_bulk_start: a request");
2822 #endif
2823
2824 len = xfer->length;
2825 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2826 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2827 sqh = epipe->sqh;
2828
2829 epipe->u.bulk.length = len;
2830
2831 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
2832 &dataend);
2833 if (err) {
2834 DPRINTFN(-1,("ehci_device_bulk_transfer: no memory\n"));
2835 xfer->status = err;
2836 usb_transfer_complete(xfer);
2837 return (err);
2838 }
2839
2840 #ifdef EHCI_DEBUG
2841 if (ehcidebug > 5) {
2842 DPRINTF(("ehci_device_bulk_start: data(1)\n"));
2843 ehci_dump_sqh(sqh);
2844 ehci_dump_sqtds(data);
2845 }
2846 #endif
2847
2848 /* Set up interrupt info. */
2849 exfer->sqtdstart = data;
2850 exfer->sqtdend = dataend;
2851 #ifdef DIAGNOSTIC
2852 if (!exfer->isdone) {
2853 printf("ehci_device_bulk_start: not done, ex=%p\n", exfer);
2854 }
2855 exfer->isdone = 0;
2856 #endif
2857
2858 s = splusb();
2859 ehci_set_qh_qtd(sqh, data);
2860 if (xfer->timeout && !sc->sc_bus.use_polling) {
2861 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout),
2862 ehci_timeout, xfer);
2863 }
2864 ehci_add_intr_list(sc, exfer);
2865 xfer->status = USBD_IN_PROGRESS;
2866 splx(s);
2867
2868 #ifdef EHCI_DEBUG
2869 if (ehcidebug > 10) {
2870 DPRINTF(("ehci_device_bulk_start: data(2)\n"));
2871 delay(10000);
2872 DPRINTF(("ehci_device_bulk_start: data(3)\n"));
2873 ehci_dump_regs(sc);
2874 #if 0
2875 printf("async_head:\n");
2876 ehci_dump_sqh(sc->sc_async_head);
2877 #endif
2878 printf("sqh:\n");
2879 ehci_dump_sqh(sqh);
2880 ehci_dump_sqtds(data);
2881 }
2882 #endif
2883
2884 if (sc->sc_bus.use_polling)
2885 ehci_waitintr(sc, xfer);
2886
2887 return (USBD_IN_PROGRESS);
2888 #undef exfer
2889 }
2890
2891 Static void
ehci_device_bulk_abort(usbd_xfer_handle xfer)2892 ehci_device_bulk_abort(usbd_xfer_handle xfer)
2893 {
2894 DPRINTF(("ehci_device_bulk_abort: xfer=%p\n", xfer));
2895 ehci_abort_xfer(xfer, USBD_CANCELLED);
2896 }
2897
2898 /*
2899 * Close a device bulk pipe.
2900 */
2901 Static void
ehci_device_bulk_close(usbd_pipe_handle pipe)2902 ehci_device_bulk_close(usbd_pipe_handle pipe)
2903 {
2904 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
2905
2906 DPRINTF(("ehci_device_bulk_close: pipe=%p\n", pipe));
2907 ehci_close_pipe(pipe, sc->sc_async_head);
2908 }
2909
2910 void
ehci_device_bulk_done(usbd_xfer_handle xfer)2911 ehci_device_bulk_done(usbd_xfer_handle xfer)
2912 {
2913 struct ehci_xfer *ex = EXFER(xfer);
2914 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
2915 /*struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;*/
2916
2917 DPRINTFN(10,("ehci_bulk_done: xfer=%p, actlen=%d\n",
2918 xfer, xfer->actlen));
2919
2920 if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
2921 ehci_del_intr_list(ex); /* remove from active list */
2922 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
2923 }
2924
2925 DPRINTFN(5, ("ehci_bulk_done: length=%d\n", xfer->actlen));
2926 }
2927
2928 /************************/
2929
2930 Static usbd_status
ehci_device_setintr(ehci_softc_t * sc,ehci_soft_qh_t * sqh,int ival)2931 ehci_device_setintr(ehci_softc_t *sc, ehci_soft_qh_t *sqh, int ival)
2932 {
2933 struct ehci_soft_islot *isp;
2934 int islot, lev;
2935
2936 /* Find a poll rate that is large enough. */
2937 for (lev = EHCI_IPOLLRATES - 1; lev > 0; lev--)
2938 if (EHCI_ILEV_IVAL(lev) <= ival)
2939 break;
2940
2941 /* Pick an interrupt slot at the right level. */
2942 /* XXX could do better than picking at random */
2943 islot = EHCI_IQHIDX(lev, arc4random());
2944
2945 sqh->islot = islot;
2946 isp = &sc->sc_islots[islot];
2947 ehci_add_qh(sqh, isp->sqh);
2948
2949 return (USBD_NORMAL_COMPLETION);
2950 }
2951
2952 Static usbd_status
ehci_device_intr_transfer(usbd_xfer_handle xfer)2953 ehci_device_intr_transfer(usbd_xfer_handle xfer)
2954 {
2955 usbd_status err;
2956
2957 /* Insert last in queue. */
2958 err = usb_insert_transfer(xfer);
2959 if (err)
2960 return (err);
2961
2962 /*
2963 * Pipe isn't running (otherwise err would be USBD_INPROG),
2964 * so start it first.
2965 */
2966 return (ehci_device_intr_start(SIMPLEQ_FIRST(&xfer->pipe->queue)));
2967 }
2968
2969 Static usbd_status
ehci_device_intr_start(usbd_xfer_handle xfer)2970 ehci_device_intr_start(usbd_xfer_handle xfer)
2971 {
2972 #define exfer EXFER(xfer)
2973 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
2974 usbd_device_handle dev = xfer->pipe->device;
2975 ehci_softc_t *sc = (ehci_softc_t *)dev->bus;
2976 ehci_soft_qtd_t *data, *dataend;
2977 ehci_soft_qh_t *sqh;
2978 usbd_status err;
2979 int len, isread, endpt;
2980 int s;
2981
2982 DPRINTFN(2, ("ehci_device_intr_start: xfer=%p len=%d flags=%d\n",
2983 xfer, xfer->length, xfer->flags));
2984
2985 if (sc->sc_dying)
2986 return (USBD_IOERROR);
2987
2988 #ifdef DIAGNOSTIC
2989 if (xfer->rqflags & URQ_REQUEST)
2990 panic("ehci_device_intr_start: a request");
2991 #endif
2992
2993 len = xfer->length;
2994 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
2995 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
2996 sqh = epipe->sqh;
2997
2998 epipe->u.intr.length = len;
2999
3000 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer, &data,
3001 &dataend);
3002 if (err) {
3003 DPRINTFN(-1, ("ehci_device_intr_start: no memory\n"));
3004 xfer->status = err;
3005 usb_transfer_complete(xfer);
3006 return (err);
3007 }
3008
3009 #ifdef EHCI_DEBUG
3010 if (ehcidebug > 5) {
3011 DPRINTF(("ehci_device_intr_start: data(1)\n"));
3012 ehci_dump_sqh(sqh);
3013 ehci_dump_sqtds(data);
3014 }
3015 #endif
3016
3017 /* Set up interrupt info. */
3018 exfer->sqtdstart = data;
3019 exfer->sqtdend = dataend;
3020 #ifdef DIAGNOSTIC
3021 if (!exfer->isdone)
3022 printf("ehci_device_intr_start: not done, ex=%p\n", exfer);
3023 exfer->isdone = 0;
3024 #endif
3025
3026 s = splusb();
3027 ehci_set_qh_qtd(sqh, data);
3028 if (xfer->timeout && !sc->sc_bus.use_polling)
3029 usb_callout(xfer->timeout_handle, mstohz(xfer->timeout),
3030 ehci_timeout, xfer);
3031 ehci_add_intr_list(sc, exfer);
3032 xfer->status = USBD_IN_PROGRESS;
3033 splx(s);
3034
3035 #ifdef EHCI_DEBUG
3036 if (ehcidebug > 10) {
3037 DPRINTF(("ehci_device_intr_start: data(2)\n"));
3038 delay(10000);
3039 DPRINTF(("ehci_device_intr_start: data(3)\n"));
3040 ehci_dump_regs(sc);
3041 printf("sqh:\n");
3042 ehci_dump_sqh(sqh);
3043 ehci_dump_sqtds(data);
3044 }
3045 #endif
3046
3047 if (sc->sc_bus.use_polling)
3048 ehci_waitintr(sc, xfer);
3049
3050 return (USBD_IN_PROGRESS);
3051 #undef exfer
3052 }
3053
3054 Static void
ehci_device_intr_abort(usbd_xfer_handle xfer)3055 ehci_device_intr_abort(usbd_xfer_handle xfer)
3056 {
3057 DPRINTFN(1, ("ehci_device_intr_abort: xfer=%p\n", xfer));
3058 if (xfer->pipe->intrxfer == xfer) {
3059 DPRINTFN(1, ("echi_device_intr_abort: remove\n"));
3060 xfer->pipe->intrxfer = NULL;
3061 }
3062 ehci_abort_xfer(xfer, USBD_CANCELLED);
3063 }
3064
3065 Static void
ehci_device_intr_close(usbd_pipe_handle pipe)3066 ehci_device_intr_close(usbd_pipe_handle pipe)
3067 {
3068 ehci_softc_t *sc = (ehci_softc_t *)pipe->device->bus;
3069 struct ehci_pipe *epipe = (struct ehci_pipe *)pipe;
3070 struct ehci_soft_islot *isp;
3071
3072 isp = &sc->sc_islots[epipe->sqh->islot];
3073 ehci_close_pipe(pipe, isp->sqh);
3074 }
3075
3076 Static void
ehci_device_intr_done(usbd_xfer_handle xfer)3077 ehci_device_intr_done(usbd_xfer_handle xfer)
3078 {
3079 #define exfer EXFER(xfer)
3080 struct ehci_xfer *ex = EXFER(xfer);
3081 ehci_softc_t *sc = (ehci_softc_t *)xfer->pipe->device->bus;
3082 struct ehci_pipe *epipe = (struct ehci_pipe *)xfer->pipe;
3083 ehci_soft_qtd_t *data, *dataend;
3084 ehci_soft_qh_t *sqh;
3085 usbd_status err;
3086 int len, isread, endpt, s;
3087
3088 DPRINTFN(10, ("ehci_device_intr_done: xfer=%p, actlen=%d\n",
3089 xfer, xfer->actlen));
3090
3091 if (xfer->pipe->repeat) {
3092 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3093
3094 len = epipe->u.intr.length;
3095 xfer->length = len;
3096 endpt = epipe->pipe.endpoint->edesc->bEndpointAddress;
3097 isread = UE_GET_DIR(endpt) == UE_DIR_IN;
3098 sqh = epipe->sqh;
3099
3100 err = ehci_alloc_sqtd_chain(epipe, sc, len, isread, xfer,
3101 &data, &dataend);
3102 if (err) {
3103 DPRINTFN(-1, ("ehci_device_intr_done: no memory\n"));
3104 xfer->status = err;
3105 return;
3106 }
3107
3108 /* Set up interrupt info. */
3109 exfer->sqtdstart = data;
3110 exfer->sqtdend = dataend;
3111 #ifdef DIAGNOSTIC
3112 if (!exfer->isdone) {
3113 printf("ehci_device_intr_done: not done, ex=%p\n",
3114 exfer);
3115 }
3116 exfer->isdone = 0;
3117 #endif
3118
3119 s = splusb();
3120 ehci_set_qh_qtd(sqh, data);
3121 if (xfer->timeout && !sc->sc_bus.use_polling) {
3122 usb_callout(xfer->timeout_handle,
3123 mstohz(xfer->timeout), ehci_timeout, xfer);
3124 }
3125 splx(s);
3126
3127 xfer->status = USBD_IN_PROGRESS;
3128 } else if (xfer->status != USBD_NOMEM && ehci_active_intr_list(ex)) {
3129 ehci_del_intr_list(ex); /* remove from active list */
3130 ehci_free_sqtd_chain(sc, ex->sqtdstart, NULL);
3131 }
3132 #undef exfer
3133 }
3134
3135 /************************/
3136
ehci_device_isoc_transfer(usbd_xfer_handle xfer)3137 Static usbd_status ehci_device_isoc_transfer(usbd_xfer_handle xfer) { return USBD_IOERROR; }
ehci_device_isoc_start(usbd_xfer_handle xfer)3138 Static usbd_status ehci_device_isoc_start(usbd_xfer_handle xfer) { return USBD_IOERROR; }
ehci_device_isoc_abort(usbd_xfer_handle xfer)3139 Static void ehci_device_isoc_abort(usbd_xfer_handle xfer) { }
ehci_device_isoc_close(usbd_pipe_handle pipe)3140 Static void ehci_device_isoc_close(usbd_pipe_handle pipe) { }
ehci_device_isoc_done(usbd_xfer_handle xfer)3141 Static void ehci_device_isoc_done(usbd_xfer_handle xfer) { }
3142