1 /* $OpenBSD: qec.c,v 1.8 2003/06/27 01:36:53 jason Exp $ */
2 /* $NetBSD: qec.c,v 1.12 2000/12/04 20:12:55 fvdl Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 #include <sys/types.h>
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/kernel.h>
44 #include <sys/errno.h>
45 #include <sys/device.h>
46 #include <sys/malloc.h>
47
48 #include <machine/bus.h>
49 #include <machine/intr.h>
50 #include <machine/autoconf.h>
51
52 #include <dev/sbus/sbusvar.h>
53 #include <dev/sbus/qecreg.h>
54 #include <dev/sbus/qecvar.h>
55
56 int qecprint(void *, const char *);
57 int qecmatch(struct device *, void *, void *);
58 void qecattach(struct device *, struct device *, void *);
59 void qec_init(struct qec_softc *);
60
61 int qec_bus_map(
62 bus_space_tag_t,
63 bus_space_tag_t,
64 bus_addr_t, /*offset*/
65 bus_size_t, /*size*/
66 int, /*flags*/
67 bus_space_handle_t *);
68 void * qec_intr_establish(
69 bus_space_tag_t,
70 bus_space_tag_t,
71 int, /*bus interrupt priority*/
72 int, /*`device class' interrupt level*/
73 int, /*flags*/
74 int (*)(void *), /*handler*/
75 void *, /*arg*/
76 const char *); /*what*/
77
78 struct cfattach qec_ca = {
79 sizeof(struct qec_softc), qecmatch, qecattach
80 };
81
82 struct cfdriver qec_cd = {
83 NULL, "qec", DV_DULL
84 };
85
86 int
qecprint(aux,busname)87 qecprint(aux, busname)
88 void *aux;
89 const char *busname;
90 {
91 struct sbus_attach_args *sa = aux;
92 bus_space_tag_t t = sa->sa_bustag;
93 struct qec_softc *sc = t->cookie;
94
95 sa->sa_bustag = sc->sc_bustag; /* XXX */
96 sbus_print(aux, busname); /* XXX */
97 sa->sa_bustag = t; /* XXX */
98 return (UNCONF);
99 }
100
101 int
qecmatch(parent,vcf,aux)102 qecmatch(parent, vcf, aux)
103 struct device *parent;
104 void *vcf;
105 void *aux;
106 {
107 struct cfdata *cf = vcf;
108 struct sbus_attach_args *sa = aux;
109
110 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
111 }
112
113 /*
114 * Attach all the sub-devices we can find
115 */
116 void
qecattach(parent,self,aux)117 qecattach(parent, self, aux)
118 struct device *parent, *self;
119 void *aux;
120 {
121 struct sbus_attach_args *sa = aux;
122 struct qec_softc *sc = (void *)self;
123 int node;
124 int sbusburst;
125 struct sparc_bus_space_tag *sbt;
126 bus_space_handle_t bh;
127 int error;
128
129 sc->sc_bustag = sa->sa_bustag;
130 sc->sc_dmatag = sa->sa_dmatag;
131 node = sa->sa_node;
132
133 if (sa->sa_nreg < 2) {
134 printf("%s: only %d register sets\n",
135 self->dv_xname, sa->sa_nreg);
136 return;
137 }
138
139 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
140 sa->sa_reg[0].sbr_offset, sa->sa_reg[0].sbr_size,
141 0, 0, &sc->sc_regs) != 0) {
142 printf("%s: attach: cannot map registers\n", self->dv_xname);
143 return;
144 }
145
146 /*
147 * This device's "register space 1" is just a buffer where the
148 * Lance ring-buffers can be stored. Note the buffer's location
149 * and size, so the child driver can pick them up.
150 */
151 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
152 sa->sa_reg[1].sbr_offset, sa->sa_reg[1].sbr_size, 0, 0, &bh) != 0) {
153 printf("%s: attach: cannot map registers\n", self->dv_xname);
154 return;
155 }
156 sc->sc_buffer = (caddr_t)bus_space_vaddr(sc->sc_bustag, bh);
157 sc->sc_bufsiz = (bus_size_t)sa->sa_reg[1].sbr_size;
158
159 /* Get number of on-board channels */
160 sc->sc_nchannels = getpropint(node, "#channels", -1);
161 if (sc->sc_nchannels == -1) {
162 printf(": no channels\n");
163 return;
164 }
165
166 /*
167 * Get transfer burst size from PROM
168 */
169 sbusburst = ((struct sbus_softc *)parent)->sc_burst;
170 if (sbusburst == 0)
171 sbusburst = SBUS_BURST_32 - 1; /* 1->16 */
172
173 sc->sc_burst = getpropint(node, "burst-sizes", -1);
174 if (sc->sc_burst == -1)
175 /* take SBus burst sizes */
176 sc->sc_burst = sbusburst;
177
178 /* Clamp at parent's burst sizes */
179 sc->sc_burst &= sbusburst;
180
181 sbus_establish(&sc->sc_sd, &sc->sc_dev);
182
183 /*
184 * Collect address translations from the OBP.
185 */
186 error = getprop(node, "ranges", sizeof(struct sbus_range),
187 &sc->sc_nrange, (void **)&sc->sc_range);
188 switch (error) {
189 case 0:
190 break;
191 case ENOENT:
192 default:
193 panic("%s: error getting ranges property", self->dv_xname);
194 }
195
196 /* Allocate a bus tag */
197 sbt = malloc(sizeof(*sbt), M_DEVBUF, M_NOWAIT);
198 if (sbt == NULL) {
199 printf("%s: attach: out of memory\n", self->dv_xname);
200 return;
201 }
202
203 bzero(sbt, sizeof *sbt);
204 strlcpy(sbt->name, sc->sc_dev.dv_xname, sizeof(sbt->name));
205 sbt->cookie = sc;
206 sbt->parent = sc->sc_bustag;
207 sbt->asi = sbt->parent->asi;
208 sbt->sasi = sbt->parent->sasi;
209 sbt->sparc_bus_map = qec_bus_map;
210 sbt->sparc_intr_establish = qec_intr_establish;
211
212 /*
213 * Save interrupt information for use in our qec_intr_establish()
214 * function below. Apparently, the intr level for the quad
215 * ethernet board (qe) is stored in the QEC node rather then
216 * separately in each of the QE nodes.
217 *
218 * XXX - qe.c should call bus_intr_establish() with `level = 0'..
219 * XXX - maybe we should have our own attach args for all that.
220 */
221 sc->sc_intr = sa->sa_intr;
222
223 printf(": %dK memory\n", sc->sc_bufsiz / 1024);
224
225 qec_init(sc);
226
227 /* search through children */
228 for (node = firstchild(node); node; node = nextsibling(node)) {
229 struct sbus_attach_args sa;
230
231 sbus_setup_attach_args((struct sbus_softc *)parent,
232 sbt, sc->sc_dmatag, node, &sa);
233 (void)config_found(&sc->sc_dev, (void *)&sa, qecprint);
234 sbus_destroy_attach_args(&sa);
235 }
236 }
237
238 int
qec_bus_map(t,t0,addr,size,flags,hp)239 qec_bus_map(t, t0, addr, size, flags, hp)
240 bus_space_tag_t t;
241 bus_space_tag_t t0;
242 bus_addr_t addr;
243 bus_size_t size;
244 int flags;
245 bus_space_handle_t *hp;
246 {
247 struct qec_softc *sc = t->cookie;
248 int slot = BUS_ADDR_IOSPACE(addr);
249 bus_addr_t offset = BUS_ADDR_PADDR(addr);
250 int i;
251
252 for (t = t->parent; t; t = t->parent) {
253 if (t->sparc_bus_map != NULL)
254 break;
255 }
256
257 if (t == NULL) {
258 printf("\nqec_bus_map: invalid parent");
259 return (EINVAL);
260 }
261
262 if (flags & BUS_SPACE_MAP_PROMADDRESS) {
263 return ((*t->sparc_bus_map)
264 (t, t0, offset, size, flags, hp));
265 }
266
267 for (i = 0; i < sc->sc_nrange; i++) {
268 bus_addr_t paddr;
269 int iospace;
270
271 if (sc->sc_range[i].cspace != slot)
272 continue;
273
274 /* We've found the connection to the parent bus */
275 paddr = sc->sc_range[i].poffset + offset;
276 iospace = sc->sc_range[i].pspace;
277 return ((*t->sparc_bus_map)
278 (t, t0, BUS_ADDR(iospace, paddr), size, flags, hp));
279 }
280
281 return (EINVAL);
282 }
283
284 void *
qec_intr_establish(t,t0,pri,level,flags,handler,arg,what)285 qec_intr_establish(t, t0, pri, level, flags, handler, arg, what)
286 bus_space_tag_t t;
287 bus_space_tag_t t0;
288 int pri;
289 int level;
290 int flags;
291 int (*handler)(void *);
292 void *arg;
293 const char *what;
294 {
295 struct qec_softc *sc = t->cookie;
296
297 if (pri == 0) {
298 /*
299 * qe.c calls bus_intr_establish() with `pri == 0'
300 * XXX - see also comment in qec_attach().
301 */
302 if (sc->sc_intr == NULL) {
303 printf("%s: warning: no interrupts\n",
304 sc->sc_dev.dv_xname);
305 return (NULL);
306 }
307 pri = sc->sc_intr->sbi_pri;
308 }
309
310 for (t = t->parent; t; t = t->parent) {
311 if (t->sparc_intr_establish != NULL)
312 return ((*t->sparc_intr_establish)
313 (t, t0, pri, level, flags, handler, arg, what));
314 }
315
316 panic("qec_intr_extablish): no handler found");
317
318 return (NULL);
319 }
320
321 void
qec_init(sc)322 qec_init(sc)
323 struct qec_softc *sc;
324 {
325 bus_space_tag_t t = sc->sc_bustag;
326 bus_space_handle_t qr = sc->sc_regs;
327 u_int32_t v, burst = 0, psize;
328 int i;
329
330 /* First, reset the controller */
331 bus_space_write_4(t, qr, QEC_QRI_CTRL, QEC_CTRL_RESET);
332 for (i = 0; i < 1000; i++) {
333 DELAY(100);
334 v = bus_space_read_4(t, qr, QEC_QRI_CTRL);
335 if ((v & QEC_CTRL_RESET) == 0)
336 break;
337 }
338
339 /*
340 * Cut available buffer size into receive and transmit buffers.
341 * XXX - should probably be done in be & qe driver...
342 */
343 v = sc->sc_msize = sc->sc_bufsiz / sc->sc_nchannels;
344 bus_space_write_4(t, qr, QEC_QRI_MSIZE, v);
345
346 v = sc->sc_rsize = sc->sc_bufsiz / (sc->sc_nchannels * 2);
347 bus_space_write_4(t, qr, QEC_QRI_RSIZE, v);
348 bus_space_write_4(t, qr, QEC_QRI_TSIZE, v);
349
350 psize = sc->sc_nchannels == 1 ? QEC_PSIZE_2048 : 0;
351 bus_space_write_4(t, qr, QEC_QRI_PSIZE, psize);
352
353 if (sc->sc_burst & SBUS_BURST_64)
354 burst = QEC_CTRL_B64;
355 else if (sc->sc_burst & SBUS_BURST_32)
356 burst = QEC_CTRL_B32;
357 else
358 burst = QEC_CTRL_B16;
359
360 v = bus_space_read_4(t, qr, QEC_QRI_CTRL);
361 v = (v & QEC_CTRL_MODEMASK) | burst;
362 bus_space_write_4(t, qr, QEC_QRI_CTRL, v);
363 }
364
365 /*
366 * Common routine to initialize the QEC packet ring buffer.
367 * Called from be & qe drivers.
368 */
369 void
qec_meminit(qr,pktbufsz)370 qec_meminit(qr, pktbufsz)
371 struct qec_ring *qr;
372 unsigned int pktbufsz;
373 {
374 bus_addr_t txbufdma, rxbufdma;
375 bus_addr_t dma;
376 caddr_t p;
377 unsigned int ntbuf, nrbuf, i;
378
379 p = qr->rb_membase;
380 dma = qr->rb_dmabase;
381
382 ntbuf = qr->rb_ntbuf;
383 nrbuf = qr->rb_nrbuf;
384
385 /*
386 * Allocate transmit descriptors
387 */
388 qr->rb_txd = (struct qec_xd *)p;
389 qr->rb_txddma = dma;
390 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
391 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
392
393 /*
394 * Allocate receive descriptors
395 */
396 qr->rb_rxd = (struct qec_xd *)p;
397 qr->rb_rxddma = dma;
398 p += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
399 dma += QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd);
400
401
402 /*
403 * Allocate transmit buffers
404 */
405 qr->rb_txbuf = p;
406 txbufdma = dma;
407 p += ntbuf * pktbufsz;
408 dma += ntbuf * pktbufsz;
409
410 /*
411 * Allocate receive buffers
412 */
413 qr->rb_rxbuf = p;
414 rxbufdma = dma;
415 p += nrbuf * pktbufsz;
416 dma += nrbuf * pktbufsz;
417
418 /*
419 * Initialize transmit buffer descriptors
420 */
421 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) {
422 qr->rb_txd[i].xd_addr = (u_int32_t)
423 (txbufdma + (i % ntbuf) * pktbufsz);
424 qr->rb_txd[i].xd_flags = 0;
425 }
426
427 /*
428 * Initialize receive buffer descriptors
429 */
430 for (i = 0; i < QEC_XD_RING_MAXSIZE; i++) {
431 qr->rb_rxd[i].xd_addr = (u_int32_t)
432 (rxbufdma + (i % nrbuf) * pktbufsz);
433 qr->rb_rxd[i].xd_flags = (i < nrbuf)
434 ? QEC_XD_OWN | (pktbufsz & QEC_XD_LENGTH)
435 : 0;
436 }
437
438 qr->rb_tdhead = qr->rb_tdtail = 0;
439 qr->rb_td_nbusy = 0;
440 qr->rb_rdtail = 0;
441 }
442