1 /* $OpenBSD: qe.c,v 1.15 2004/05/12 06:35:11 tedu Exp $ */
2 /* $NetBSD: qe.c,v 1.16 2001/03/30 17:30:18 christos Exp $ */
3
4 /*-
5 * Copyright (c) 1999 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * Copyright (c) 1998 Jason L. Wright.
42 * All rights reserved.
43 *
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
46 * are met:
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 *
53 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
54 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
55 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
56 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
57 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
58 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
59 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
60 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
61 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
62 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
63 */
64
65 /*
66 * Driver for the SBus qec+qe QuadEthernet board.
67 *
68 * This driver was written using the AMD MACE Am79C940 documentation, some
69 * ideas gleaned from the S/Linux driver for this card, Solaris header files,
70 * and a loan of a card from Paul Southworth of the Internet Engineering
71 * Group (www.ieng.com).
72 */
73
74 #define QEDEBUG
75
76 #include "bpfilter.h"
77
78 #include <sys/param.h>
79 #include <sys/systm.h>
80 #include <sys/kernel.h>
81 #include <sys/errno.h>
82 #include <sys/ioctl.h>
83 #include <sys/mbuf.h>
84 #include <sys/socket.h>
85 #include <sys/syslog.h>
86 #include <sys/device.h>
87 #include <sys/malloc.h>
88
89 #include <net/if.h>
90 #include <net/if_dl.h>
91 #include <net/if_types.h>
92 #include <net/netisr.h>
93 #include <net/if_media.h>
94
95 #ifdef INET
96 #include <netinet/in.h>
97 #include <netinet/in_systm.h>
98 #include <netinet/in_var.h>
99 #include <netinet/ip.h>
100 #include <netinet/if_ether.h>
101 #endif
102
103 #ifdef NS
104 #include <netns/ns.h>
105 #include <netns/ns_if.h>
106 #endif
107
108 #if NBPFILTER > 0
109 #include <net/bpf.h>
110 #endif
111
112 #include <machine/bus.h>
113 #include <machine/intr.h>
114 #include <machine/autoconf.h>
115
116 #include <dev/sbus/sbusvar.h>
117 #include <dev/sbus/qecreg.h>
118 #include <dev/sbus/qecvar.h>
119 #include <dev/sbus/qereg.h>
120
121 struct qe_softc {
122 struct device sc_dev; /* base device */
123 struct sbusdev sc_sd; /* sbus device */
124 bus_space_tag_t sc_bustag; /* bus & dma tags */
125 bus_dma_tag_t sc_dmatag;
126 bus_dmamap_t sc_dmamap;
127 struct arpcom sc_arpcom;
128 struct ifmedia sc_ifmedia; /* interface media */
129
130 struct qec_softc *sc_qec; /* QEC parent */
131
132 bus_space_handle_t sc_qr; /* QEC registers */
133 bus_space_handle_t sc_mr; /* MACE registers */
134 bus_space_handle_t sc_cr; /* channel registers */
135
136 int sc_channel; /* channel number */
137 u_int sc_rev; /* board revision */
138
139 int sc_burst;
140
141 struct qec_ring sc_rb; /* Packet Ring Buffer */
142
143 #ifdef QEDEBUG
144 int sc_debug;
145 #endif
146 };
147
148 int qematch(struct device *, void *, void *);
149 void qeattach(struct device *, struct device *, void *);
150
151 void qeinit(struct qe_softc *);
152 void qestart(struct ifnet *);
153 void qestop(struct qe_softc *);
154 void qewatchdog(struct ifnet *);
155 int qeioctl(struct ifnet *, u_long, caddr_t);
156 void qereset(struct qe_softc *);
157
158 int qeintr(void *);
159 int qe_eint(struct qe_softc *, u_int32_t);
160 int qe_rint(struct qe_softc *);
161 int qe_tint(struct qe_softc *);
162 void qe_mcreset(struct qe_softc *);
163
164 int qe_put(struct qe_softc *, int, struct mbuf *);
165 void qe_read(struct qe_softc *, int, int);
166 struct mbuf *qe_get(struct qe_softc *, int, int);
167
168 /* ifmedia callbacks */
169 void qe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
170 int qe_ifmedia_upd(struct ifnet *);
171
172 struct cfattach qe_ca = {
173 sizeof(struct qe_softc), qematch, qeattach
174 };
175
176 struct cfdriver qe_cd = {
177 NULL, "qe", DV_IFNET
178 };
179
180 int
qematch(parent,vcf,aux)181 qematch(parent, vcf, aux)
182 struct device *parent;
183 void *vcf;
184 void *aux;
185 {
186 struct cfdata *cf = vcf;
187 struct sbus_attach_args *sa = aux;
188
189 return (strcmp(cf->cf_driver->cd_name, sa->sa_name) == 0);
190 }
191
192 void
qeattach(parent,self,aux)193 qeattach(parent, self, aux)
194 struct device *parent, *self;
195 void *aux;
196 {
197 struct sbus_attach_args *sa = aux;
198 struct qec_softc *qec = (struct qec_softc *)parent;
199 struct qe_softc *sc = (struct qe_softc *)self;
200 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
201 int node = sa->sa_node;
202 bus_dma_tag_t dmatag = sa->sa_dmatag;
203 bus_dma_segment_t seg;
204 bus_size_t size;
205 int rseg, error;
206 extern void myetheraddr(u_char *);
207
208 /* Pass on the bus tags */
209 sc->sc_bustag = sa->sa_bustag;
210 sc->sc_dmatag = sa->sa_dmatag;
211
212 if (sa->sa_nreg < 2) {
213 printf("%s: only %d register sets\n",
214 self->dv_xname, sa->sa_nreg);
215 return;
216 }
217
218 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[0].sbr_slot,
219 (bus_addr_t)sa->sa_reg[0].sbr_offset,
220 (bus_size_t)sa->sa_reg[0].sbr_size, 0, 0, &sc->sc_cr) != 0) {
221 printf("%s: cannot map registers\n", self->dv_xname);
222 return;
223 }
224
225 if (sbus_bus_map(sa->sa_bustag, sa->sa_reg[1].sbr_slot,
226 (bus_addr_t)sa->sa_reg[1].sbr_offset,
227 (bus_size_t)sa->sa_reg[1].sbr_size, 0, 0, &sc->sc_mr) != 0) {
228 printf("%s: cannot map registers\n", self->dv_xname);
229 return;
230 }
231
232 sc->sc_rev = getpropint(node, "mace-version", -1);
233 printf(" rev %x", sc->sc_rev);
234
235 sc->sc_qec = qec;
236 sc->sc_qr = qec->sc_regs;
237
238 sc->sc_channel = getpropint(node, "channel#", -1);
239 sc->sc_burst = qec->sc_burst;
240
241 qestop(sc);
242
243 /* Note: no interrupt level passed */
244 if (bus_intr_establish(sa->sa_bustag, 0, IPL_NET, 0, qeintr, sc,
245 self->dv_xname) == NULL) {
246 printf(": no interrupt established\n");
247 return;
248 }
249
250 myetheraddr(sc->sc_arpcom.ac_enaddr);
251
252 /*
253 * Allocate descriptor ring and buffers.
254 */
255
256 /* for now, allocate as many bufs as there are ring descriptors */
257 sc->sc_rb.rb_ntbuf = QEC_XD_RING_MAXSIZE;
258 sc->sc_rb.rb_nrbuf = QEC_XD_RING_MAXSIZE;
259
260 size =
261 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
262 QEC_XD_RING_MAXSIZE * sizeof(struct qec_xd) +
263 sc->sc_rb.rb_ntbuf * QE_PKT_BUF_SZ +
264 sc->sc_rb.rb_nrbuf * QE_PKT_BUF_SZ;
265
266 /* Get a DMA handle */
267 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
268 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
269 printf("%s: DMA map create error %d\n", self->dv_xname, error);
270 return;
271 }
272
273 /* Allocate DMA buffer */
274 if ((error = bus_dmamem_alloc(dmatag, size, 0, 0,
275 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
276 printf("%s: DMA buffer alloc error %d\n",
277 self->dv_xname, error);
278 return;
279 }
280
281 /* Map DMA buffer in CPU addressable space */
282 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
283 &sc->sc_rb.rb_membase,
284 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
285 printf("%s: DMA buffer map error %d\n",
286 self->dv_xname, error);
287 bus_dmamem_free(dmatag, &seg, rseg);
288 return;
289 }
290
291 /* Load the buffer */
292 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
293 sc->sc_rb.rb_membase, size, NULL, BUS_DMA_NOWAIT)) != 0) {
294 printf("%s: DMA buffer map load error %d\n",
295 self->dv_xname, error);
296 bus_dmamem_unmap(dmatag, sc->sc_rb.rb_membase, size);
297 bus_dmamem_free(dmatag, &seg, rseg);
298 return;
299 }
300 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
301
302 /* Initialize media properties */
303 ifmedia_init(&sc->sc_ifmedia, 0, qe_ifmedia_upd, qe_ifmedia_sts);
304 ifmedia_add(&sc->sc_ifmedia,
305 IFM_MAKEWORD(IFM_ETHER,IFM_10_T,0,0), 0, NULL);
306 ifmedia_add(&sc->sc_ifmedia,
307 IFM_MAKEWORD(IFM_ETHER,IFM_10_5,0,0), 0, NULL);
308 ifmedia_add(&sc->sc_ifmedia,
309 IFM_MAKEWORD(IFM_ETHER,IFM_AUTO,0,0), 0, NULL);
310 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER|IFM_AUTO);
311
312 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
313 ifp->if_softc = sc;
314 ifp->if_start = qestart;
315 ifp->if_ioctl = qeioctl;
316 ifp->if_watchdog = qewatchdog;
317 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS |
318 IFF_MULTICAST;
319 IFQ_SET_READY(&ifp->if_snd);
320
321 /* Attach the interface. */
322 if_attach(ifp);
323 ether_ifattach(ifp);
324
325 printf(" address %s\n", ether_sprintf(sc->sc_arpcom.ac_enaddr));
326 }
327
328 /*
329 * Pull data off an interface.
330 * Len is the length of data, with local net header stripped.
331 * We copy the data into mbufs. When full cluster sized units are present,
332 * we copy into clusters.
333 */
334 struct mbuf *
qe_get(sc,idx,totlen)335 qe_get(sc, idx, totlen)
336 struct qe_softc *sc;
337 int idx, totlen;
338 {
339 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
340 struct mbuf *m;
341 struct mbuf *top, **mp;
342 int len, pad, boff = 0;
343 caddr_t bp;
344
345 bp = sc->sc_rb.rb_rxbuf + (idx % sc->sc_rb.rb_nrbuf) * QE_PKT_BUF_SZ;
346
347 MGETHDR(m, M_DONTWAIT, MT_DATA);
348 if (m == NULL)
349 return (NULL);
350 m->m_pkthdr.rcvif = ifp;
351 m->m_pkthdr.len = totlen;
352 pad = ALIGN(sizeof(struct ether_header)) - sizeof(struct ether_header);
353 m->m_data += pad;
354 len = MHLEN - pad;
355 top = NULL;
356 mp = ⊤
357
358 while (totlen > 0) {
359 if (top) {
360 MGET(m, M_DONTWAIT, MT_DATA);
361 if (m == NULL) {
362 m_freem(top);
363 return (NULL);
364 }
365 len = MLEN;
366 }
367 if (top && totlen >= MINCLSIZE) {
368 MCLGET(m, M_DONTWAIT);
369 if (m->m_flags & M_EXT)
370 len = MCLBYTES;
371 }
372 m->m_len = len = min(totlen, len);
373 bcopy(bp + boff, mtod(m, caddr_t), len);
374 boff += len;
375 totlen -= len;
376 *mp = m;
377 mp = &m->m_next;
378 }
379
380 return (top);
381 }
382
383 /*
384 * Routine to copy from mbuf chain to transmit buffer in
385 * network buffer memory.
386 */
387 __inline__ int
qe_put(sc,idx,m)388 qe_put(sc, idx, m)
389 struct qe_softc *sc;
390 int idx;
391 struct mbuf *m;
392 {
393 struct mbuf *n;
394 int len, tlen = 0, boff = 0;
395 caddr_t bp;
396
397 bp = sc->sc_rb.rb_txbuf + (idx % sc->sc_rb.rb_ntbuf) * QE_PKT_BUF_SZ;
398
399 for (; m; m = n) {
400 len = m->m_len;
401 if (len == 0) {
402 MFREE(m, n);
403 continue;
404 }
405 bcopy(mtod(m, caddr_t), bp+boff, len);
406 boff += len;
407 tlen += len;
408 MFREE(m, n);
409 }
410 return (tlen);
411 }
412
413 /*
414 * Pass a packet to the higher levels.
415 */
416 __inline__ void
qe_read(sc,idx,len)417 qe_read(sc, idx, len)
418 struct qe_softc *sc;
419 int idx, len;
420 {
421 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
422 struct mbuf *m;
423
424 if (len <= sizeof(struct ether_header) ||
425 len > ETHERMTU + sizeof(struct ether_header)) {
426
427 printf("%s: invalid packet size %d; dropping\n",
428 ifp->if_xname, len);
429
430 ifp->if_ierrors++;
431 return;
432 }
433
434 /*
435 * Pull packet off interface.
436 */
437 m = qe_get(sc, idx, len);
438 if (m == NULL) {
439 ifp->if_ierrors++;
440 return;
441 }
442 ifp->if_ipackets++;
443
444 #if NBPFILTER > 0
445 /*
446 * Check if there's a BPF listener on this interface.
447 * If so, hand off the raw packet to BPF.
448 */
449 if (ifp->if_bpf)
450 bpf_mtap(ifp->if_bpf, m);
451 #endif
452 /* Pass the packet up. */
453 ether_input_mbuf(ifp, m);
454 }
455
456 /*
457 * Start output on interface.
458 * We make two assumptions here:
459 * 1) that the current priority is set to splnet _before_ this code
460 * is called *and* is returned to the appropriate priority after
461 * return
462 * 2) that the IFF_OACTIVE flag is checked before this code is called
463 * (i.e. that the output part of the interface is idle)
464 */
465 void
qestart(ifp)466 qestart(ifp)
467 struct ifnet *ifp;
468 {
469 struct qe_softc *sc = (struct qe_softc *)ifp->if_softc;
470 struct qec_xd *txd = sc->sc_rb.rb_txd;
471 struct mbuf *m;
472 unsigned int bix, len;
473 unsigned int ntbuf = sc->sc_rb.rb_ntbuf;
474
475 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
476 return;
477
478 bix = sc->sc_rb.rb_tdhead;
479
480 for (;;) {
481 IFQ_POLL(&ifp->if_snd, m);
482 if (m == NULL)
483 break;
484
485 IFQ_DEQUEUE(&ifp->if_snd, m);
486
487 #if NBPFILTER > 0
488 /*
489 * If BPF is listening on this interface, let it see the
490 * packet before we commit it to the wire.
491 */
492 if (ifp->if_bpf)
493 bpf_mtap(ifp->if_bpf, m);
494 #endif
495
496 /*
497 * Copy the mbuf chain into the transmit buffer.
498 */
499 len = qe_put(sc, bix, m);
500
501 /*
502 * Initialize transmit registers and start transmission
503 */
504 txd[bix].xd_flags = QEC_XD_OWN | QEC_XD_SOP | QEC_XD_EOP |
505 (len & QEC_XD_LENGTH);
506 bus_space_write_4(sc->sc_bustag, sc->sc_cr, QE_CRI_CTRL,
507 QE_CR_CTRL_TWAKEUP);
508
509 if (++bix == QEC_XD_RING_MAXSIZE)
510 bix = 0;
511
512 if (++sc->sc_rb.rb_td_nbusy == ntbuf) {
513 ifp->if_flags |= IFF_OACTIVE;
514 break;
515 }
516 }
517
518 sc->sc_rb.rb_tdhead = bix;
519 }
520
521 void
qestop(sc)522 qestop(sc)
523 struct qe_softc *sc;
524 {
525 bus_space_tag_t t = sc->sc_bustag;
526 bus_space_handle_t mr = sc->sc_mr;
527 bus_space_handle_t cr = sc->sc_cr;
528 int n;
529
530 #if defined(SUN4U) || defined(__GNUC__)
531 (void)&t;
532 #endif
533 /* Stop the schwurst */
534 bus_space_write_1(t, mr, QE_MRI_BIUCC, QE_MR_BIUCC_SWRST);
535 for (n = 200; n > 0; n--) {
536 if ((bus_space_read_1(t, mr, QE_MRI_BIUCC) &
537 QE_MR_BIUCC_SWRST) == 0)
538 break;
539 DELAY(20);
540 }
541
542 /* then reset */
543 bus_space_write_4(t, cr, QE_CRI_CTRL, QE_CR_CTRL_RESET);
544 for (n = 200; n > 0; n--) {
545 if ((bus_space_read_4(t, cr, QE_CRI_CTRL) &
546 QE_CR_CTRL_RESET) == 0)
547 break;
548 DELAY(20);
549 }
550 }
551
552 /*
553 * Reset interface.
554 */
555 void
qereset(sc)556 qereset(sc)
557 struct qe_softc *sc;
558 {
559 int s;
560
561 s = splnet();
562 qestop(sc);
563 qeinit(sc);
564 splx(s);
565 }
566
567 void
qewatchdog(ifp)568 qewatchdog(ifp)
569 struct ifnet *ifp;
570 {
571 struct qe_softc *sc = ifp->if_softc;
572
573 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
574 ifp->if_oerrors++;
575
576 qereset(sc);
577 }
578
579 /*
580 * Interrupt dispatch.
581 */
582 int
qeintr(arg)583 qeintr(arg)
584 void *arg;
585 {
586 struct qe_softc *sc = (struct qe_softc *)arg;
587 bus_space_tag_t t = sc->sc_bustag;
588 u_int32_t qecstat, qestat;
589 int r = 0;
590
591 #if defined(SUN4U) || defined(__GNUC__)
592 (void)&t;
593 #endif
594 /* Read QEC status and channel status */
595 qecstat = bus_space_read_4(t, sc->sc_qr, QEC_QRI_STAT);
596 #ifdef QEDEBUG
597 if (sc->sc_debug) {
598 printf("qe%d: intr: qecstat=%x\n", sc->sc_channel, qecstat);
599 }
600 #endif
601
602 /* Filter out status for this channel */
603 qecstat = qecstat >> (4 * sc->sc_channel);
604 if ((qecstat & 0xf) == 0)
605 return (r);
606
607 qestat = bus_space_read_4(t, sc->sc_cr, QE_CRI_STAT);
608
609 #ifdef QEDEBUG
610 if (sc->sc_debug) {
611 int i;
612 bus_space_tag_t t = sc->sc_bustag;
613 bus_space_handle_t mr = sc->sc_mr;
614
615 printf("qe%d: intr: qestat=%b\n", sc->sc_channel,
616 qestat, QE_CR_STAT_BITS);
617
618 printf("MACE registers:\n");
619 for (i = 0 ; i < 32; i++) {
620 printf(" m[%d]=%x,", i, bus_space_read_1(t, mr, i));
621 if (((i+1) & 7) == 0)
622 printf("\n");
623 }
624 }
625 #endif
626
627 if (qestat & QE_CR_STAT_ALLERRORS) {
628 #ifdef QEDEBUG
629 if (sc->sc_debug)
630 printf("qe%d: eint: qestat=%b\n", sc->sc_channel,
631 qestat, QE_CR_STAT_BITS);
632 #endif
633 r |= qe_eint(sc, qestat);
634 if (r == -1)
635 return (1);
636 }
637
638 if (qestat & QE_CR_STAT_TXIRQ)
639 r |= qe_tint(sc);
640
641 if (qestat & QE_CR_STAT_RXIRQ)
642 r |= qe_rint(sc);
643
644 return (1);
645 }
646
647 /*
648 * Transmit interrupt.
649 */
650 int
qe_tint(sc)651 qe_tint(sc)
652 struct qe_softc *sc;
653 {
654 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
655 unsigned int bix, txflags;
656
657 bix = sc->sc_rb.rb_tdtail;
658
659 for (;;) {
660 if (sc->sc_rb.rb_td_nbusy <= 0)
661 break;
662
663 txflags = sc->sc_rb.rb_txd[bix].xd_flags;
664
665 if (txflags & QEC_XD_OWN)
666 break;
667
668 ifp->if_flags &= ~IFF_OACTIVE;
669 ifp->if_opackets++;
670
671 if (++bix == QEC_XD_RING_MAXSIZE)
672 bix = 0;
673
674 --sc->sc_rb.rb_td_nbusy;
675 }
676
677 if (sc->sc_rb.rb_td_nbusy == 0)
678 ifp->if_timer = 0;
679
680 if (sc->sc_rb.rb_tdtail != bix) {
681 sc->sc_rb.rb_tdtail = bix;
682 if (ifp->if_flags & IFF_OACTIVE) {
683 ifp->if_flags &= ~IFF_OACTIVE;
684 qestart(ifp);
685 }
686 }
687
688 return (1);
689 }
690
691 /*
692 * Receive interrupt.
693 */
694 int
qe_rint(sc)695 qe_rint(sc)
696 struct qe_softc *sc;
697 {
698 struct qec_xd *xd = sc->sc_rb.rb_rxd;
699 unsigned int bix, len;
700 unsigned int nrbuf = sc->sc_rb.rb_nrbuf;
701 #ifdef QEDEBUG
702 int npackets = 0;
703 #endif
704
705 bix = sc->sc_rb.rb_rdtail;
706
707 /*
708 * Process all buffers with valid data.
709 */
710 for (;;) {
711 len = xd[bix].xd_flags;
712 if (len & QEC_XD_OWN)
713 break;
714
715 #ifdef QEDEBUG
716 npackets++;
717 #endif
718
719 len &= QEC_XD_LENGTH;
720 len -= 4;
721 qe_read(sc, bix, len);
722
723 /* ... */
724 xd[(bix+nrbuf) % QEC_XD_RING_MAXSIZE].xd_flags =
725 QEC_XD_OWN | (QE_PKT_BUF_SZ & QEC_XD_LENGTH);
726
727 if (++bix == QEC_XD_RING_MAXSIZE)
728 bix = 0;
729 }
730 #ifdef QEDEBUG
731 if (npackets == 0 && sc->sc_debug)
732 printf("%s: rint: no packets; rb index %d; status 0x%x\n",
733 sc->sc_dev.dv_xname, bix, len);
734 #endif
735
736 sc->sc_rb.rb_rdtail = bix;
737
738 return (1);
739 }
740
741 /*
742 * Error interrupt.
743 */
744 int
qe_eint(sc,why)745 qe_eint(sc, why)
746 struct qe_softc *sc;
747 u_int32_t why;
748 {
749 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
750 int r = 0, rst = 0;
751
752 if (why & QE_CR_STAT_EDEFER) {
753 printf("%s: excessive tx defers.\n", sc->sc_dev.dv_xname);
754 r |= 1;
755 ifp->if_oerrors++;
756 }
757
758 if (why & QE_CR_STAT_CLOSS) {
759 ifp->if_oerrors++;
760 r |= 1;
761 }
762
763 if (why & QE_CR_STAT_ERETRIES) {
764 printf("%s: excessive tx retries\n", sc->sc_dev.dv_xname);
765 ifp->if_oerrors++;
766 r |= 1;
767 rst = 1;
768 }
769
770
771 if (why & QE_CR_STAT_LCOLL) {
772 printf("%s: late tx transmission\n", sc->sc_dev.dv_xname);
773 ifp->if_oerrors++;
774 r |= 1;
775 rst = 1;
776 }
777
778 if (why & QE_CR_STAT_FUFLOW) {
779 printf("%s: tx fifo underflow\n", sc->sc_dev.dv_xname);
780 ifp->if_oerrors++;
781 r |= 1;
782 rst = 1;
783 }
784
785 if (why & QE_CR_STAT_JERROR) {
786 printf("%s: jabber seen\n", sc->sc_dev.dv_xname);
787 r |= 1;
788 }
789
790 if (why & QE_CR_STAT_BERROR) {
791 printf("%s: babble seen\n", sc->sc_dev.dv_xname);
792 r |= 1;
793 }
794
795 if (why & QE_CR_STAT_TCCOFLOW) {
796 ifp->if_collisions += 256;
797 ifp->if_oerrors += 256;
798 r |= 1;
799 }
800
801 if (why & QE_CR_STAT_TXDERROR) {
802 printf("%s: tx descriptor is bad\n", sc->sc_dev.dv_xname);
803 rst = 1;
804 r |= 1;
805 }
806
807 if (why & QE_CR_STAT_TXLERR) {
808 printf("%s: tx late error\n", sc->sc_dev.dv_xname);
809 ifp->if_oerrors++;
810 rst = 1;
811 r |= 1;
812 }
813
814 if (why & QE_CR_STAT_TXPERR) {
815 printf("%s: tx dma parity error\n", sc->sc_dev.dv_xname);
816 ifp->if_oerrors++;
817 rst = 1;
818 r |= 1;
819 }
820
821 if (why & QE_CR_STAT_TXSERR) {
822 printf("%s: tx dma sbus error ack\n", sc->sc_dev.dv_xname);
823 ifp->if_oerrors++;
824 rst = 1;
825 r |= 1;
826 }
827
828 if (why & QE_CR_STAT_RCCOFLOW) {
829 ifp->if_collisions += 256;
830 ifp->if_ierrors += 256;
831 r |= 1;
832 }
833
834 if (why & QE_CR_STAT_RUOFLOW) {
835 ifp->if_ierrors += 256;
836 r |= 1;
837 }
838
839 if (why & QE_CR_STAT_MCOFLOW) {
840 ifp->if_ierrors += 256;
841 r |= 1;
842 }
843
844 if (why & QE_CR_STAT_RXFOFLOW) {
845 printf("%s: rx fifo overflow\n", sc->sc_dev.dv_xname);
846 ifp->if_ierrors++;
847 r |= 1;
848 }
849
850 if (why & QE_CR_STAT_RLCOLL) {
851 printf("%s: rx late collision\n", sc->sc_dev.dv_xname);
852 ifp->if_ierrors++;
853 ifp->if_collisions++;
854 r |= 1;
855 }
856
857 if (why & QE_CR_STAT_FCOFLOW) {
858 ifp->if_ierrors += 256;
859 r |= 1;
860 }
861
862 if (why & QE_CR_STAT_CECOFLOW) {
863 ifp->if_ierrors += 256;
864 r |= 1;
865 }
866
867 if (why & QE_CR_STAT_RXDROP) {
868 printf("%s: rx packet dropped\n", sc->sc_dev.dv_xname);
869 ifp->if_ierrors++;
870 r |= 1;
871 }
872
873 if (why & QE_CR_STAT_RXSMALL) {
874 printf("%s: rx buffer too small\n", sc->sc_dev.dv_xname);
875 ifp->if_ierrors++;
876 r |= 1;
877 rst = 1;
878 }
879
880 if (why & QE_CR_STAT_RXLERR) {
881 printf("%s: rx late error\n", sc->sc_dev.dv_xname);
882 ifp->if_ierrors++;
883 r |= 1;
884 rst = 1;
885 }
886
887 if (why & QE_CR_STAT_RXPERR) {
888 printf("%s: rx dma parity error\n", sc->sc_dev.dv_xname);
889 ifp->if_ierrors++;
890 r |= 1;
891 rst = 1;
892 }
893
894 if (why & QE_CR_STAT_RXSERR) {
895 printf("%s: rx dma sbus error ack\n", sc->sc_dev.dv_xname);
896 ifp->if_ierrors++;
897 r |= 1;
898 rst = 1;
899 }
900
901 if (r == 0)
902 printf("%s: unexpected interrupt error: %08x\n",
903 sc->sc_dev.dv_xname, why);
904
905 if (rst) {
906 printf("%s: resetting...\n", sc->sc_dev.dv_xname);
907 qereset(sc);
908 return (-1);
909 }
910
911 return (r);
912 }
913
914 int
qeioctl(ifp,cmd,data)915 qeioctl(ifp, cmd, data)
916 struct ifnet *ifp;
917 u_long cmd;
918 caddr_t data;
919 {
920 struct qe_softc *sc = ifp->if_softc;
921 struct ifaddr *ifa = (struct ifaddr *)data;
922 struct ifreq *ifr = (struct ifreq *)data;
923 int s, error = 0;
924
925 s = splnet();
926
927 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
928 splx(s);
929 return (error);
930 }
931
932 switch (cmd) {
933 case SIOCSIFADDR:
934 ifp->if_flags |= IFF_UP;
935 switch (ifa->ifa_addr->sa_family) {
936 #ifdef INET
937 case AF_INET:
938 qeinit(sc);
939 arp_ifinit(&sc->sc_arpcom, ifa);
940 break;
941 #endif /* INET */
942 #ifdef NS
943 case AF_NS:
944 {
945 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
946
947 if (ns_nullhost(*ina))
948 ina->x_host =
949 *(union ns_host *)LLADDR(ifp->if_sadl);
950 else
951 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
952 sizeof(sc->sc_arpcom.ac_enaddr));
953 /* Set new address. */
954 qeinit(sc);
955 break;
956 }
957 #endif /* NS */
958 default:
959 qeinit(sc);
960 break;
961 }
962 break;
963
964 case SIOCSIFFLAGS:
965 if ((ifp->if_flags & IFF_UP) == 0 &&
966 (ifp->if_flags & IFF_RUNNING) != 0) {
967 /*
968 * If interface is marked down and it is running, then
969 * stop it.
970 */
971 qestop(sc);
972 ifp->if_flags &= ~IFF_RUNNING;
973 } else if ((ifp->if_flags & IFF_UP) != 0 &&
974 (ifp->if_flags & IFF_RUNNING) == 0) {
975 /*
976 * If interface is marked up and it is stopped, then
977 * start it.
978 */
979 qeinit(sc);
980 } else {
981 /*
982 * Reset the interface to pick up changes in any other
983 * flags that affect hardware registers.
984 */
985 qestop(sc);
986 qeinit(sc);
987 }
988 #ifdef QEDEBUG
989 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
990 #endif
991 break;
992
993 case SIOCADDMULTI:
994 case SIOCDELMULTI:
995 error = (cmd == SIOCADDMULTI) ?
996 ether_addmulti(ifr, &sc->sc_arpcom):
997 ether_delmulti(ifr, &sc->sc_arpcom);
998
999 if (error == ENETRESET) {
1000 /*
1001 * Multicast list has changed; set the hardware filter
1002 * accordingly.
1003 */
1004 qe_mcreset(sc);
1005 error = 0;
1006 }
1007 break;
1008
1009 case SIOCGIFMEDIA:
1010 case SIOCSIFMEDIA:
1011 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd);
1012 break;
1013
1014 default:
1015 error = EINVAL;
1016 break;
1017 }
1018
1019 splx(s);
1020 return (error);
1021 }
1022
1023
1024 void
qeinit(sc)1025 qeinit(sc)
1026 struct qe_softc *sc;
1027 {
1028 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1029 bus_space_tag_t t = sc->sc_bustag;
1030 bus_space_handle_t cr = sc->sc_cr;
1031 bus_space_handle_t mr = sc->sc_mr;
1032 struct qec_softc *qec = sc->sc_qec;
1033 u_int32_t qecaddr;
1034 u_int8_t *ea;
1035 int s;
1036
1037 #if defined(SUN4U) || defined(__GNUC__)
1038 (void)&t;
1039 #endif
1040 s = splnet();
1041
1042 qestop(sc);
1043
1044 /*
1045 * Allocate descriptor ring and buffers
1046 */
1047 qec_meminit(&sc->sc_rb, QE_PKT_BUF_SZ);
1048
1049 /* Channel registers: */
1050 bus_space_write_4(t, cr, QE_CRI_RXDS, (u_int32_t)sc->sc_rb.rb_rxddma);
1051 bus_space_write_4(t, cr, QE_CRI_TXDS, (u_int32_t)sc->sc_rb.rb_txddma);
1052
1053 bus_space_write_4(t, cr, QE_CRI_RIMASK, 0);
1054 bus_space_write_4(t, cr, QE_CRI_TIMASK, 0);
1055 bus_space_write_4(t, cr, QE_CRI_QMASK, 0);
1056 bus_space_write_4(t, cr, QE_CRI_MMASK, QE_CR_MMASK_RXCOLL);
1057 bus_space_write_4(t, cr, QE_CRI_CCNT, 0);
1058 bus_space_write_4(t, cr, QE_CRI_PIPG, 0);
1059
1060 qecaddr = sc->sc_channel * qec->sc_msize;
1061 bus_space_write_4(t, cr, QE_CRI_RXWBUF, qecaddr);
1062 bus_space_write_4(t, cr, QE_CRI_RXRBUF, qecaddr);
1063 bus_space_write_4(t, cr, QE_CRI_TXWBUF, qecaddr + qec->sc_rsize);
1064 bus_space_write_4(t, cr, QE_CRI_TXRBUF, qecaddr + qec->sc_rsize);
1065
1066 /*
1067 * When switching from mace<->qec always guarantee an sbus
1068 * turnaround (if last op was read, perform a dummy write, and
1069 * vice versa).
1070 */
1071 bus_space_read_4(t, cr, QE_CRI_QMASK);
1072
1073 /* MACE registers: */
1074 bus_space_write_1(t, mr, QE_MRI_PHYCC, QE_MR_PHYCC_ASEL);
1075 bus_space_write_1(t, mr, QE_MRI_XMTFC, QE_MR_XMTFC_APADXMT);
1076 bus_space_write_1(t, mr, QE_MRI_RCVFC, 0);
1077
1078 /*
1079 * Mask MACE's receive interrupt, since we're being notified
1080 * by the QEC after DMA completes.
1081 */
1082 bus_space_write_1(t, mr, QE_MRI_IMR,
1083 QE_MR_IMR_CERRM | QE_MR_IMR_RCVINTM);
1084
1085 bus_space_write_1(t, mr, QE_MRI_BIUCC,
1086 QE_MR_BIUCC_BSWAP | QE_MR_BIUCC_64TS);
1087
1088 bus_space_write_1(t, mr, QE_MRI_FIFOFC,
1089 QE_MR_FIFOCC_TXF16 | QE_MR_FIFOCC_RXF32 |
1090 QE_MR_FIFOCC_RFWU | QE_MR_FIFOCC_TFWU);
1091
1092 bus_space_write_1(t, mr, QE_MRI_PLSCC, QE_MR_PLSCC_TP);
1093
1094 /*
1095 * Station address
1096 */
1097 ea = sc->sc_arpcom.ac_enaddr;
1098 bus_space_write_1(t, mr, QE_MRI_IAC,
1099 QE_MR_IAC_ADDRCHG | QE_MR_IAC_PHYADDR);
1100 bus_space_write_multi_1(t, mr, QE_MRI_PADR, ea, 6);
1101
1102 /* Apply media settings */
1103 qe_ifmedia_upd(ifp);
1104
1105 /*
1106 * Clear Logical address filter
1107 */
1108 bus_space_write_1(t, mr, QE_MRI_IAC,
1109 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1110 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0, 8);
1111 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1112
1113 /* Clear missed packet count (register cleared on read) */
1114 (void)bus_space_read_1(t, mr, QE_MRI_MPC);
1115
1116 #if 0
1117 /* test register: */
1118 bus_space_write_1(t, mr, QE_MRI_UTR, 0);
1119 #endif
1120
1121 /* Reset multicast filter */
1122 qe_mcreset(sc);
1123
1124 ifp->if_flags |= IFF_RUNNING;
1125 ifp->if_flags &= ~IFF_OACTIVE;
1126 splx(s);
1127 }
1128
1129 /*
1130 * Reset multicast filter.
1131 */
1132 void
qe_mcreset(sc)1133 qe_mcreset(sc)
1134 struct qe_softc *sc;
1135 {
1136 struct arpcom *ac = &sc->sc_arpcom;
1137 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1138 bus_space_tag_t t = sc->sc_bustag;
1139 bus_space_handle_t mr = sc->sc_mr;
1140 struct ether_multi *enm;
1141 struct ether_multistep step;
1142 u_int32_t crc;
1143 u_int16_t hash[4];
1144 u_int8_t octet, maccc, *ladrp = (u_int8_t *)&hash[0];
1145 int i, j;
1146
1147 #if defined(SUN4U) || defined(__GNUC__)
1148 (void)&t;
1149 #endif
1150
1151 /* We also enable transmitter & receiver here */
1152 maccc = QE_MR_MACCC_ENXMT | QE_MR_MACCC_ENRCV;
1153
1154 if (ifp->if_flags & IFF_PROMISC) {
1155 maccc |= QE_MR_MACCC_PROM;
1156 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1157 return;
1158 }
1159
1160 if (ifp->if_flags & IFF_ALLMULTI) {
1161 bus_space_write_1(t, mr, QE_MRI_IAC,
1162 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1163 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
1164 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1165 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1166 return;
1167 }
1168
1169 hash[3] = hash[2] = hash[1] = hash[0] = 0;
1170
1171 ETHER_FIRST_MULTI(step, ac, enm);
1172 while (enm != NULL) {
1173 if (bcmp(enm->enm_addrlo, enm->enm_addrhi,
1174 ETHER_ADDR_LEN) != 0) {
1175 /*
1176 * We must listen to a range of multicast
1177 * addresses. For now, just accept all
1178 * multicasts, rather than trying to set only
1179 * those filter bits needed to match the range.
1180 * (At this time, the only use of address
1181 * ranges is for IP multicast routing, for
1182 * which the range is big enough to require
1183 * all bits set.)
1184 */
1185 bus_space_write_1(t, mr, QE_MRI_IAC,
1186 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1187 bus_space_set_multi_1(t, mr, QE_MRI_LADRF, 0xff, 8);
1188 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1189 ifp->if_flags |= IFF_ALLMULTI;
1190 break;
1191 }
1192
1193 crc = 0xffffffff;
1194
1195 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1196 octet = enm->enm_addrlo[i];
1197
1198 for (j = 0; j < 8; j++) {
1199 if ((crc & 1) ^ (octet & 1)) {
1200 crc >>= 1;
1201 crc ^= MC_POLY_LE;
1202 }
1203 else
1204 crc >>= 1;
1205 octet >>= 1;
1206 }
1207 }
1208
1209 crc >>= 26;
1210 hash[crc >> 4] |= 1 << (crc & 0xf);
1211 ETHER_NEXT_MULTI(step, enm);
1212 }
1213
1214 bus_space_write_1(t, mr, QE_MRI_IAC,
1215 QE_MR_IAC_ADDRCHG | QE_MR_IAC_LOGADDR);
1216 bus_space_write_multi_1(t, mr, QE_MRI_LADRF, ladrp, 8);
1217 bus_space_write_1(t, mr, QE_MRI_IAC, 0);
1218 bus_space_write_1(t, mr, QE_MRI_MACCC, maccc);
1219 }
1220
1221 /*
1222 * Get current media settings.
1223 */
1224 void
qe_ifmedia_sts(ifp,ifmr)1225 qe_ifmedia_sts(ifp, ifmr)
1226 struct ifnet *ifp;
1227 struct ifmediareq *ifmr;
1228 {
1229 struct qe_softc *sc = ifp->if_softc;
1230 u_int8_t phycc;
1231
1232 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1233 phycc = bus_space_read_1(sc->sc_bustag, sc->sc_mr, QE_MRI_PHYCC);
1234 if ((phycc & QE_MR_PHYCC_DLNKTST) == 0) {
1235 ifmr->ifm_status |= IFM_AVALID;
1236 if (phycc & QE_MR_PHYCC_LNKFL)
1237 ifmr->ifm_status &= ~IFM_ACTIVE;
1238 else
1239 ifmr->ifm_status |= IFM_ACTIVE;
1240 }
1241 }
1242
1243 /*
1244 * Set media options.
1245 */
1246 int
qe_ifmedia_upd(ifp)1247 qe_ifmedia_upd(ifp)
1248 struct ifnet *ifp;
1249 {
1250 struct qe_softc *sc = ifp->if_softc;
1251 int media = sc->sc_ifmedia.ifm_media;
1252
1253 if (IFM_TYPE(media) != IFM_ETHER)
1254 return (EINVAL);
1255
1256 if (IFM_SUBTYPE(media) != IFM_10_T)
1257 return (EINVAL);
1258
1259 return (0);
1260 }
1261