1 /** $MirOS: src/sys/dev/pci/ubsec.c,v 1.3 2011/11/20 18:54:48 tg Exp $ */
2 /* $OpenBSD: ubsec.c,v 1.135 2004/05/07 14:42:26 millert Exp $ */
3
4 /*
5 * Copyright (c) 2000 Jason L. Wright (jason@thought.net)
6 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org)
7 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com)
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 *
30 * Effort sponsored in part by the Defense Advanced Research Projects
31 * Agency (DARPA) and Air Force Research Laboratory, Air Force
32 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
33 *
34 */
35
36 #undef UBSEC_DEBUG
37
38 /*
39 * uBsec 5[56]01, 58xx hardware crypto accelerator
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/proc.h>
45 #include <sys/errno.h>
46 #include <sys/malloc.h>
47 #include <sys/kernel.h>
48 #include <sys/mbuf.h>
49 #include <sys/device.h>
50 #include <sys/queue.h>
51
52 #include <crypto/cryptodev.h>
53 #include <crypto/cryptosoft.h>
54 #include <dev/rndvar.h>
55 #include <syskern/md5.h>
56 #include <crypto/sha1.h>
57
58 #include <dev/pci/pcireg.h>
59 #include <dev/pci/pcivar.h>
60 #include <dev/pci/pcidevs.h>
61
62 #include <dev/pci/ubsecreg.h>
63 #include <dev/pci/ubsecvar.h>
64
65 /*
66 * Prototypes and count for the pci_device structure
67 */
68 int ubsec_probe(struct device *, void *, void *);
69 void ubsec_attach(struct device *, struct device *, void *);
70 void ubsec_reset_board(struct ubsec_softc *);
71 void ubsec_init_board(struct ubsec_softc *);
72 void ubsec_init_pciregs(struct pci_attach_args *pa);
73 void ubsec_cleanchip(struct ubsec_softc *);
74 void ubsec_totalreset(struct ubsec_softc *);
75 int ubsec_free_q(struct ubsec_softc*, struct ubsec_q *);
76
77 struct cfattach ubsec_ca = {
78 sizeof(struct ubsec_softc), ubsec_probe, ubsec_attach,
79 };
80
81 struct cfdriver ubsec_cd = {
82 0, "ubsec", DV_DULL
83 };
84
85 int ubsec_intr(void *);
86 int ubsec_newsession(u_int32_t *, struct cryptoini *);
87 int ubsec_freesession(u_int64_t);
88 int ubsec_process(struct cryptop *);
89 void ubsec_callback(struct ubsec_softc *, struct ubsec_q *);
90 void ubsec_feed(struct ubsec_softc *);
91 void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int);
92 void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *);
93 void ubsec_feed2(struct ubsec_softc *);
94 void ubsec_rng(void *);
95 int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t,
96 struct ubsec_dma_alloc *, int);
97 void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *);
98 int ubsec_dmamap_aligned(bus_dmamap_t);
99
100 int ubsec_kprocess(struct cryptkop *);
101 struct ubsec_softc *ubsec_kfind(struct cryptkop *);
102 int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *);
103 int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *);
104 int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *);
105 void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *);
106 int ubsec_ksigbits(struct crparam *);
107 void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
108 void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int);
109
110 /* DEBUG crap... */
111 void ubsec_dump_pb(struct ubsec_pktbuf *);
112 void ubsec_dump_mcr(struct ubsec_mcr *);
113 void ubsec_dump_ctx2(struct ubsec_ctx_keyop *);
114
115 #define READ_REG(sc,r) \
116 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r))
117
118 #define WRITE_REG(sc,reg,val) \
119 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val)
120
121 #define SWAP32(x) (x) = htole32(ntohl((x)))
122
123
124 struct ubsec_stats ubsecstats;
125
126 const struct pci_matchid ubsec_devices[] = {
127 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5501 },
128 { PCI_VENDOR_BLUESTEEL, PCI_PRODUCT_BLUESTEEL_5601 },
129 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5801 },
130 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5802 },
131 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5805 },
132 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5820 },
133 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5821 },
134 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5822 },
135 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_5823 },
136 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_SCA1K },
137 { PCI_VENDOR_SUN, PCI_PRODUCT_SUN_5821 },
138 };
139
140 int
ubsec_probe(struct device * parent,void * match,void * aux)141 ubsec_probe(struct device *parent, void *match, void *aux)
142 {
143 return (pci_matchbyid((struct pci_attach_args *)aux, ubsec_devices,
144 sizeof(ubsec_devices)/sizeof(ubsec_devices[0])));
145 }
146
147 void
ubsec_attach(struct device * parent,struct device * self,void * aux)148 ubsec_attach(struct device *parent, struct device *self, void *aux)
149 {
150 struct ubsec_softc *sc = (struct ubsec_softc *)self;
151 struct pci_attach_args *pa = aux;
152 pci_chipset_tag_t pc = pa->pa_pc;
153 pci_intr_handle_t ih;
154 const char *intrstr = NULL;
155 struct ubsec_dma *dmap;
156 bus_size_t iosize;
157 u_int32_t cmd, i;
158 int algs[CRYPTO_ALGORITHM_MAX + 1];
159 int kalgs[CRK_ALGORITHM_MAX + 1];
160
161 SIMPLEQ_INIT(&sc->sc_queue);
162 SIMPLEQ_INIT(&sc->sc_qchip);
163 SIMPLEQ_INIT(&sc->sc_queue2);
164 SIMPLEQ_INIT(&sc->sc_qchip2);
165 SIMPLEQ_INIT(&sc->sc_q2free);
166
167 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR;
168
169 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BLUESTEEL &&
170 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BLUESTEEL_5601)
171 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
172
173 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
174 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5802 ||
175 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5805))
176 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG;
177
178 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
179 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5820 ||
180 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5822 ||
181 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5823))
182 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
183 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
184
185 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_BROADCOM &&
186 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_BROADCOM_5821) ||
187 (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SUN &&
188 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_SCA1K ||
189 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SUN_5821))) {
190 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY |
191 BS_STAT_MCR2_ALLEMPTY;
192 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG |
193 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY;
194 }
195
196 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
197 cmd |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE;
198 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, cmd);
199 cmd = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
200
201 if (!(cmd & PCI_COMMAND_MEM_ENABLE)) {
202 printf(": failed to enable memory mapping\n");
203 return;
204 }
205
206 if (!(cmd & PCI_COMMAND_MASTER_ENABLE)) {
207 printf(": failed to enable bus mastering\n");
208 return;
209 }
210
211 if (pci_mapreg_map(pa, BS_BAR, PCI_MAPREG_TYPE_MEM, 0,
212 &sc->sc_st, &sc->sc_sh, NULL, &iosize, 0)) {
213 printf(": can't find mem space\n");
214 return;
215 }
216 sc->sc_dmat = pa->pa_dmat;
217
218 if (pci_intr_map(pa, &ih)) {
219 printf(": couldn't map interrupt\n");
220 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize);
221 return;
222 }
223 intrstr = pci_intr_string(pc, ih);
224 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, ubsec_intr, sc,
225 self->dv_xname);
226 if (sc->sc_ih == NULL) {
227 printf(": couldn't establish interrupt");
228 if (intrstr != NULL)
229 printf(" at %s", intrstr);
230 printf("\n");
231 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize);
232 return;
233 }
234
235 sc->sc_cid = crypto_get_driverid(0);
236 if (sc->sc_cid < 0) {
237 pci_intr_disestablish(pc, sc->sc_ih);
238 bus_space_unmap(sc->sc_st, sc->sc_sh, iosize);
239 return;
240 }
241
242 SIMPLEQ_INIT(&sc->sc_freequeue);
243 dmap = sc->sc_dmaa;
244 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) {
245 struct ubsec_q *q;
246
247 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q),
248 M_DEVBUF, M_NOWAIT);
249 if (q == NULL) {
250 printf(": can't allocate queue buffers\n");
251 break;
252 }
253
254 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk),
255 &dmap->d_alloc, 0)) {
256 printf(": can't allocate dma buffers\n");
257 free(q, M_DEVBUF);
258 break;
259 }
260 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr;
261
262 q->q_dma = dmap;
263 sc->sc_queuea[i] = q;
264
265 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
266 }
267
268 bzero(algs, sizeof(algs));
269 algs[CRYPTO_3DES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED;
270 algs[CRYPTO_DES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED;
271 algs[CRYPTO_MD5_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
272 algs[CRYPTO_SHA1_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED;
273 crypto_register(sc->sc_cid, algs, ubsec_newsession,
274 ubsec_freesession, ubsec_process);
275
276 /*
277 * Reset Broadcom chip
278 */
279 ubsec_reset_board(sc);
280
281 /*
282 * Init Broadcom specific PCI settings
283 */
284 ubsec_init_pciregs(pa);
285
286 /*
287 * Init Broadcom chip
288 */
289 ubsec_init_board(sc);
290
291 printf(": 3DES MD5 SHA1");
292
293 #ifndef UBSEC_NO_RNG
294 if (sc->sc_flags & UBS_FLAGS_RNG) {
295 sc->sc_statmask |= BS_STAT_MCR2_DONE;
296
297 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
298 &sc->sc_rng.rng_q.q_mcr, 0))
299 goto skip_rng;
300
301 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass),
302 &sc->sc_rng.rng_q.q_ctx, 0)) {
303 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
304 goto skip_rng;
305 }
306
307 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) *
308 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) {
309 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx);
310 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr);
311 goto skip_rng;
312 }
313
314 timeout_set(&sc->sc_rngto, ubsec_rng, sc);
315 if (hz >= 100)
316 sc->sc_rnghz = hz / 100;
317 else
318 sc->sc_rnghz = 1;
319 timeout_add(&sc->sc_rngto, sc->sc_rnghz);
320 printf(" RNG");
321 skip_rng:
322 ;
323 }
324 #endif /* UBSEC_NO_RNG */
325
326 if (sc->sc_flags & UBS_FLAGS_KEY) {
327 sc->sc_statmask |= BS_STAT_MCR2_DONE;
328
329 bzero(kalgs, sizeof(kalgs));
330 kalgs[CRK_MOD_EXP] = CRYPTO_ALG_FLAG_SUPPORTED;
331 #if 0
332 kalgs[CRK_MOD_EXP_CRT] = CRYPTO_ALG_FLAG_SUPPORTED;
333 #endif
334
335 crypto_kregister(sc->sc_cid, kalgs, ubsec_kprocess);
336 printf(" PK");
337 }
338
339 printf(", %s\n", intrstr);
340 }
341
342 /*
343 * UBSEC Interrupt routine
344 */
345 int
ubsec_intr(void * arg)346 ubsec_intr(void *arg)
347 {
348 struct ubsec_softc *sc = arg;
349 volatile u_int32_t stat;
350 struct ubsec_q *q;
351 struct ubsec_dma *dmap;
352 int npkts = 0, i;
353
354 stat = READ_REG(sc, BS_STAT);
355
356 stat &= sc->sc_statmask;
357 if (stat == 0)
358 return (0);
359
360 WRITE_REG(sc, BS_STAT, stat); /* IACK */
361
362 /*
363 * Check to see if we have any packets waiting for us
364 */
365 if ((stat & BS_STAT_MCR1_DONE)) {
366 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
367 q = SIMPLEQ_FIRST(&sc->sc_qchip);
368 dmap = q->q_dma;
369
370 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0)
371 break;
372
373 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
374
375 npkts = q->q_nstacked_mcrs;
376 /*
377 * search for further sc_qchip ubsec_q's that share
378 * the same MCR, and complete them too, they must be
379 * at the top.
380 */
381 for (i = 0; i < npkts; i++) {
382 if(q->q_stacked_mcr[i])
383 ubsec_callback(sc, q->q_stacked_mcr[i]);
384 else
385 break;
386 }
387 ubsec_callback(sc, q);
388 }
389
390 /*
391 * Don't send any more packet to chip if there has been
392 * a DMAERR.
393 */
394 if (!(stat & BS_STAT_DMAERR))
395 ubsec_feed(sc);
396 }
397
398 /*
399 * Check to see if we have any key setups/rng's waiting for us
400 */
401 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) &&
402 (stat & BS_STAT_MCR2_DONE)) {
403 struct ubsec_q2 *q2;
404 struct ubsec_mcr *mcr;
405
406 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) {
407 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2);
408
409 bus_dmamap_sync(sc->sc_dmat, q2->q_mcr.dma_map,
410 0, q2->q_mcr.dma_map->dm_mapsize,
411 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
412
413 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr;
414 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) {
415 bus_dmamap_sync(sc->sc_dmat,
416 q2->q_mcr.dma_map, 0,
417 q2->q_mcr.dma_map->dm_mapsize,
418 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
419 break;
420 }
421 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next);
422 ubsec_callback2(sc, q2);
423 /*
424 * Don't send any more packet to chip if there has been
425 * a DMAERR.
426 */
427 if (!(stat & BS_STAT_DMAERR))
428 ubsec_feed2(sc);
429 }
430 }
431
432 /*
433 * Check to see if we got any DMA Error
434 */
435 if (stat & BS_STAT_DMAERR) {
436 #ifdef UBSEC_DEBUG
437 volatile u_int32_t a = READ_REG(sc, BS_ERR);
438
439 printf("%s: dmaerr %s@%08x\n", sc->sc_dv.dv_xname,
440 (a & BS_ERR_READ) ? "read" : "write", a & BS_ERR_ADDR);
441 #endif /* UBSEC_DEBUG */
442 ubsecstats.hst_dmaerr++;
443 ubsec_totalreset(sc);
444 ubsec_feed(sc);
445 }
446
447 return (1);
448 }
449
450 /*
451 * ubsec_feed() - aggregate and post requests to chip
452 * It is assumed that the caller set splnet()
453 */
454 void
ubsec_feed(struct ubsec_softc * sc)455 ubsec_feed(struct ubsec_softc *sc)
456 {
457 #ifdef UBSEC_DEBUG
458 static int max;
459 #endif /* UBSEC_DEBUG */
460 struct ubsec_q *q, *q2;
461 int npkts, i;
462 void *v;
463 u_int32_t stat;
464
465 npkts = sc->sc_nqueue;
466 if (npkts > UBS_MAX_AGGR)
467 npkts = UBS_MAX_AGGR;
468 if (npkts < 2)
469 goto feed1;
470
471 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
472 if(stat & BS_STAT_DMAERR) {
473 ubsec_totalreset(sc);
474 ubsecstats.hst_dmaerr++;
475 }
476 return;
477 }
478
479 #ifdef UBSEC_DEBUG
480 printf("merging %d records\n", npkts);
481
482 /* XXX temporary aggregation statistics reporting code */
483 if (max < npkts) {
484 max = npkts;
485 printf("%s: new max aggregate %d\n", sc->sc_dv.dv_xname, max);
486 }
487 #endif /* UBSEC_DEBUG */
488
489 q = SIMPLEQ_FIRST(&sc->sc_queue);
490 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
491 --sc->sc_nqueue;
492
493 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
494 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
495 if (q->q_dst_map != NULL)
496 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
497 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
498
499 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */
500
501 for (i = 0; i < q->q_nstacked_mcrs; i++) {
502 q2 = SIMPLEQ_FIRST(&sc->sc_queue);
503 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map,
504 0, q2->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
505 if (q2->q_dst_map != NULL)
506 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map,
507 0, q2->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
508 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
509 --sc->sc_nqueue;
510
511 v = ((void *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) -
512 sizeof(struct ubsec_mcr_add);
513 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add));
514 q->q_stacked_mcr[i] = q2;
515 }
516 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts);
517 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
518 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
519 0, q->q_dma->d_alloc.dma_map->dm_mapsize,
520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
521 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
522 offsetof(struct ubsec_dmachunk, d_mcr));
523 return;
524
525 feed1:
526 while (!SIMPLEQ_EMPTY(&sc->sc_queue)) {
527 if ((stat = READ_REG(sc, BS_STAT)) &
528 (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) {
529 if(stat & BS_STAT_DMAERR) {
530 ubsec_totalreset(sc);
531 ubsecstats.hst_dmaerr++;
532 }
533 break;
534 }
535
536 q = SIMPLEQ_FIRST(&sc->sc_queue);
537
538 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
539 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
540 if (q->q_dst_map != NULL)
541 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
542 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_PREREAD);
543 bus_dmamap_sync(sc->sc_dmat, q->q_dma->d_alloc.dma_map,
544 0, q->q_dma->d_alloc.dma_map->dm_mapsize,
545 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
546
547 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr +
548 offsetof(struct ubsec_dmachunk, d_mcr));
549 #ifdef UBSEC_DEBUG
550 printf("feed: q->chip %p %08x\n", q,
551 (u_int32_t)q->q_dma->d_alloc.dma_paddr);
552 #endif /* UBSEC_DEBUG */
553 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next);
554 --sc->sc_nqueue;
555 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next);
556 }
557 }
558
559 /*
560 * Allocate a new 'session' and return an encoded session id. 'sidp'
561 * contains our registration id, and should contain an encoded session
562 * id on successful allocation.
563 */
564 int
ubsec_newsession(u_int32_t * sidp,struct cryptoini * cri)565 ubsec_newsession(u_int32_t *sidp, struct cryptoini *cri)
566 {
567 struct cryptoini *c, *encini = NULL, *macini = NULL;
568 struct ubsec_softc *sc = NULL;
569 struct ubsec_session *ses = NULL;
570 MD5_CTX md5ctx;
571 SHA1_CTX sha1ctx;
572 int i, sesn;
573
574 if (sidp == NULL || cri == NULL)
575 return (EINVAL);
576
577 for (i = 0; i < ubsec_cd.cd_ndevs; i++) {
578 sc = ubsec_cd.cd_devs[i];
579 if (sc == NULL || sc->sc_cid == (*sidp))
580 break;
581 }
582 if (sc == NULL)
583 return (EINVAL);
584
585 for (c = cri; c != NULL; c = c->cri_next) {
586 if (c->cri_alg == CRYPTO_MD5_HMAC ||
587 c->cri_alg == CRYPTO_SHA1_HMAC) {
588 if (macini)
589 return (EINVAL);
590 macini = c;
591 } else if (c->cri_alg == CRYPTO_DES_CBC ||
592 c->cri_alg == CRYPTO_3DES_CBC) {
593 if (encini)
594 return (EINVAL);
595 encini = c;
596 } else
597 return (EINVAL);
598 }
599 if (encini == NULL && macini == NULL)
600 return (EINVAL);
601
602 if (sc->sc_sessions == NULL) {
603 ses = sc->sc_sessions = (struct ubsec_session *)malloc(
604 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
605 if (ses == NULL)
606 return (ENOMEM);
607 sesn = 0;
608 sc->sc_nsessions = 1;
609 } else {
610 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
611 if (sc->sc_sessions[sesn].ses_used == 0) {
612 ses = &sc->sc_sessions[sesn];
613 break;
614 }
615 }
616
617 if (ses == NULL) {
618 sesn = sc->sc_nsessions;
619 ses = (struct ubsec_session *)malloc((sesn + 1) *
620 sizeof(struct ubsec_session), M_DEVBUF, M_NOWAIT);
621 if (ses == NULL)
622 return (ENOMEM);
623 bcopy(sc->sc_sessions, ses, sesn *
624 sizeof(struct ubsec_session));
625 bzero(sc->sc_sessions, sesn *
626 sizeof(struct ubsec_session));
627 free(sc->sc_sessions, M_DEVBUF);
628 sc->sc_sessions = ses;
629 ses = &sc->sc_sessions[sesn];
630 sc->sc_nsessions++;
631 }
632 }
633
634 bzero(ses, sizeof(struct ubsec_session));
635 ses->ses_used = 1;
636 if (encini) {
637 /* get an IV, network byte order */
638 get_random_bytes(ses->ses_iv, sizeof(ses->ses_iv));
639
640 /* Go ahead and compute key in ubsec's byte order */
641 if (encini->cri_alg == CRYPTO_DES_CBC) {
642 bcopy(encini->cri_key, &ses->ses_deskey[0], 8);
643 bcopy(encini->cri_key, &ses->ses_deskey[2], 8);
644 bcopy(encini->cri_key, &ses->ses_deskey[4], 8);
645 } else
646 bcopy(encini->cri_key, ses->ses_deskey, 24);
647
648 SWAP32(ses->ses_deskey[0]);
649 SWAP32(ses->ses_deskey[1]);
650 SWAP32(ses->ses_deskey[2]);
651 SWAP32(ses->ses_deskey[3]);
652 SWAP32(ses->ses_deskey[4]);
653 SWAP32(ses->ses_deskey[5]);
654 }
655
656 if (macini) {
657 for (i = 0; i < macini->cri_klen / 8; i++)
658 macini->cri_key[i] ^= HMAC_IPAD_VAL;
659
660 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
661 MD5Init(&md5ctx);
662 MD5Update(&md5ctx, macini->cri_key,
663 macini->cri_klen / 8);
664 MD5Update(&md5ctx, hmac_ipad_buffer,
665 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
666 bcopy(md5ctx.state, ses->ses_hminner,
667 sizeof(md5ctx.state));
668 } else {
669 SHA1Init(&sha1ctx);
670 SHA1Update(&sha1ctx, macini->cri_key,
671 macini->cri_klen / 8);
672 SHA1Update(&sha1ctx, hmac_ipad_buffer,
673 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
674 bcopy(sha1ctx.state, ses->ses_hminner,
675 sizeof(sha1ctx.state));
676 }
677
678 for (i = 0; i < macini->cri_klen / 8; i++)
679 macini->cri_key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL);
680
681 if (macini->cri_alg == CRYPTO_MD5_HMAC) {
682 MD5Init(&md5ctx);
683 MD5Update(&md5ctx, macini->cri_key,
684 macini->cri_klen / 8);
685 MD5Update(&md5ctx, hmac_opad_buffer,
686 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
687 bcopy(md5ctx.state, ses->ses_hmouter,
688 sizeof(md5ctx.state));
689 } else {
690 SHA1Init(&sha1ctx);
691 SHA1Update(&sha1ctx, macini->cri_key,
692 macini->cri_klen / 8);
693 SHA1Update(&sha1ctx, hmac_opad_buffer,
694 HMAC_BLOCK_LEN - (macini->cri_klen / 8));
695 bcopy(sha1ctx.state, ses->ses_hmouter,
696 sizeof(sha1ctx.state));
697 }
698
699 for (i = 0; i < macini->cri_klen / 8; i++)
700 macini->cri_key[i] ^= HMAC_OPAD_VAL;
701 }
702
703 *sidp = UBSEC_SID(sc->sc_dv.dv_unit, sesn);
704 return (0);
705 }
706
707 /*
708 * Deallocate a session.
709 */
710 int
ubsec_freesession(u_int64_t tid)711 ubsec_freesession(u_int64_t tid)
712 {
713 struct ubsec_softc *sc;
714 int card, session;
715 u_int32_t sid = ((u_int32_t)tid) & 0xffffffff;
716
717 card = UBSEC_CARD(sid);
718 if (card >= ubsec_cd.cd_ndevs || ubsec_cd.cd_devs[card] == NULL)
719 return (EINVAL);
720 sc = ubsec_cd.cd_devs[card];
721 session = UBSEC_SESSION(sid);
722 bzero(&sc->sc_sessions[session], sizeof(sc->sc_sessions[session]));
723 return (0);
724 }
725
726 int
ubsec_process(struct cryptop * crp)727 ubsec_process(struct cryptop *crp)
728 {
729 struct ubsec_q *q = NULL;
730 int card, err = 0, i, j, s, nicealign;
731 struct ubsec_softc *sc;
732 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
733 int encoffset = 0, macoffset = 0, cpskip, cpoffset;
734 int sskip, dskip, stheend, dtheend;
735 int16_t coffset;
736 struct ubsec_session *ses;
737 struct ubsec_pktctx ctx;
738 struct ubsec_dma *dmap = NULL;
739
740 if (crp == NULL || crp->crp_callback == NULL) {
741 ubsecstats.hst_invalid++;
742 return (EINVAL);
743 }
744 card = UBSEC_CARD(crp->crp_sid);
745 if (card >= ubsec_cd.cd_ndevs || ubsec_cd.cd_devs[card] == NULL) {
746 ubsecstats.hst_invalid++;
747 return (EINVAL);
748 }
749
750 sc = ubsec_cd.cd_devs[card];
751
752 s = splnet();
753
754 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) {
755 ubsecstats.hst_queuefull++;
756 splx(s);
757 err = ENOMEM;
758 goto errout2;
759 }
760
761 q = SIMPLEQ_FIRST(&sc->sc_freequeue);
762 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next);
763 splx(s);
764
765 dmap = q->q_dma; /* Save dma pointer */
766 bzero(q, sizeof(struct ubsec_q));
767 bzero(&ctx, sizeof(ctx));
768
769 q->q_sesn = UBSEC_SESSION(crp->crp_sid);
770 q->q_dma = dmap;
771 ses = &sc->sc_sessions[q->q_sesn];
772
773 if (crp->crp_flags & CRYPTO_F_IMBUF) {
774 q->q_src_m = (struct mbuf *)crp->crp_buf;
775 q->q_dst_m = (struct mbuf *)crp->crp_buf;
776 } else if (crp->crp_flags & CRYPTO_F_IOV) {
777 q->q_src_io = (struct uio *)crp->crp_buf;
778 q->q_dst_io = (struct uio *)crp->crp_buf;
779 } else {
780 err = EINVAL;
781 goto errout; /* XXX we don't handle contiguous blocks! */
782 }
783
784 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr));
785
786 dmap->d_dma->d_mcr.mcr_pkts = htole16(1);
787 dmap->d_dma->d_mcr.mcr_flags = 0;
788 q->q_crp = crp;
789
790 crd1 = crp->crp_desc;
791 if (crd1 == NULL) {
792 err = EINVAL;
793 goto errout;
794 }
795 crd2 = crd1->crd_next;
796
797 if (crd2 == NULL) {
798 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
799 crd1->crd_alg == CRYPTO_SHA1_HMAC) {
800 maccrd = crd1;
801 enccrd = NULL;
802 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
803 crd1->crd_alg == CRYPTO_3DES_CBC) {
804 maccrd = NULL;
805 enccrd = crd1;
806 } else {
807 err = EINVAL;
808 goto errout;
809 }
810 } else {
811 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
812 crd1->crd_alg == CRYPTO_SHA1_HMAC) &&
813 (crd2->crd_alg == CRYPTO_DES_CBC ||
814 crd2->crd_alg == CRYPTO_3DES_CBC) &&
815 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
816 maccrd = crd1;
817 enccrd = crd2;
818 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
819 crd1->crd_alg == CRYPTO_3DES_CBC) &&
820 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
821 crd2->crd_alg == CRYPTO_SHA1_HMAC) &&
822 (crd1->crd_flags & CRD_F_ENCRYPT)) {
823 enccrd = crd1;
824 maccrd = crd2;
825 } else {
826 /*
827 * We cannot order the ubsec as requested
828 */
829 err = EINVAL;
830 goto errout;
831 }
832 }
833
834 if (enccrd) {
835 encoffset = enccrd->crd_skip;
836 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES);
837
838 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
839 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV;
840
841 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
842 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
843 else {
844 ctx.pc_iv[0] = ses->ses_iv[0];
845 ctx.pc_iv[1] = ses->ses_iv[1];
846 }
847
848 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) {
849 if (crp->crp_flags & CRYPTO_F_IMBUF)
850 m_copyback(q->q_src_m,
851 enccrd->crd_inject,
852 8, ctx.pc_iv);
853 else if (crp->crp_flags & CRYPTO_F_IOV)
854 cuio_copyback(q->q_src_io,
855 enccrd->crd_inject,
856 8, ctx.pc_iv);
857 }
858 } else {
859 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND);
860
861 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
862 bcopy(enccrd->crd_iv, ctx.pc_iv, 8);
863 else if (crp->crp_flags & CRYPTO_F_IMBUF)
864 m_copydata(q->q_src_m, enccrd->crd_inject,
865 8, (caddr_t)ctx.pc_iv);
866 else if (crp->crp_flags & CRYPTO_F_IOV)
867 cuio_copydata(q->q_src_io,
868 enccrd->crd_inject, 8,
869 (caddr_t)ctx.pc_iv);
870 }
871
872 ctx.pc_deskey[0] = ses->ses_deskey[0];
873 ctx.pc_deskey[1] = ses->ses_deskey[1];
874 ctx.pc_deskey[2] = ses->ses_deskey[2];
875 ctx.pc_deskey[3] = ses->ses_deskey[3];
876 ctx.pc_deskey[4] = ses->ses_deskey[4];
877 ctx.pc_deskey[5] = ses->ses_deskey[5];
878 SWAP32(ctx.pc_iv[0]);
879 SWAP32(ctx.pc_iv[1]);
880 }
881
882 if (maccrd) {
883 macoffset = maccrd->crd_skip;
884
885 if (maccrd->crd_alg == CRYPTO_MD5_HMAC)
886 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5);
887 else
888 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1);
889
890 for (i = 0; i < 5; i++) {
891 ctx.pc_hminner[i] = ses->ses_hminner[i];
892 ctx.pc_hmouter[i] = ses->ses_hmouter[i];
893
894 HTOLE32(ctx.pc_hminner[i]);
895 HTOLE32(ctx.pc_hmouter[i]);
896 }
897 }
898
899 if (enccrd && maccrd) {
900 /*
901 * ubsec cannot handle packets where the end of encryption
902 * and authentication are not the same, or where the
903 * encrypted part begins before the authenticated part.
904 */
905 if (((encoffset + enccrd->crd_len) !=
906 (macoffset + maccrd->crd_len)) ||
907 (enccrd->crd_skip < maccrd->crd_skip)) {
908 err = EINVAL;
909 goto errout;
910 }
911 sskip = maccrd->crd_skip;
912 cpskip = dskip = enccrd->crd_skip;
913 stheend = maccrd->crd_len;
914 dtheend = enccrd->crd_len;
915 coffset = enccrd->crd_skip - maccrd->crd_skip;
916 cpoffset = cpskip + dtheend;
917 #ifdef UBSEC_DEBUG
918 printf("mac: skip %d, len %d, inject %d\n",
919 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject);
920 printf("enc: skip %d, len %d, inject %d\n",
921 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject);
922 printf("src: skip %d, len %d\n", sskip, stheend);
923 printf("dst: skip %d, len %d\n", dskip, dtheend);
924 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n",
925 coffset, stheend, cpskip, cpoffset);
926 #endif
927 } else {
928 cpskip = dskip = sskip = macoffset + encoffset;
929 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len;
930 cpoffset = cpskip + dtheend;
931 coffset = 0;
932 }
933 ctx.pc_offset = htole16(coffset >> 2);
934
935 if (bus_dmamap_create(sc->sc_dmat, 0xfff0, UBS_MAX_SCATTER,
936 0xfff0, 0, BUS_DMA_NOWAIT, &q->q_src_map) != 0) {
937 err = ENOMEM;
938 goto errout;
939 }
940 if (crp->crp_flags & CRYPTO_F_IMBUF) {
941 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map,
942 q->q_src_m, BUS_DMA_NOWAIT) != 0) {
943 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
944 q->q_src_map = NULL;
945 err = ENOMEM;
946 goto errout;
947 }
948 } else if (crp->crp_flags & CRYPTO_F_IOV) {
949 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map,
950 q->q_src_io, BUS_DMA_NOWAIT) != 0) {
951 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
952 q->q_src_map = NULL;
953 err = ENOMEM;
954 goto errout;
955 }
956 }
957 nicealign = ubsec_dmamap_aligned(q->q_src_map);
958
959 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend);
960
961 #ifdef UBSEC_DEBUG
962 printf("src skip: %d\n", sskip);
963 #endif
964 for (i = j = 0; i < q->q_src_map->dm_nsegs; i++) {
965 struct ubsec_pktbuf *pb;
966 bus_size_t packl = q->q_src_map->dm_segs[i].ds_len;
967 bus_addr_t packp = q->q_src_map->dm_segs[i].ds_addr;
968
969 if (sskip >= packl) {
970 sskip -= packl;
971 continue;
972 }
973
974 packl -= sskip;
975 packp += sskip;
976 sskip = 0;
977
978 if (packl > 0xfffc) {
979 err = EIO;
980 goto errout;
981 }
982
983 if (j == 0)
984 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf;
985 else
986 pb = &dmap->d_dma->d_sbuf[j - 1];
987
988 pb->pb_addr = htole32(packp);
989
990 if (stheend) {
991 if (packl > stheend) {
992 pb->pb_len = htole32(stheend);
993 stheend = 0;
994 } else {
995 pb->pb_len = htole32(packl);
996 stheend -= packl;
997 }
998 } else
999 pb->pb_len = htole32(packl);
1000
1001 if ((i + 1) == q->q_src_map->dm_nsegs)
1002 pb->pb_next = 0;
1003 else
1004 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1005 offsetof(struct ubsec_dmachunk, d_sbuf[j]));
1006 j++;
1007 }
1008
1009 if (enccrd == NULL && maccrd != NULL) {
1010 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0;
1011 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0;
1012 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next =
1013 htole32(dmap->d_alloc.dma_paddr +
1014 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1015 #ifdef UBSEC_DEBUG
1016 printf("opkt: %x %x %x\n",
1017 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr,
1018 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len,
1019 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next);
1020 #endif
1021 } else {
1022 if (crp->crp_flags & CRYPTO_F_IOV) {
1023 if (!nicealign) {
1024 err = EINVAL;
1025 goto errout;
1026 }
1027 if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1028 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1029 &q->q_dst_map) != 0) {
1030 err = ENOMEM;
1031 goto errout;
1032 }
1033 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map,
1034 q->q_dst_io, BUS_DMA_NOWAIT) != 0) {
1035 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1036 q->q_dst_map = NULL;
1037 goto errout;
1038 }
1039 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1040 if (nicealign) {
1041 q->q_dst_m = q->q_src_m;
1042 q->q_dst_map = q->q_src_map;
1043 } else {
1044 int totlen, len;
1045 struct mbuf *m, *top, **mp;
1046
1047 totlen = q->q_src_map->dm_mapsize;
1048 if (q->q_src_m->m_flags & M_PKTHDR) {
1049 len = MHLEN;
1050 MGETHDR(m, M_DONTWAIT, MT_DATA);
1051 } else {
1052 len = MLEN;
1053 MGET(m, M_DONTWAIT, MT_DATA);
1054 }
1055 if (m == NULL) {
1056 err = ENOMEM;
1057 goto errout;
1058 }
1059 if (len == MHLEN)
1060 M_DUP_PKTHDR(m, q->q_src_m);
1061 if (totlen >= MINCLSIZE) {
1062 MCLGET(m, M_DONTWAIT);
1063 if (m->m_flags & M_EXT)
1064 len = MCLBYTES;
1065 }
1066 m->m_len = len;
1067 top = NULL;
1068 mp = ⊤
1069
1070 while (totlen > 0) {
1071 if (top) {
1072 MGET(m, M_DONTWAIT, MT_DATA);
1073 if (m == NULL) {
1074 m_freem(top);
1075 err = ENOMEM;
1076 goto errout;
1077 }
1078 len = MLEN;
1079 }
1080 if (top && totlen >= MINCLSIZE) {
1081 MCLGET(m, M_DONTWAIT);
1082 if (m->m_flags & M_EXT)
1083 len = MCLBYTES;
1084 }
1085 m->m_len = len = min(totlen, len);
1086 totlen -= len;
1087 *mp = m;
1088 mp = &m->m_next;
1089 }
1090 q->q_dst_m = top;
1091 ubsec_mcopy(q->q_src_m, q->q_dst_m,
1092 cpskip, cpoffset);
1093 if (bus_dmamap_create(sc->sc_dmat, 0xfff0,
1094 UBS_MAX_SCATTER, 0xfff0, 0, BUS_DMA_NOWAIT,
1095 &q->q_dst_map) != 0) {
1096 err = ENOMEM;
1097 goto errout;
1098 }
1099 if (bus_dmamap_load_mbuf(sc->sc_dmat,
1100 q->q_dst_map, q->q_dst_m,
1101 BUS_DMA_NOWAIT) != 0) {
1102 bus_dmamap_destroy(sc->sc_dmat,
1103 q->q_dst_map);
1104 q->q_dst_map = NULL;
1105 err = ENOMEM;
1106 goto errout;
1107 }
1108 }
1109 } else {
1110 err = EINVAL;
1111 goto errout;
1112 }
1113
1114 #ifdef UBSEC_DEBUG
1115 printf("dst skip: %d\n", dskip);
1116 #endif
1117 for (i = j = 0; i < q->q_dst_map->dm_nsegs; i++) {
1118 struct ubsec_pktbuf *pb;
1119 bus_size_t packl = q->q_dst_map->dm_segs[i].ds_len;
1120 bus_addr_t packp = q->q_dst_map->dm_segs[i].ds_addr;
1121
1122 if (dskip >= packl) {
1123 dskip -= packl;
1124 continue;
1125 }
1126
1127 packl -= dskip;
1128 packp += dskip;
1129 dskip = 0;
1130
1131 if (packl > 0xfffc) {
1132 err = EIO;
1133 goto errout;
1134 }
1135
1136 if (j == 0)
1137 pb = &dmap->d_dma->d_mcr.mcr_opktbuf;
1138 else
1139 pb = &dmap->d_dma->d_dbuf[j - 1];
1140
1141 pb->pb_addr = htole32(packp);
1142
1143 if (dtheend) {
1144 if (packl > dtheend) {
1145 pb->pb_len = htole32(dtheend);
1146 dtheend = 0;
1147 } else {
1148 pb->pb_len = htole32(packl);
1149 dtheend -= packl;
1150 }
1151 } else
1152 pb->pb_len = htole32(packl);
1153
1154 if ((i + 1) == q->q_dst_map->dm_nsegs) {
1155 if (maccrd)
1156 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1157 offsetof(struct ubsec_dmachunk, d_macbuf[0]));
1158 else
1159 pb->pb_next = 0;
1160 } else
1161 pb->pb_next = htole32(dmap->d_alloc.dma_paddr +
1162 offsetof(struct ubsec_dmachunk, d_dbuf[j]));
1163 j++;
1164 }
1165 }
1166
1167 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr +
1168 offsetof(struct ubsec_dmachunk, d_ctx));
1169
1170 if (sc->sc_flags & UBS_FLAGS_LONGCTX) {
1171 struct ubsec_pktctx_long *ctxl;
1172
1173 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr +
1174 offsetof(struct ubsec_dmachunk, d_ctx));
1175
1176 /* transform small context into long context */
1177 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long));
1178 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC);
1179 ctxl->pc_flags = ctx.pc_flags;
1180 ctxl->pc_offset = ctx.pc_offset;
1181 for (i = 0; i < 6; i++)
1182 ctxl->pc_deskey[i] = ctx.pc_deskey[i];
1183 for (i = 0; i < 5; i++)
1184 ctxl->pc_hminner[i] = ctx.pc_hminner[i];
1185 for (i = 0; i < 5; i++)
1186 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i];
1187 ctxl->pc_iv[0] = ctx.pc_iv[0];
1188 ctxl->pc_iv[1] = ctx.pc_iv[1];
1189 } else
1190 bcopy(&ctx, dmap->d_alloc.dma_vaddr +
1191 offsetof(struct ubsec_dmachunk, d_ctx),
1192 sizeof(struct ubsec_pktctx));
1193
1194 s = splnet();
1195 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next);
1196 sc->sc_nqueue++;
1197 ubsecstats.hst_ipackets++;
1198 ubsecstats.hst_ibytes += dmap->d_alloc.dma_map->dm_mapsize;
1199 ubsec_feed(sc);
1200 splx(s);
1201 return (0);
1202
1203 errout:
1204 if (q != NULL) {
1205 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1206 m_freem(q->q_dst_m);
1207
1208 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1209 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1210 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1211 }
1212 if (q->q_src_map != NULL) {
1213 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1214 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1215 }
1216
1217 s = splnet();
1218 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1219 splx(s);
1220 }
1221 if (err == EINVAL)
1222 ubsecstats.hst_invalid++;
1223 else
1224 ubsecstats.hst_nomem++;
1225 errout2:
1226 crp->crp_etype = err;
1227 crypto_done(crp);
1228 return (0);
1229 }
1230
1231 void
ubsec_callback(struct ubsec_softc * sc,struct ubsec_q * q)1232 ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q)
1233 {
1234 struct cryptop *crp = (struct cryptop *)q->q_crp;
1235 struct cryptodesc *crd;
1236 struct ubsec_dma *dmap = q->q_dma;
1237
1238 ubsecstats.hst_opackets++;
1239 ubsecstats.hst_obytes += dmap->d_alloc.dma_size;
1240
1241 bus_dmamap_sync(sc->sc_dmat, dmap->d_alloc.dma_map, 0,
1242 dmap->d_alloc.dma_map->dm_mapsize,
1243 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1244 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) {
1245 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map,
1246 0, q->q_dst_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1247 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map);
1248 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map);
1249 }
1250 bus_dmamap_sync(sc->sc_dmat, q->q_src_map,
1251 0, q->q_src_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1252 bus_dmamap_unload(sc->sc_dmat, q->q_src_map);
1253 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map);
1254
1255 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) {
1256 m_freem(q->q_src_m);
1257 crp->crp_buf = (caddr_t)q->q_dst_m;
1258 }
1259
1260 /* copy out IV for future use */
1261 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) {
1262 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1263 if (crd->crd_alg != CRYPTO_DES_CBC &&
1264 crd->crd_alg != CRYPTO_3DES_CBC)
1265 continue;
1266 if (crp->crp_flags & CRYPTO_F_IMBUF)
1267 m_copydata((struct mbuf *)crp->crp_buf,
1268 crd->crd_skip + crd->crd_len - 8, 8,
1269 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1270 else if (crp->crp_flags & CRYPTO_F_IOV) {
1271 cuio_copydata((struct uio *)crp->crp_buf,
1272 crd->crd_skip + crd->crd_len - 8, 8,
1273 (caddr_t)sc->sc_sessions[q->q_sesn].ses_iv);
1274 }
1275 break;
1276 }
1277 }
1278
1279 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
1280 if (crd->crd_alg != CRYPTO_MD5_HMAC &&
1281 crd->crd_alg != CRYPTO_SHA1_HMAC)
1282 continue;
1283 if (crp->crp_flags & CRYPTO_F_IMBUF)
1284 m_copyback((struct mbuf *)crp->crp_buf,
1285 crd->crd_inject, 12,
1286 dmap->d_dma->d_macbuf);
1287 else if (crp->crp_flags & CRYPTO_F_IOV && crp->crp_mac)
1288 bcopy((caddr_t)dmap->d_dma->d_macbuf,
1289 crp->crp_mac, 12);
1290 break;
1291 }
1292 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1293 crypto_done(crp);
1294 }
1295
1296 void
ubsec_mcopy(struct mbuf * srcm,struct mbuf * dstm,int hoffset,int toffset)1297 ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset)
1298 {
1299 int i, j, dlen, slen;
1300 caddr_t dptr, sptr;
1301
1302 j = 0;
1303 sptr = srcm->m_data;
1304 slen = srcm->m_len;
1305 dptr = dstm->m_data;
1306 dlen = dstm->m_len;
1307
1308 while (1) {
1309 for (i = 0; i < min(slen, dlen); i++) {
1310 if (j < hoffset || j >= toffset)
1311 *dptr++ = *sptr++;
1312 slen--;
1313 dlen--;
1314 j++;
1315 }
1316 if (slen == 0) {
1317 srcm = srcm->m_next;
1318 if (srcm == NULL)
1319 return;
1320 sptr = srcm->m_data;
1321 slen = srcm->m_len;
1322 }
1323 if (dlen == 0) {
1324 dstm = dstm->m_next;
1325 if (dstm == NULL)
1326 return;
1327 dptr = dstm->m_data;
1328 dlen = dstm->m_len;
1329 }
1330 }
1331 }
1332
1333 /*
1334 * feed the key generator, must be called at splnet() or higher.
1335 */
1336 void
ubsec_feed2(struct ubsec_softc * sc)1337 ubsec_feed2(struct ubsec_softc *sc)
1338 {
1339 struct ubsec_q2 *q;
1340
1341 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) {
1342 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL)
1343 break;
1344 q = SIMPLEQ_FIRST(&sc->sc_queue2);
1345
1346 bus_dmamap_sync(sc->sc_dmat, q->q_mcr.dma_map, 0,
1347 q->q_mcr.dma_map->dm_mapsize,
1348 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1349 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0,
1350 q->q_ctx.dma_map->dm_mapsize,
1351 BUS_DMASYNC_PREWRITE);
1352
1353 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr);
1354 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next);
1355 --sc->sc_nqueue2;
1356 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next);
1357 }
1358 }
1359
1360 /*
1361 * Callback for handling random numbers
1362 */
1363 void
ubsec_callback2(struct ubsec_softc * sc,struct ubsec_q2 * q)1364 ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q)
1365 {
1366 struct cryptkop *krp;
1367 struct ubsec_ctx_keyop *ctx;
1368
1369 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr;
1370 bus_dmamap_sync(sc->sc_dmat, q->q_ctx.dma_map, 0,
1371 q->q_ctx.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1372
1373 switch (q->q_type) {
1374 #ifndef UBSEC_NO_RNG
1375 case UBS_CTXOP_RNGSHA1:
1376 case UBS_CTXOP_RNGBYPASS: {
1377 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q;
1378 u_int32_t *p;
1379 int i;
1380
1381 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0,
1382 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1383 p = (u_int32_t *)rng->rng_buf.dma_vaddr;
1384 for (i = 0; i < UBSEC_RNG_BUFSIZ; p++, i++)
1385 add_true_randomness(*p);
1386 rng->rng_used = 0;
1387 timeout_add(&sc->sc_rngto, sc->sc_rnghz);
1388 break;
1389 }
1390 #endif
1391 case UBS_CTXOP_MODEXP: {
1392 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1393 u_int rlen, clen;
1394
1395 krp = me->me_krp;
1396 rlen = (me->me_modbits + 7) / 8;
1397 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8;
1398
1399 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map,
1400 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1401 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map,
1402 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1403 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map,
1404 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1405 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map,
1406 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1407
1408 if (clen < rlen)
1409 krp->krp_status = E2BIG;
1410 else {
1411 if (sc->sc_flags & UBS_FLAGS_HWNORM) {
1412 bzero(krp->krp_param[krp->krp_iparams].crp_p,
1413 (krp->krp_param[krp->krp_iparams].crp_nbits
1414 + 7) / 8);
1415 bcopy(me->me_C.dma_vaddr,
1416 krp->krp_param[krp->krp_iparams].crp_p,
1417 (me->me_modbits + 7) / 8);
1418 } else
1419 ubsec_kshift_l(me->me_shiftbits,
1420 me->me_C.dma_vaddr, me->me_normbits,
1421 krp->krp_param[krp->krp_iparams].crp_p,
1422 krp->krp_param[krp->krp_iparams].crp_nbits);
1423 }
1424 crypto_kdone(krp);
1425
1426 /* bzero all potentially sensitive data */
1427 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1428 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1429 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1430 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1431
1432 /* Can't free here, so put us on the free list. */
1433 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next);
1434 break;
1435 }
1436 case UBS_CTXOP_RSAPRIV: {
1437 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1438 u_int len;
1439
1440 krp = rp->rpr_krp;
1441 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map, 0,
1442 rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1443 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map, 0,
1444 rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1445
1446 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8;
1447 bcopy(rp->rpr_msgout.dma_vaddr,
1448 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len);
1449
1450 crypto_kdone(krp);
1451
1452 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
1453 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
1454 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size);
1455
1456 /* Can't free here, so put us on the free list. */
1457 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next);
1458 break;
1459 }
1460 default:
1461 printf("%s: unknown ctx op: %x\n", sc->sc_dv.dv_xname,
1462 letoh16(ctx->ctx_op));
1463 break;
1464 }
1465 }
1466
1467 #ifndef UBSEC_NO_RNG
1468 void
ubsec_rng(void * vsc)1469 ubsec_rng(void *vsc)
1470 {
1471 struct ubsec_softc *sc = vsc;
1472 struct ubsec_q2_rng *rng = &sc->sc_rng;
1473 struct ubsec_mcr *mcr;
1474 struct ubsec_ctx_rngbypass *ctx;
1475 int s;
1476
1477 s = splnet();
1478 if (rng->rng_used) {
1479 splx(s);
1480 return;
1481 }
1482 sc->sc_nqueue2++;
1483 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE)
1484 goto out;
1485
1486 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr;
1487 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr;
1488
1489 mcr->mcr_pkts = htole16(1);
1490 mcr->mcr_flags = 0;
1491 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr);
1492 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0;
1493 mcr->mcr_ipktbuf.pb_len = 0;
1494 mcr->mcr_reserved = mcr->mcr_pktlen = 0;
1495 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr);
1496 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) &
1497 UBS_PKTBUF_LEN);
1498 mcr->mcr_opktbuf.pb_next = 0;
1499
1500 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass));
1501 ctx->rbp_op = htole16(UBS_CTXOP_RNGSHA1);
1502 rng->rng_q.q_type = UBS_CTXOP_RNGSHA1;
1503
1504 bus_dmamap_sync(sc->sc_dmat, rng->rng_buf.dma_map, 0,
1505 rng->rng_buf.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD);
1506
1507 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next);
1508 rng->rng_used = 1;
1509 ubsec_feed2(sc);
1510 splx(s);
1511
1512 return;
1513
1514 out:
1515 /*
1516 * Something weird happened, generate our own call back.
1517 */
1518 sc->sc_nqueue2--;
1519 splx(s);
1520 timeout_add(&sc->sc_rngto, sc->sc_rnghz);
1521 }
1522 #endif /* UBSEC_NO_RNG */
1523
1524 int
ubsec_dma_malloc(struct ubsec_softc * sc,bus_size_t size,struct ubsec_dma_alloc * dma,int mapflags)1525 ubsec_dma_malloc(struct ubsec_softc *sc, bus_size_t size,
1526 struct ubsec_dma_alloc *dma, int mapflags)
1527 {
1528 int r;
1529
1530 if ((r = bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0,
1531 &dma->dma_seg, 1, &dma->dma_nseg, BUS_DMA_NOWAIT)) != 0)
1532 goto fail_0;
1533
1534 if ((r = bus_dmamem_map(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg,
1535 size, &dma->dma_vaddr, mapflags | BUS_DMA_NOWAIT)) != 0)
1536 goto fail_1;
1537
1538 if ((r = bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
1539 BUS_DMA_NOWAIT, &dma->dma_map)) != 0)
1540 goto fail_2;
1541
1542 if ((r = bus_dmamap_load(sc->sc_dmat, dma->dma_map, dma->dma_vaddr,
1543 size, NULL, BUS_DMA_NOWAIT)) != 0)
1544 goto fail_3;
1545
1546 dma->dma_paddr = dma->dma_map->dm_segs[0].ds_addr;
1547 dma->dma_size = size;
1548 return (0);
1549
1550 fail_3:
1551 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
1552 fail_2:
1553 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, size);
1554 fail_1:
1555 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg);
1556 fail_0:
1557 dma->dma_map = NULL;
1558 return (r);
1559 }
1560
1561 void
ubsec_dma_free(struct ubsec_softc * sc,struct ubsec_dma_alloc * dma)1562 ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma)
1563 {
1564 bus_dmamap_unload(sc->sc_dmat, dma->dma_map);
1565 bus_dmamem_unmap(sc->sc_dmat, dma->dma_vaddr, dma->dma_size);
1566 bus_dmamem_free(sc->sc_dmat, &dma->dma_seg, dma->dma_nseg);
1567 bus_dmamap_destroy(sc->sc_dmat, dma->dma_map);
1568 }
1569
1570 /*
1571 * Resets the board. Values in the regesters are left as is
1572 * from the reset (i.e. initial values are assigned elsewhere).
1573 */
1574 void
ubsec_reset_board(struct ubsec_softc * sc)1575 ubsec_reset_board(struct ubsec_softc *sc)
1576 {
1577 volatile u_int32_t ctrl;
1578
1579 ctrl = READ_REG(sc, BS_CTRL);
1580 ctrl |= BS_CTRL_RESET;
1581 WRITE_REG(sc, BS_CTRL, ctrl);
1582
1583 /*
1584 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us
1585 */
1586 DELAY(10);
1587 }
1588
1589 /*
1590 * Init Broadcom registers
1591 */
1592 void
ubsec_init_board(struct ubsec_softc * sc)1593 ubsec_init_board(struct ubsec_softc *sc)
1594 {
1595 u_int32_t ctrl;
1596
1597 ctrl = READ_REG(sc, BS_CTRL);
1598 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64);
1599 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT;
1600
1601 if (sc->sc_flags & UBS_FLAGS_KEY)
1602 ctrl |= BS_CTRL_MCR2INT;
1603 else
1604 ctrl &= ~BS_CTRL_MCR2INT;
1605
1606 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1607 ctrl &= ~BS_CTRL_SWNORM;
1608
1609 WRITE_REG(sc, BS_CTRL, ctrl);
1610 }
1611
1612 /*
1613 * Init Broadcom PCI registers
1614 */
1615 void
ubsec_init_pciregs(struct pci_attach_args * pa)1616 ubsec_init_pciregs(struct pci_attach_args *pa)
1617 {
1618 pci_chipset_tag_t pc = pa->pa_pc;
1619 u_int32_t misc;
1620
1621 /*
1622 * This will set the cache line size to 1, this will
1623 * force the BCM58xx chip just to do burst read/writes.
1624 * Cache line read/writes are to slow
1625 */
1626 misc = pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG);
1627 misc = (misc & ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT))
1628 | ((UBS_DEF_CACHELINE & 0xff) << PCI_CACHELINE_SHIFT);
1629 pci_conf_write(pc, pa->pa_tag, PCI_BHLC_REG, misc);
1630 }
1631
1632 /*
1633 * Clean up after a chip crash.
1634 * It is assumed that the caller is in splnet()
1635 */
1636 void
ubsec_cleanchip(struct ubsec_softc * sc)1637 ubsec_cleanchip(struct ubsec_softc *sc)
1638 {
1639 struct ubsec_q *q;
1640
1641 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) {
1642 q = SIMPLEQ_FIRST(&sc->sc_qchip);
1643 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next);
1644 ubsec_free_q(sc, q);
1645 }
1646 }
1647
1648 /*
1649 * free a ubsec_q
1650 * It is assumed that the caller is within splnet()
1651 */
1652 int
ubsec_free_q(struct ubsec_softc * sc,struct ubsec_q * q)1653 ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q)
1654 {
1655 struct ubsec_q *q2;
1656 struct cryptop *crp;
1657 int npkts;
1658 int i;
1659
1660 npkts = q->q_nstacked_mcrs;
1661
1662 for (i = 0; i < npkts; i++) {
1663 if(q->q_stacked_mcr[i]) {
1664 q2 = q->q_stacked_mcr[i];
1665
1666 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m))
1667 m_freem(q2->q_dst_m);
1668
1669 crp = (struct cryptop *)q2->q_crp;
1670
1671 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next);
1672
1673 crp->crp_etype = EFAULT;
1674 crypto_done(crp);
1675 } else {
1676 break;
1677 }
1678 }
1679
1680 /*
1681 * Free header MCR
1682 */
1683 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m))
1684 m_freem(q->q_dst_m);
1685
1686 crp = (struct cryptop *)q->q_crp;
1687
1688 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next);
1689
1690 crp->crp_etype = EFAULT;
1691 crypto_done(crp);
1692 return(0);
1693 }
1694
1695 /*
1696 * Routine to reset the chip and clean up.
1697 * It is assumed that the caller is in splnet()
1698 */
1699 void
ubsec_totalreset(struct ubsec_softc * sc)1700 ubsec_totalreset(struct ubsec_softc *sc)
1701 {
1702 ubsec_reset_board(sc);
1703 ubsec_init_board(sc);
1704 ubsec_cleanchip(sc);
1705 }
1706
1707 int
ubsec_dmamap_aligned(bus_dmamap_t map)1708 ubsec_dmamap_aligned(bus_dmamap_t map)
1709 {
1710 int i;
1711
1712 for (i = 0; i < map->dm_nsegs; i++) {
1713 if (map->dm_segs[i].ds_addr & 3)
1714 return (0);
1715 if ((i != (map->dm_nsegs - 1)) &&
1716 (map->dm_segs[i].ds_len & 3))
1717 return (0);
1718 }
1719 return (1);
1720 }
1721
1722 struct ubsec_softc *
ubsec_kfind(struct cryptkop * krp)1723 ubsec_kfind(struct cryptkop *krp)
1724 {
1725 struct ubsec_softc *sc;
1726 int i;
1727
1728 for (i = 0; i < ubsec_cd.cd_ndevs; i++) {
1729 sc = ubsec_cd.cd_devs[i];
1730 if (sc == NULL)
1731 continue;
1732 if (sc->sc_cid == krp->krp_hid)
1733 return (sc);
1734 }
1735 return (NULL);
1736 }
1737
1738 void
ubsec_kfree(struct ubsec_softc * sc,struct ubsec_q2 * q)1739 ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q)
1740 {
1741 switch (q->q_type) {
1742 case UBS_CTXOP_MODEXP: {
1743 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q;
1744
1745 ubsec_dma_free(sc, &me->me_q.q_mcr);
1746 ubsec_dma_free(sc, &me->me_q.q_ctx);
1747 ubsec_dma_free(sc, &me->me_M);
1748 ubsec_dma_free(sc, &me->me_E);
1749 ubsec_dma_free(sc, &me->me_C);
1750 ubsec_dma_free(sc, &me->me_epb);
1751 free(me, M_DEVBUF);
1752 break;
1753 }
1754 case UBS_CTXOP_RSAPRIV: {
1755 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q;
1756
1757 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
1758 ubsec_dma_free(sc, &rp->rpr_q.q_ctx);
1759 ubsec_dma_free(sc, &rp->rpr_msgin);
1760 ubsec_dma_free(sc, &rp->rpr_msgout);
1761 free(rp, M_DEVBUF);
1762 break;
1763 }
1764 default:
1765 printf("%s: invalid kfree 0x%x\n", sc->sc_dv.dv_xname,
1766 q->q_type);
1767 break;
1768 }
1769 }
1770
1771 int
ubsec_kprocess(struct cryptkop * krp)1772 ubsec_kprocess(struct cryptkop *krp)
1773 {
1774 struct ubsec_softc *sc;
1775 int r;
1776
1777 if (krp == NULL || krp->krp_callback == NULL)
1778 return (EINVAL);
1779 if ((sc = ubsec_kfind(krp)) == NULL)
1780 return (EINVAL);
1781
1782 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) {
1783 struct ubsec_q2 *q;
1784
1785 q = SIMPLEQ_FIRST(&sc->sc_q2free);
1786 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next);
1787 ubsec_kfree(sc, q);
1788 }
1789
1790 switch (krp->krp_op) {
1791 case CRK_MOD_EXP:
1792 if (sc->sc_flags & UBS_FLAGS_HWNORM)
1793 r = ubsec_kprocess_modexp_hw(sc, krp);
1794 else
1795 r = ubsec_kprocess_modexp_sw(sc, krp);
1796 break;
1797 case CRK_MOD_EXP_CRT:
1798 r = ubsec_kprocess_rsapriv(sc, krp);
1799 break;
1800 default:
1801 printf("%s: kprocess: invalid op 0x%x\n",
1802 sc->sc_dv.dv_xname, krp->krp_op);
1803 krp->krp_status = EOPNOTSUPP;
1804 crypto_kdone(krp);
1805 r = 0;
1806 }
1807 return (r);
1808 }
1809
1810 /*
1811 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization)
1812 */
1813 int
ubsec_kprocess_modexp_sw(struct ubsec_softc * sc,struct cryptkop * krp)1814 ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp)
1815 {
1816 struct ubsec_q2_modexp *me;
1817 struct ubsec_mcr *mcr;
1818 struct ubsec_ctx_modexp *ctx;
1819 struct ubsec_pktbuf *epb;
1820 int err = 0, s;
1821 u_int nbits, normbits, mbits, shiftbits, ebits;
1822
1823 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
1824 if (me == NULL) {
1825 err = ENOMEM;
1826 goto errout;
1827 }
1828 bzero(me, sizeof *me);
1829 me->me_krp = krp;
1830 me->me_q.q_type = UBS_CTXOP_MODEXP;
1831
1832 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
1833 if (nbits <= 512)
1834 normbits = 512;
1835 else if (nbits <= 768)
1836 normbits = 768;
1837 else if (nbits <= 1024)
1838 normbits = 1024;
1839 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
1840 normbits = 1536;
1841 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
1842 normbits = 2048;
1843 else {
1844 err = E2BIG;
1845 goto errout;
1846 }
1847
1848 shiftbits = normbits - nbits;
1849
1850 me->me_modbits = nbits;
1851 me->me_shiftbits = shiftbits;
1852 me->me_normbits = normbits;
1853
1854 /* Sanity check: result bits must be >= true modulus bits. */
1855 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
1856 err = ERANGE;
1857 goto errout;
1858 }
1859
1860 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
1861 &me->me_q.q_mcr, 0)) {
1862 err = ENOMEM;
1863 goto errout;
1864 }
1865 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
1866
1867 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
1868 &me->me_q.q_ctx, 0)) {
1869 err = ENOMEM;
1870 goto errout;
1871 }
1872
1873 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
1874 if (mbits > nbits) {
1875 err = E2BIG;
1876 goto errout;
1877 }
1878 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
1879 err = ENOMEM;
1880 goto errout;
1881 }
1882 ubsec_kshift_r(shiftbits,
1883 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits,
1884 me->me_M.dma_vaddr, normbits);
1885
1886 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
1887 err = ENOMEM;
1888 goto errout;
1889 }
1890 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1891
1892 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
1893 if (ebits > nbits) {
1894 err = E2BIG;
1895 goto errout;
1896 }
1897 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
1898 err = ENOMEM;
1899 goto errout;
1900 }
1901 ubsec_kshift_r(shiftbits,
1902 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits,
1903 me->me_E.dma_vaddr, normbits);
1904
1905 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
1906 &me->me_epb, 0)) {
1907 err = ENOMEM;
1908 goto errout;
1909 }
1910 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
1911 epb->pb_addr = htole32(me->me_E.dma_paddr);
1912 epb->pb_next = 0;
1913 epb->pb_len = htole32(normbits / 8);
1914
1915 #ifdef UBSEC_DEBUG
1916 printf("Epb ");
1917 ubsec_dump_pb(epb);
1918 #endif
1919
1920 mcr->mcr_pkts = htole16(1);
1921 mcr->mcr_flags = 0;
1922 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
1923 mcr->mcr_reserved = 0;
1924 mcr->mcr_pktlen = 0;
1925
1926 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
1927 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
1928 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
1929
1930 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
1931 mcr->mcr_opktbuf.pb_next = 0;
1932 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
1933
1934 #ifdef DIAGNOSTIC
1935 /* Misaligned output buffer will hang the chip. */
1936 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
1937 panic("%s: modexp invalid addr 0x%x",
1938 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_addr));
1939 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
1940 panic("%s: modexp invalid len 0x%x",
1941 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_len));
1942 #endif
1943
1944 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
1945 bzero(ctx, sizeof(*ctx));
1946 ubsec_kshift_r(shiftbits,
1947 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits,
1948 ctx->me_N, normbits);
1949 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
1950 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
1951 ctx->me_E_len = htole16(nbits);
1952 ctx->me_N_len = htole16(nbits);
1953
1954 #ifdef UBSEC_DEBUG
1955 ubsec_dump_mcr(mcr);
1956 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
1957 #endif
1958
1959 /*
1960 * ubsec_feed2 will sync mcr and ctx, we just need to sync
1961 * everything else.
1962 */
1963 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map,
1964 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1965 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map,
1966 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1967 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map,
1968 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD);
1969 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map,
1970 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1971
1972 /* Enqueue and we're done... */
1973 s = splnet();
1974 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
1975 ubsec_feed2(sc);
1976 splx(s);
1977
1978 return (0);
1979
1980 errout:
1981 if (me != NULL) {
1982 if (me->me_q.q_mcr.dma_map != NULL)
1983 ubsec_dma_free(sc, &me->me_q.q_mcr);
1984 if (me->me_q.q_ctx.dma_map != NULL) {
1985 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
1986 ubsec_dma_free(sc, &me->me_q.q_ctx);
1987 }
1988 if (me->me_M.dma_map != NULL) {
1989 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
1990 ubsec_dma_free(sc, &me->me_M);
1991 }
1992 if (me->me_E.dma_map != NULL) {
1993 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
1994 ubsec_dma_free(sc, &me->me_E);
1995 }
1996 if (me->me_C.dma_map != NULL) {
1997 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
1998 ubsec_dma_free(sc, &me->me_C);
1999 }
2000 if (me->me_epb.dma_map != NULL)
2001 ubsec_dma_free(sc, &me->me_epb);
2002 free(me, M_DEVBUF);
2003 }
2004 krp->krp_status = err;
2005 crypto_kdone(krp);
2006 return (0);
2007 }
2008
2009 /*
2010 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization)
2011 */
2012 int
ubsec_kprocess_modexp_hw(struct ubsec_softc * sc,struct cryptkop * krp)2013 ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp)
2014 {
2015 struct ubsec_q2_modexp *me;
2016 struct ubsec_mcr *mcr;
2017 struct ubsec_ctx_modexp *ctx;
2018 struct ubsec_pktbuf *epb;
2019 int err = 0, s;
2020 u_int nbits, normbits, mbits, shiftbits, ebits;
2021
2022 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT);
2023 if (me == NULL) {
2024 err = ENOMEM;
2025 goto errout;
2026 }
2027 bzero(me, sizeof *me);
2028 me->me_krp = krp;
2029 me->me_q.q_type = UBS_CTXOP_MODEXP;
2030
2031 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]);
2032 if (nbits <= 512)
2033 normbits = 512;
2034 else if (nbits <= 768)
2035 normbits = 768;
2036 else if (nbits <= 1024)
2037 normbits = 1024;
2038 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536)
2039 normbits = 1536;
2040 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048)
2041 normbits = 2048;
2042 else {
2043 err = E2BIG;
2044 goto errout;
2045 }
2046
2047 shiftbits = normbits - nbits;
2048
2049 /* XXX ??? */
2050 me->me_modbits = nbits;
2051 me->me_shiftbits = shiftbits;
2052 me->me_normbits = normbits;
2053
2054 /* Sanity check: result bits must be >= true modulus bits. */
2055 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) {
2056 err = ERANGE;
2057 goto errout;
2058 }
2059
2060 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2061 &me->me_q.q_mcr, 0)) {
2062 err = ENOMEM;
2063 goto errout;
2064 }
2065 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr;
2066
2067 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp),
2068 &me->me_q.q_ctx, 0)) {
2069 err = ENOMEM;
2070 goto errout;
2071 }
2072
2073 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]);
2074 if (mbits > nbits) {
2075 err = E2BIG;
2076 goto errout;
2077 }
2078 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) {
2079 err = ENOMEM;
2080 goto errout;
2081 }
2082 bzero(me->me_M.dma_vaddr, normbits / 8);
2083 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p,
2084 me->me_M.dma_vaddr, (mbits + 7) / 8);
2085
2086 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) {
2087 err = ENOMEM;
2088 goto errout;
2089 }
2090 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2091
2092 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]);
2093 if (ebits > nbits) {
2094 err = E2BIG;
2095 goto errout;
2096 }
2097 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) {
2098 err = ENOMEM;
2099 goto errout;
2100 }
2101 bzero(me->me_E.dma_vaddr, normbits / 8);
2102 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p,
2103 me->me_E.dma_vaddr, (ebits + 7) / 8);
2104
2105 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf),
2106 &me->me_epb, 0)) {
2107 err = ENOMEM;
2108 goto errout;
2109 }
2110 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr;
2111 epb->pb_addr = htole32(me->me_E.dma_paddr);
2112 epb->pb_next = 0;
2113 epb->pb_len = htole32((ebits + 7) / 8);
2114
2115 #ifdef UBSEC_DEBUG
2116 printf("Epb ");
2117 ubsec_dump_pb(epb);
2118 #endif
2119
2120 mcr->mcr_pkts = htole16(1);
2121 mcr->mcr_flags = 0;
2122 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr);
2123 mcr->mcr_reserved = 0;
2124 mcr->mcr_pktlen = 0;
2125
2126 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr);
2127 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8);
2128 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr);
2129
2130 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr);
2131 mcr->mcr_opktbuf.pb_next = 0;
2132 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8);
2133
2134 #ifdef DIAGNOSTIC
2135 /* Misaligned output buffer will hang the chip. */
2136 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0)
2137 panic("%s: modexp invalid addr 0x%x",
2138 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_addr));
2139 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0)
2140 panic("%s: modexp invalid len 0x%x",
2141 sc->sc_dv.dv_xname, letoh32(mcr->mcr_opktbuf.pb_len));
2142 #endif
2143
2144 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr;
2145 bzero(ctx, sizeof(*ctx));
2146 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N,
2147 (nbits + 7) / 8);
2148 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t)));
2149 ctx->me_op = htole16(UBS_CTXOP_MODEXP);
2150 ctx->me_E_len = htole16(ebits);
2151 ctx->me_N_len = htole16(nbits);
2152
2153 #ifdef UBSEC_DEBUG
2154 ubsec_dump_mcr(mcr);
2155 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx);
2156 #endif
2157
2158 /*
2159 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2160 * everything else.
2161 */
2162 bus_dmamap_sync(sc->sc_dmat, me->me_M.dma_map,
2163 0, me->me_M.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
2164 bus_dmamap_sync(sc->sc_dmat, me->me_E.dma_map,
2165 0, me->me_E.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
2166 bus_dmamap_sync(sc->sc_dmat, me->me_C.dma_map,
2167 0, me->me_C.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD);
2168 bus_dmamap_sync(sc->sc_dmat, me->me_epb.dma_map,
2169 0, me->me_epb.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
2170
2171 /* Enqueue and we're done... */
2172 s = splnet();
2173 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next);
2174 ubsec_feed2(sc);
2175 splx(s);
2176
2177 return (0);
2178
2179 errout:
2180 if (me != NULL) {
2181 if (me->me_q.q_mcr.dma_map != NULL)
2182 ubsec_dma_free(sc, &me->me_q.q_mcr);
2183 if (me->me_q.q_ctx.dma_map != NULL) {
2184 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size);
2185 ubsec_dma_free(sc, &me->me_q.q_ctx);
2186 }
2187 if (me->me_M.dma_map != NULL) {
2188 bzero(me->me_M.dma_vaddr, me->me_M.dma_size);
2189 ubsec_dma_free(sc, &me->me_M);
2190 }
2191 if (me->me_E.dma_map != NULL) {
2192 bzero(me->me_E.dma_vaddr, me->me_E.dma_size);
2193 ubsec_dma_free(sc, &me->me_E);
2194 }
2195 if (me->me_C.dma_map != NULL) {
2196 bzero(me->me_C.dma_vaddr, me->me_C.dma_size);
2197 ubsec_dma_free(sc, &me->me_C);
2198 }
2199 if (me->me_epb.dma_map != NULL)
2200 ubsec_dma_free(sc, &me->me_epb);
2201 free(me, M_DEVBUF);
2202 }
2203 krp->krp_status = err;
2204 crypto_kdone(krp);
2205 return (0);
2206 }
2207
2208 int
ubsec_kprocess_rsapriv(struct ubsec_softc * sc,struct cryptkop * krp)2209 ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp)
2210 {
2211 struct ubsec_q2_rsapriv *rp = NULL;
2212 struct ubsec_mcr *mcr;
2213 struct ubsec_ctx_rsapriv *ctx;
2214 int err = 0, s;
2215 u_int padlen, msglen;
2216
2217 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]);
2218 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]);
2219 if (msglen > padlen)
2220 padlen = msglen;
2221
2222 if (padlen <= 256)
2223 padlen = 256;
2224 else if (padlen <= 384)
2225 padlen = 384;
2226 else if (padlen <= 512)
2227 padlen = 512;
2228 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768)
2229 padlen = 768;
2230 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024)
2231 padlen = 1024;
2232 else {
2233 err = E2BIG;
2234 goto errout;
2235 }
2236
2237 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) {
2238 err = E2BIG;
2239 goto errout;
2240 }
2241
2242 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) {
2243 err = E2BIG;
2244 goto errout;
2245 }
2246
2247 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) {
2248 err = E2BIG;
2249 goto errout;
2250 }
2251
2252 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT);
2253 if (rp == NULL)
2254 return (ENOMEM);
2255 bzero(rp, sizeof *rp);
2256 rp->rpr_krp = krp;
2257 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV;
2258
2259 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr),
2260 &rp->rpr_q.q_mcr, 0)) {
2261 err = ENOMEM;
2262 goto errout;
2263 }
2264 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr;
2265
2266 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv),
2267 &rp->rpr_q.q_ctx, 0)) {
2268 err = ENOMEM;
2269 goto errout;
2270 }
2271 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr;
2272 bzero(ctx, sizeof *ctx);
2273
2274 /* Copy in p */
2275 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p,
2276 &ctx->rpr_buf[0 * (padlen / 8)],
2277 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8);
2278
2279 /* Copy in q */
2280 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p,
2281 &ctx->rpr_buf[1 * (padlen / 8)],
2282 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8);
2283
2284 /* Copy in dp */
2285 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p,
2286 &ctx->rpr_buf[2 * (padlen / 8)],
2287 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8);
2288
2289 /* Copy in dq */
2290 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p,
2291 &ctx->rpr_buf[3 * (padlen / 8)],
2292 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8);
2293
2294 /* Copy in pinv */
2295 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p,
2296 &ctx->rpr_buf[4 * (padlen / 8)],
2297 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8);
2298
2299 msglen = padlen * 2;
2300
2301 /* Copy in input message (aligned buffer/length). */
2302 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) {
2303 /* Is this likely? */
2304 err = E2BIG;
2305 goto errout;
2306 }
2307 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) {
2308 err = ENOMEM;
2309 goto errout;
2310 }
2311 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8);
2312 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p,
2313 rp->rpr_msgin.dma_vaddr,
2314 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8);
2315
2316 /* Prepare space for output message (aligned buffer/length). */
2317 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) {
2318 /* Is this likely? */
2319 err = E2BIG;
2320 goto errout;
2321 }
2322 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) {
2323 err = ENOMEM;
2324 goto errout;
2325 }
2326 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8);
2327
2328 mcr->mcr_pkts = htole16(1);
2329 mcr->mcr_flags = 0;
2330 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr);
2331 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr);
2332 mcr->mcr_ipktbuf.pb_next = 0;
2333 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size);
2334 mcr->mcr_reserved = 0;
2335 mcr->mcr_pktlen = htole16(msglen);
2336 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr);
2337 mcr->mcr_opktbuf.pb_next = 0;
2338 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size);
2339
2340 #ifdef DIAGNOSTIC
2341 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) {
2342 panic("%s: rsapriv: invalid msgin %p(0x%x)",
2343 sc->sc_dv.dv_xname, (void *)(rp->rpr_msgin.dma_paddr),
2344 (unsigned)(rp->rpr_msgin.dma_size));
2345 }
2346 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) {
2347 panic("%s: rsapriv: invalid msgout %p(0x%x)",
2348 sc->sc_dv.dv_xname, (void *)(rp->rpr_msgout.dma_paddr),
2349 (unsigned)(rp->rpr_msgout.dma_size));
2350 }
2351 #endif
2352
2353 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8));
2354 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV);
2355 ctx->rpr_q_len = htole16(padlen);
2356 ctx->rpr_p_len = htole16(padlen);
2357
2358 /*
2359 * ubsec_feed2 will sync mcr and ctx, we just need to sync
2360 * everything else.
2361 */
2362 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgin.dma_map,
2363 0, rp->rpr_msgin.dma_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
2364 bus_dmamap_sync(sc->sc_dmat, rp->rpr_msgout.dma_map,
2365 0, rp->rpr_msgout.dma_map->dm_mapsize, BUS_DMASYNC_PREREAD);
2366
2367 /* Enqueue and we're done... */
2368 s = splnet();
2369 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next);
2370 ubsec_feed2(sc);
2371 splx(s);
2372 return (0);
2373
2374 errout:
2375 if (rp != NULL) {
2376 if (rp->rpr_q.q_mcr.dma_map != NULL)
2377 ubsec_dma_free(sc, &rp->rpr_q.q_mcr);
2378 if (rp->rpr_msgin.dma_map != NULL) {
2379 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size);
2380 ubsec_dma_free(sc, &rp->rpr_msgin);
2381 }
2382 if (rp->rpr_msgout.dma_map != NULL) {
2383 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size);
2384 ubsec_dma_free(sc, &rp->rpr_msgout);
2385 }
2386 free(rp, M_DEVBUF);
2387 }
2388 krp->krp_status = err;
2389 crypto_kdone(krp);
2390 return (0);
2391 }
2392
2393 void
ubsec_dump_pb(struct ubsec_pktbuf * pb)2394 ubsec_dump_pb(struct ubsec_pktbuf *pb)
2395 {
2396 printf("addr 0x%x (0x%x) next 0x%x\n",
2397 pb->pb_addr, pb->pb_len, pb->pb_next);
2398 }
2399
2400 void
ubsec_dump_ctx2(struct ubsec_ctx_keyop * c)2401 ubsec_dump_ctx2(struct ubsec_ctx_keyop *c)
2402 {
2403 printf("CTX (0x%x):\n", c->ctx_len);
2404 switch (letoh16(c->ctx_op)) {
2405 case UBS_CTXOP_RNGBYPASS:
2406 case UBS_CTXOP_RNGSHA1:
2407 break;
2408 case UBS_CTXOP_MODEXP:
2409 {
2410 struct ubsec_ctx_modexp *cx = (void *)c;
2411 int i, len;
2412
2413 printf(" Elen %u, Nlen %u\n",
2414 letoh16(cx->me_E_len), letoh16(cx->me_N_len));
2415 len = (cx->me_N_len + 7)/8;
2416 for (i = 0; i < len; i++)
2417 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]);
2418 printf("\n");
2419 break;
2420 }
2421 default:
2422 printf("unknown context: %x\n", c->ctx_op);
2423 }
2424 printf("END CTX\n");
2425 }
2426
2427 void
ubsec_dump_mcr(struct ubsec_mcr * mcr)2428 ubsec_dump_mcr(struct ubsec_mcr *mcr)
2429 {
2430 struct ubsec_mcr_add *ma;
2431 int i;
2432
2433 printf("MCR:\n");
2434 printf(" pkts: %u, flags 0x%x\n",
2435 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags));
2436 ma = (struct ubsec_mcr_add *)&mcr->mcr_cmdctxp;
2437 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) {
2438 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i,
2439 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen),
2440 letoh16(ma->mcr_reserved));
2441 printf(" %d: ipkt ", i);
2442 ubsec_dump_pb(&ma->mcr_ipktbuf);
2443 printf(" %d: opkt ", i);
2444 ubsec_dump_pb(&ma->mcr_opktbuf);
2445 ma++;
2446 }
2447 printf("END MCR\n");
2448 }
2449
2450 /*
2451 * Return the number of significant bits of a big number.
2452 */
2453 int
ubsec_ksigbits(struct crparam * cr)2454 ubsec_ksigbits(struct crparam *cr)
2455 {
2456 u_int plen = (cr->crp_nbits + 7) / 8;
2457 int i, sig = plen * 8;
2458 u_int8_t c, *p = cr->crp_p;
2459
2460 for (i = plen - 1; i >= 0; i--) {
2461 c = p[i];
2462 if (c != 0) {
2463 while ((c & 0x80) == 0) {
2464 sig--;
2465 c <<= 1;
2466 }
2467 break;
2468 }
2469 sig -= 8;
2470 }
2471 return (sig);
2472 }
2473
2474 void
ubsec_kshift_r(u_int shiftbits,u_int8_t * src,u_int srcbits,u_int8_t * dst,u_int dstbits)2475 ubsec_kshift_r(u_int shiftbits, u_int8_t *src, u_int srcbits,
2476 u_int8_t *dst, u_int dstbits)
2477 {
2478 u_int slen, dlen;
2479 int i, si, di, n;
2480
2481 slen = (srcbits + 7) / 8;
2482 dlen = (dstbits + 7) / 8;
2483
2484 for (i = 0; i < slen; i++)
2485 dst[i] = src[i];
2486 for (i = 0; i < dlen - slen; i++)
2487 dst[slen + i] = 0;
2488
2489 n = shiftbits / 8;
2490 if (n != 0) {
2491 si = dlen - n - 1;
2492 di = dlen - 1;
2493 while (si >= 0)
2494 dst[di--] = dst[si--];
2495 while (di >= 0)
2496 dst[di--] = 0;
2497 }
2498
2499 n = shiftbits % 8;
2500 if (n != 0) {
2501 for (i = dlen - 1; i > 0; i--)
2502 dst[i] = (dst[i] << n) |
2503 (dst[i - 1] >> (8 - n));
2504 dst[0] = dst[0] << n;
2505 }
2506 }
2507
2508 void
ubsec_kshift_l(u_int shiftbits,u_int8_t * src,u_int srcbits,u_int8_t * dst,u_int dstbits)2509 ubsec_kshift_l(u_int shiftbits, u_int8_t *src, u_int srcbits,
2510 u_int8_t *dst, u_int dstbits)
2511 {
2512 int slen, dlen, i, n;
2513
2514 slen = (srcbits + 7) / 8;
2515 dlen = (dstbits + 7) / 8;
2516
2517 n = shiftbits / 8;
2518 for (i = 0; i < slen; i++)
2519 dst[i] = src[i + n];
2520 for (i = 0; i < dlen - slen; i++)
2521 dst[slen + i] = 0;
2522
2523 n = shiftbits % 8;
2524 if (n != 0) {
2525 for (i = 0; i < (dlen - 1); i++)
2526 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n));
2527 dst[dlen - 1] = dst[dlen - 1] >> n;
2528 }
2529 }
2530