1 /* $OpenBSD: pccbb.c,v 1.35 2005/01/27 17:03:23 millert Exp $ */
2 /* $NetBSD: pccbb.c,v 1.96 2004/03/28 09:49:31 nakayama Exp $ */
3
4 /*
5 * Copyright (c) 1998, 1999 and 2000
6 * HAYAKAWA Koichi. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by HAYAKAWA Koichi.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*
35 #define CBB_DEBUG
36 #define SHOW_REGS
37 #define PCCBB_PCMCIA_POLL
38 */
39 /* #define CBB_DEBUG */
40
41 /*
42 #define CB_PCMCIA_POLL
43 #define CB_PCMCIA_POLL_ONLY
44 #define LEVEL2
45 */
46
47 #include <sys/types.h>
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/errno.h>
52 #include <sys/ioctl.h>
53 #include <sys/syslog.h>
54 #include <sys/device.h>
55 #include <sys/malloc.h>
56
57 #include <machine/intr.h>
58 #include <machine/bus.h>
59
60 #include <dev/pci/pcivar.h>
61 #include <dev/pci/pcireg.h>
62 #include <dev/pci/pcidevs.h>
63
64 #include <dev/pci/pccbbreg.h>
65
66 #include <dev/cardbus/cardslotvar.h>
67
68 #include <dev/cardbus/cardbusvar.h>
69
70 #include <dev/pcmcia/pcmciareg.h>
71 #include <dev/pcmcia/pcmciavar.h>
72
73 #include <dev/ic/i82365reg.h>
74 #include <dev/ic/i82365var.h>
75 #include <dev/pci/pccbbvar.h>
76
77 #ifndef __NetBSD_Version__
78 struct cfdriver cbb_cd = {
79 NULL, "cbb", DV_DULL
80 };
81 #endif
82
83 #if defined CBB_DEBUG
84 #define DPRINTF(x) printf x
85 #else
86 #define DPRINTF(x)
87 #endif
88
89 int pcicbbmatch(struct device *, void *, void *);
90 void pccbbattach(struct device *, struct device *, void *);
91 int pccbbintr(void *);
92 void pccbb_shutdown(void *);
93 void pci113x_insert(void *);
94 int pccbbintr_function(struct pccbb_softc *);
95
96 int pccbb_detect_card(struct pccbb_softc *);
97
98 void pccbb_pcmcia_write(struct pcic_handle *, int, int);
99 u_int8_t pccbb_pcmcia_read(struct pcic_handle *, int);
100 #define Pcic_read(ph, reg) ((ph)->ph_read((ph), (reg)))
101 #define Pcic_write(ph, reg, val) ((ph)->ph_write((ph), (reg), (val)))
102
103 int cb_reset(struct pccbb_softc *);
104 int cb_detect_voltage(struct pccbb_softc *);
105 int cbbprint(void *, const char *);
106
107 int cb_chipset(u_int32_t, int *);
108 void pccbb_pcmcia_attach_setup(struct pccbb_softc *,
109 struct pcmciabus_attach_args *);
110 #if 0
111 void pccbb_pcmcia_attach_card(struct pcic_handle *);
112 void pccbb_pcmcia_detach_card(struct pcic_handle *, int);
113 void pccbb_pcmcia_deactivate_card(struct pcic_handle *);
114 #endif
115
116 int pccbb_ctrl(cardbus_chipset_tag_t, int);
117 int pccbb_power(cardbus_chipset_tag_t, int);
118 int pccbb_cardenable(struct pccbb_softc * sc, int function);
119 #if !rbus
120 int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t);
121 int pccbb_io_close(cardbus_chipset_tag_t, int);
122 int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t);
123 int pccbb_mem_close(cardbus_chipset_tag_t, int);
124 #endif /* !rbus */
125 void *pccbb_intr_establish(struct pccbb_softc *, int irq, int level,
126 int (*ih) (void *), void *sc);
127 void pccbb_intr_disestablish(struct pccbb_softc *, void *ih);
128
129 void *pccbb_cb_intr_establish(cardbus_chipset_tag_t, int irq, int level,
130 int (*ih) (void *), void *sc);
131 void pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct, void *ih);
132
133 cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t, int, int, int);
134 void pccbb_free_tag(cardbus_chipset_tag_t, cardbustag_t);
135 cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t, cardbustag_t, int);
136 void pccbb_conf_write(cardbus_chipset_tag_t, cardbustag_t, int,
137 cardbusreg_t);
138 void pccbb_chipinit(struct pccbb_softc *);
139
140 int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t, bus_size_t,
141 struct pcmcia_mem_handle *);
142 void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t,
143 struct pcmcia_mem_handle *);
144 int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t,
145 bus_size_t, struct pcmcia_mem_handle *, bus_addr_t *, int *);
146 void pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t, int);
147 int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t, bus_addr_t,
148 bus_size_t, bus_size_t, struct pcmcia_io_handle *);
149 void pccbb_pcmcia_io_free(pcmcia_chipset_handle_t,
150 struct pcmcia_io_handle *);
151 int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t, int, bus_addr_t,
152 bus_size_t, struct pcmcia_io_handle *, int *);
153 void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t, int);
154 void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t,
155 struct pcmcia_function *, int, int (*)(void *), void *, char *);
156 void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t, void *);
157 const char *pccbb_pcmcia_intr_string(pcmcia_chipset_handle_t, void *);
158 void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t);
159 void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t);
160 int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t pch);
161
162 void pccbb_pcmcia_do_io_map(struct pcic_handle *, int);
163 void pccbb_pcmcia_wait_ready(struct pcic_handle *);
164 void pccbb_pcmcia_do_mem_map(struct pcic_handle *, int);
165 void pccbb_powerhook(int, void *);
166
167 /* bus-space allocation and deallocation functions */
168 #if rbus
169
170 int pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t, rbus_tag_t,
171 bus_addr_t addr, bus_size_t size, bus_addr_t mask, bus_size_t align,
172 int flags, bus_addr_t * addrp, bus_space_handle_t * bshp);
173 int pccbb_rbus_cb_space_free(cardbus_chipset_tag_t, rbus_tag_t,
174 bus_space_handle_t, bus_size_t);
175
176 #endif /* rbus */
177
178 #if rbus
179
180 int pccbb_open_win(struct pccbb_softc *, bus_space_tag_t,
181 bus_addr_t, bus_size_t, bus_space_handle_t, int flags);
182 int pccbb_close_win(struct pccbb_softc *, bus_space_tag_t,
183 bus_space_handle_t, bus_size_t);
184 int pccbb_winlist_insert(struct pccbb_win_chain_head *, bus_addr_t,
185 bus_size_t, bus_space_handle_t, int);
186 int pccbb_winlist_delete(struct pccbb_win_chain_head *,
187 bus_space_handle_t, bus_size_t);
188 void pccbb_winset(bus_addr_t align, struct pccbb_softc *,
189 bus_space_tag_t);
190 void pccbb_winlist_show(struct pccbb_win_chain *);
191
192 #endif /* rbus */
193
194 /* for config_defer */
195 void pccbb_pci_callback(struct device *);
196
197 #if defined SHOW_REGS
198 void cb_show_regs(pci_chipset_tag_t, pcitag_t, bus_space_tag_t,
199 bus_space_handle_t memh);
200 #endif
201
202 struct cfattach cbb_pci_ca = {
203 sizeof(struct pccbb_softc), pcicbbmatch, pccbbattach
204 };
205
206 static struct pcmcia_chip_functions pccbb_pcmcia_funcs = {
207 pccbb_pcmcia_mem_alloc,
208 pccbb_pcmcia_mem_free,
209 pccbb_pcmcia_mem_map,
210 pccbb_pcmcia_mem_unmap,
211 pccbb_pcmcia_io_alloc,
212 pccbb_pcmcia_io_free,
213 pccbb_pcmcia_io_map,
214 pccbb_pcmcia_io_unmap,
215 pccbb_pcmcia_intr_establish,
216 pccbb_pcmcia_intr_disestablish,
217 pccbb_pcmcia_intr_string,
218 pccbb_pcmcia_socket_enable,
219 pccbb_pcmcia_socket_disable,
220 pccbb_pcmcia_card_detect
221 };
222
223 #if rbus
224 static struct cardbus_functions pccbb_funcs = {
225 pccbb_rbus_cb_space_alloc,
226 pccbb_rbus_cb_space_free,
227 pccbb_cb_intr_establish,
228 pccbb_cb_intr_disestablish,
229 pccbb_ctrl,
230 pccbb_power,
231 pccbb_make_tag,
232 pccbb_free_tag,
233 pccbb_conf_read,
234 pccbb_conf_write,
235 };
236 #else
237 static struct cardbus_functions pccbb_funcs = {
238 pccbb_ctrl,
239 pccbb_power,
240 pccbb_mem_open,
241 pccbb_mem_close,
242 pccbb_io_open,
243 pccbb_io_close,
244 pccbb_cb_intr_establish,
245 pccbb_cb_intr_disestablish,
246 pccbb_make_tag,
247 pccbb_conf_read,
248 pccbb_conf_write,
249 };
250 #endif
251
252 int
pcicbbmatch(parent,match,aux)253 pcicbbmatch(parent, match, aux)
254 struct device *parent;
255 void *match;
256 void *aux;
257 {
258 struct pci_attach_args *pa = (struct pci_attach_args *)aux;
259
260 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_BRIDGE &&
261 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_BRIDGE_CARDBUS &&
262 PCI_INTERFACE(pa->pa_class) == 0) {
263 return 1;
264 }
265
266 return 0;
267 }
268
269 #define MAKEID(vendor, prod) (((vendor) << PCI_VENDOR_SHIFT) \
270 | ((prod) << PCI_PRODUCT_SHIFT))
271
272 struct yenta_chipinfo {
273 pcireg_t yc_id; /* vendor tag | product tag */
274 int yc_chiptype;
275 int yc_flags;
276 } yc_chipsets[] = {
277 /* Texas Instruments chips */
278 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1130), CB_TI113X,
279 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
280 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1131), CB_TI113X,
281 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
282 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1250), CB_TI125X,
283 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
284 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1220), CB_TI12XX,
285 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
286 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1221), CB_TI12XX,
287 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
288 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1225), CB_TI12XX,
289 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
290 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251), CB_TI125X,
291 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
292 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1251B), CB_TI125X,
293 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
294 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1211), CB_TI12XX,
295 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
296 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1410), CB_TI12XX,
297 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
298 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1420), CB_TI12XX,
299 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
300 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1450), CB_TI125X,
301 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
302 { MAKEID(PCI_VENDOR_TI, PCI_PRODUCT_TI_PCI1451), CB_TI12XX,
303 PCCBB_PCMCIA_IO_RELOC | PCCBB_PCMCIA_MEM_32},
304
305 /* Ricoh chips */
306 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C475), CB_RX5C47X,
307 PCCBB_PCMCIA_MEM_32},
308 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C476), CB_RX5C47X,
309 PCCBB_PCMCIA_MEM_32},
310 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C477), CB_RX5C47X,
311 PCCBB_PCMCIA_MEM_32},
312 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C478), CB_RX5C47X,
313 PCCBB_PCMCIA_MEM_32},
314 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C465), CB_RX5C46X,
315 PCCBB_PCMCIA_MEM_32},
316 { MAKEID(PCI_VENDOR_RICOH, PCI_PRODUCT_RICOH_RF5C466), CB_RX5C46X,
317 PCCBB_PCMCIA_MEM_32},
318
319 /* Toshiba products */
320 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95),
321 CB_TOPIC95, PCCBB_PCMCIA_MEM_32},
322 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC95B),
323 CB_TOPIC95B, PCCBB_PCMCIA_MEM_32},
324 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC97),
325 CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
326 { MAKEID(PCI_VENDOR_TOSHIBA2, PCI_PRODUCT_TOSHIBA2_ToPIC100),
327 CB_TOPIC97, PCCBB_PCMCIA_MEM_32},
328
329 /* Cirrus Logic products */
330 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6832),
331 CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
332 { MAKEID(PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CL_PD6833),
333 CB_CIRRUS, PCCBB_PCMCIA_MEM_32},
334
335 /* sentinel, or Generic chip */
336 { 0 /* null id */ , CB_UNKNOWN, PCCBB_PCMCIA_MEM_32},
337 };
338
339 int
cb_chipset(pci_id,flagp)340 cb_chipset(pci_id, flagp)
341 u_int32_t pci_id;
342 int *flagp;
343 {
344 struct yenta_chipinfo *yc;
345
346 /* Loop over except the last default entry. */
347 for (yc = yc_chipsets; yc < yc_chipsets +
348 sizeof(yc_chipsets) / sizeof(yc_chipsets[0]) - 1; yc++)
349 if (pci_id == yc->yc_id)
350 break;
351
352 if (flagp != NULL)
353 *flagp = yc->yc_flags;
354
355 return (yc->yc_chiptype);
356 }
357
358 void
pccbb_shutdown(void * arg)359 pccbb_shutdown(void *arg)
360 {
361 struct pccbb_softc *sc = arg;
362 pcireg_t command;
363
364 DPRINTF(("%s: shutdown\n", sc->sc_dev.dv_xname));
365
366 /* turn off power */
367 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
368
369 bus_space_write_4(sc->sc_base_memt, sc->sc_base_memh, CB_SOCKET_MASK,
370 0);
371
372 command = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
373
374 command &= ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
375 PCI_COMMAND_MASTER_ENABLE);
376 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
377 }
378
379 void
pccbbattach(parent,self,aux)380 pccbbattach(parent, self, aux)
381 struct device *parent;
382 struct device *self;
383 void *aux;
384 {
385 struct pccbb_softc *sc = (void *)self;
386 struct pci_attach_args *pa = aux;
387 pci_chipset_tag_t pc = pa->pa_pc;
388 pcireg_t busreg, reg, sock_base;
389 pci_intr_handle_t ih;
390 const char *intrstr = NULL;
391 bus_addr_t sockbase;
392 int flags;
393
394 sc->sc_chipset = cb_chipset(pa->pa_id, &flags);
395
396 #ifdef CBB_DEBUG
397 printf(" (chipflags %x)", flags);
398 #endif
399
400 TAILQ_INIT(&sc->sc_memwindow);
401 TAILQ_INIT(&sc->sc_iowindow);
402
403 #if rbus
404 sc->sc_rbus_iot = rbus_pccbb_parent_io(self, pa);
405 sc->sc_rbus_memt = rbus_pccbb_parent_mem(self, pa);
406 #endif /* rbus */
407
408 sc->sc_base_memh = 0;
409
410 /*
411 * MAP socket registers and ExCA registers on memory-space
412 * When no valid address is set on socket base registers (on pci
413 * config space), get it not polite way.
414 */
415 sock_base = pci_conf_read(pc, pa->pa_tag, PCI_SOCKBASE);
416
417 if (PCI_MAPREG_MEM_ADDR(sock_base) >= 0x100000 &&
418 PCI_MAPREG_MEM_ADDR(sock_base) != 0xfffffff0) {
419 /* The address must be valid. */
420 if (pci_mapreg_map(pa, PCI_SOCKBASE, PCI_MAPREG_TYPE_MEM, 0,
421 &sc->sc_base_memt, &sc->sc_base_memh, &sockbase, NULL, 0))
422 {
423 printf("%s: can't map socket base address 0x%x\n",
424 sc->sc_dev.dv_xname, sock_base);
425 /*
426 * I think it's funny: socket base registers must be
427 * mapped on memory space, but ...
428 */
429 if (pci_mapreg_map(pa, PCI_SOCKBASE,
430 PCI_MAPREG_TYPE_IO, 0, &sc->sc_base_memt,
431 &sc->sc_base_memh, &sockbase, NULL, 0)) {
432 printf("%s: can't map socket base address"
433 " 0x%lx: io mode\n", sc->sc_dev.dv_xname,
434 sockbase);
435 /* give up... allocate reg space via rbus. */
436 sc->sc_base_memh = 0;
437 pci_conf_write(pc, pa->pa_tag, PCI_SOCKBASE, 0);
438 }
439 } else {
440 DPRINTF(("%s: socket base address 0x%lx\n",
441 sc->sc_dev.dv_xname, sockbase));
442 }
443 }
444
445 sc->sc_mem_start = 0; /* XXX */
446 sc->sc_mem_end = 0xffffffff; /* XXX */
447
448 /*
449 * When bus number isn't set correctly, give up using 32-bit CardBus
450 * mode.
451 */
452 busreg = pci_conf_read(pc, pa->pa_tag, PCI_BUSNUM);
453 #if notyet
454 if (((busreg >> 8) & 0xff) == 0) {
455 printf(": CardBus support disabled because of unconfigured bus number\n");
456 flags |= PCCBB_PCMCIA_16BITONLY;
457 }
458 #endif
459
460 /* pccbb_machdep.c end */
461
462 #if defined CBB_DEBUG
463 {
464 static char *intrname[5] = { "NON", "A", "B", "C", "D" };
465 printf(": intrpin %s, intrtag %d\n",
466 intrname[pa->pa_intrpin], pa->pa_intrline);
467 }
468 #endif
469
470 /* setup softc */
471 sc->sc_pc = pc;
472 sc->sc_iot = pa->pa_iot;
473 sc->sc_memt = pa->pa_memt;
474 sc->sc_dmat = pa->pa_dmat;
475 sc->sc_tag = pa->pa_tag;
476 sc->sc_function = pa->pa_function;
477 sc->sc_sockbase = sock_base;
478 sc->sc_busnum = busreg;
479 sc->sc_intrtag = pa->pa_intrtag;
480 sc->sc_intrpin = pa->pa_intrpin;
481
482 sc->sc_pcmcia_flags = flags; /* set PCMCIA facility */
483
484 /* Map and establish the interrupt. */
485 if (pci_intr_map(pa, &ih)) {
486 printf(": couldn't map interrupt\n");
487 return;
488 }
489 intrstr = pci_intr_string(pc, ih);
490 /* must do this after intr is mapped and established */
491 sc->sc_intrline = pci_intr_line(ih);
492
493 /*
494 * XXX pccbbintr should be called under the priority lower
495 * than any other hard interrputs.
496 */
497 sc->sc_ih = pci_intr_establish(pc, ih, IPL_BIO, pccbbintr, sc,
498 sc->sc_dev.dv_xname);
499
500 if (sc->sc_ih == NULL) {
501 printf(": couldn't establish interrupt");
502 if (intrstr != NULL) {
503 printf(" at %s", intrstr);
504 }
505 printf("\n");
506 return;
507 }
508 printf(": %s\n", intrstr);
509
510 shutdownhook_establish(pccbb_shutdown, sc);
511
512 /* Disable legacy register mapping. */
513 switch (sc->sc_chipset) {
514 case CB_RX5C46X: /* fallthrough */
515 #if 0
516 /* The RX5C47X-series requires writes to the PCI_LEGACY register. */
517 case CB_RX5C47X:
518 #endif
519 /*
520 * The legacy pcic io-port on Ricoh RX5C46X CardBus bridges
521 * cannot be disabled by substituting 0 into PCI_LEGACY
522 * register. Ricoh CardBus bridges have special bits on Bridge
523 * control reg (addr 0x3e on PCI config space).
524 */
525 reg = pci_conf_read(pc, pa->pa_tag, PCI_BCR_INTR);
526 reg &= ~(CB_BCRI_RL_3E0_ENA | CB_BCRI_RL_3E2_ENA);
527 pci_conf_write(pc, pa->pa_tag, PCI_BCR_INTR, reg);
528 break;
529
530 default:
531 /* XXX I don't know proper way to kill legacy I/O. */
532 pci_conf_write(pc, pa->pa_tag, PCI_LEGACY, 0x0);
533 break;
534 }
535
536 timeout_set(&sc->sc_ins_tmo, pci113x_insert, sc);
537 config_defer(self, pccbb_pci_callback);
538 }
539
540
541
542
543 /*
544 * void pccbb_pci_callback(struct device *self)
545 *
546 * The actual attach routine: get memory space for YENTA register
547 * space, setup YENTA register and route interrupt.
548 *
549 * This function should be deferred because this device may obtain
550 * memory space dynamically. This function must avoid obtaining
551 * memory area which has already kept for another device. Also,
552 * this function MUST be done before ISA attach process because this
553 * function kills pcic compatible port used by ISA pcic.
554 */
555 void
pccbb_pci_callback(self)556 pccbb_pci_callback(self)
557 struct device *self;
558 {
559 struct pccbb_softc *sc = (void *)self;
560 pci_chipset_tag_t pc = sc->sc_pc;
561 bus_space_tag_t base_memt;
562 bus_space_handle_t base_memh;
563 u_int32_t maskreg;
564 bus_addr_t sockbase;
565 struct cbslot_attach_args cba;
566 struct pcmciabus_attach_args paa;
567 struct cardslot_attach_args caa;
568 struct cardslot_softc *csc;
569
570 if (0 == sc->sc_base_memh) {
571 /* The socket registers aren't mapped correctly. */
572 #if rbus
573 if (rbus_space_alloc(sc->sc_rbus_memt, 0, 0x1000, 0x0fff,
574 (sc->sc_chipset == CB_RX5C47X
575 || sc->sc_chipset == CB_TI113X) ? 0x10000 : 0x1000,
576 0, &sockbase, &sc->sc_base_memh)) {
577 return;
578 }
579 sc->sc_base_memt = sc->sc_memt;
580 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
581 DPRINTF(("%s: CardBus resister address 0x%lx -> 0x%x\n",
582 sc->sc_dev.dv_xname, sockbase, pci_conf_read(pc, sc->sc_tag,
583 PCI_SOCKBASE)));
584 #else
585 sc->sc_base_memt = sc->sc_memt;
586 #if !defined CBB_PCI_BASE
587 #define CBB_PCI_BASE 0x20000000
588 #endif
589 if (bus_space_alloc(sc->sc_base_memt, CBB_PCI_BASE, 0xffffffff,
590 0x1000, 0x1000, 0, 0, &sockbase, &sc->sc_base_memh)) {
591 /* cannot allocate memory space */
592 return;
593 }
594 pci_conf_write(pc, sc->sc_tag, PCI_SOCKBASE, sockbase);
595 DPRINTF(("%s: CardBus resister address 0x%x -> 0x%x\n",
596 sc->sc_dev.dv_xname, sock_base, pci_conf_read(pc,
597 sc->sc_tag, PCI_SOCKBASE)));
598 #endif
599 }
600
601 /* bus bridge initialization */
602 pccbb_chipinit(sc);
603
604 base_memt = sc->sc_base_memt; /* socket regs memory tag */
605 base_memh = sc->sc_base_memh; /* socket regs memory handle */
606
607 /* clear data structure for child device interrupt handlers */
608 sc->sc_pil = NULL;
609 sc->sc_pil_intr_enable = 1;
610
611 powerhook_establish(pccbb_powerhook, sc);
612
613 {
614 u_int32_t sockstat =
615 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
616 if (0 == (sockstat & CB_SOCKET_STAT_CD)) {
617 sc->sc_flags |= CBB_CARDEXIST;
618 }
619 }
620
621 /*
622 * attach cardbus
623 */
624 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {
625 pcireg_t busreg = pci_conf_read(pc, sc->sc_tag, PCI_BUSNUM);
626 pcireg_t bhlc = pci_conf_read(pc, sc->sc_tag, PCI_BHLC_REG);
627
628 /* initialize cbslot_attach */
629 cba.cba_busname = "cardbus";
630 cba.cba_iot = sc->sc_iot;
631 cba.cba_memt = sc->sc_memt;
632 cba.cba_dmat = sc->sc_dmat;
633 cba.cba_bus = (busreg >> 8) & 0x0ff;
634 cba.cba_cc = (void *)sc;
635 cba.cba_cf = &pccbb_funcs;
636 cba.cba_intrline = sc->sc_intrline;
637
638 #if rbus
639 cba.cba_rbus_iot = sc->sc_rbus_iot;
640 cba.cba_rbus_memt = sc->sc_rbus_memt;
641 #endif
642
643 cba.cba_cacheline = PCI_CACHELINE(bhlc);
644 cba.cba_lattimer = PCI_CB_LATENCY(busreg);
645
646 #if defined CBB_DEBUG
647 printf("%s: cacheline 0x%x lattimer 0x%x\n",
648 sc->sc_dev.dv_xname, cba.cba_cacheline, cba.cba_lattimer);
649 printf("%s: bhlc 0x%x lscp 0x%x\n", sc->sc_dev.dv_xname, bhlc,
650 busreg);
651 #endif
652 #if defined SHOW_REGS
653 cb_show_regs(sc->sc_pc, sc->sc_tag, sc->sc_base_memt,
654 sc->sc_base_memh);
655 #endif
656 }
657
658 pccbb_pcmcia_attach_setup(sc, &paa);
659 caa.caa_cb_attach = NULL;
660 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_16BITONLY)) {
661 caa.caa_cb_attach = &cba;
662 }
663 caa.caa_16_attach = &paa;
664 caa.caa_ph = &sc->sc_pcmcia_h;
665
666 if (NULL != (csc = (void *)config_found(self, &caa, cbbprint))) {
667 DPRINTF(("pccbbattach: found cardslot\n"));
668 sc->sc_csc = csc;
669 }
670
671 sc->sc_ints_on = 1;
672
673 /* CSC Interrupt: Card detect interrupt on */
674 maskreg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
675 maskreg |= CB_SOCKET_MASK_CD; /* Card detect intr is turned on. */
676 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, maskreg);
677 /* reset interrupt */
678 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT,
679 bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT));
680
681 return;
682 }
683
684
685
686
687
688 /*
689 * void pccbb_chipinit(struct pccbb_softc *sc)
690 *
691 * This function initialize YENTA chip registers listed below:
692 * 1) PCI command reg,
693 * 2) PCI and CardBus latency timer,
694 * 3) route PCI interrupt,
695 * 4) close all memory and io windows.
696 */
697 void
pccbb_chipinit(sc)698 pccbb_chipinit(sc)
699 struct pccbb_softc *sc;
700 {
701 pci_chipset_tag_t pc = sc->sc_pc;
702 pcitag_t tag = sc->sc_tag;
703 pcireg_t reg;
704
705 /*
706 * Set PCI command reg.
707 * Some laptop's BIOSes (i.e. TICO) do not enable CardBus chip.
708 */
709 reg = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
710 /* I believe it is harmless. */
711 reg |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
712 PCI_COMMAND_MASTER_ENABLE);
713 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, reg);
714
715 /*
716 * Set CardBus latency timer.
717 */
718 reg = pci_conf_read(pc, tag, PCI_CB_LSCP_REG);
719 if (PCI_CB_LATENCY(reg) < 0x20) {
720 reg &= ~(PCI_CB_LATENCY_MASK << PCI_CB_LATENCY_SHIFT);
721 reg |= (0x20 << PCI_CB_LATENCY_SHIFT);
722 pci_conf_write(pc, tag, PCI_CB_LSCP_REG, reg);
723 }
724 DPRINTF(("CardBus latency timer 0x%x (%x)\n",
725 PCI_CB_LATENCY(reg), pci_conf_read(pc, tag, PCI_CB_LSCP_REG)));
726
727 /*
728 * Set PCI latency timer.
729 */
730 reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
731 if (PCI_LATTIMER(reg) < 0x10) {
732 reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
733 reg |= (0x10 << PCI_LATTIMER_SHIFT);
734 pci_conf_write(pc, tag, PCI_BHLC_REG, reg);
735 }
736 DPRINTF(("PCI latency timer 0x%x (%x)\n",
737 PCI_LATTIMER(reg), pci_conf_read(pc, tag, PCI_BHLC_REG)));
738
739 /* Route functional interrupts to PCI. */
740 reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
741 reg |= CB_BCR_INTR_IREQ_ENABLE; /* disable PCI Intr */
742 reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
743 reg |= CB_BCR_RESET_ENABLE; /* assert reset */
744 pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
745
746 switch (sc->sc_chipset) {
747 case CB_TI113X:
748 reg = pci_conf_read(pc, tag, PCI_CBCTRL);
749 /* This bit is shared, but may read as 0 on some chips, so set
750 it explicitly on both functions. */
751 reg |= PCI113X_CBCTRL_PCI_IRQ_ENA;
752 /* CSC intr enable */
753 reg |= PCI113X_CBCTRL_PCI_CSC;
754 /* functional intr prohibit | prohibit ISA routing */
755 reg &= ~(PCI113X_CBCTRL_PCI_INTR | PCI113X_CBCTRL_INT_MASK);
756 pci_conf_write(pc, tag, PCI_CBCTRL, reg);
757 break;
758
759 case CB_TI12XX:
760 /*
761 * Some TI 12xx (and [14][45]xx) based pci cards
762 * sometimes have issues with the MFUNC register not
763 * being initialized due to a bad EEPROM on board.
764 * Laptops that this matters on have this register
765 * properly initialized.
766 *
767 * The TI125X parts have a different register.
768 */
769 reg = pci_conf_read(pc, tag, PCI12XX_MFUNC);
770 if (reg == 0) {
771 reg &= ~PCI12XX_MFUNC_PIN0;
772 reg |= PCI12XX_MFUNC_PIN0_INTA;
773 if ((pci_conf_read(pc, tag, PCI_SYSCTRL) &
774 PCI12XX_SYSCTRL_INTRTIE) == 0) {
775 reg &= ~PCI12XX_MFUNC_PIN1;
776 reg |= PCI12XX_MFUNC_PIN1_INTB;
777 }
778 pci_conf_write(pc, tag, PCI12XX_MFUNC, reg);
779 }
780 /* fallthrough */
781
782 case CB_TI125X:
783 /*
784 * Disable zoom video. Some machines initialize this
785 * improperly and experience has shown that this helps
786 * prevent strange behavior.
787 */
788 pci_conf_write(pc, tag, PCI12XX_MMCTRL, 0);
789
790 reg = pci_conf_read(pc, tag, PCI_SYSCTRL);
791 reg |= PCI12XX_SYSCTRL_VCCPROT;
792 pci_conf_write(pc, tag, PCI_SYSCTRL, reg);
793 reg = pci_conf_read(pc, tag, PCI_CBCTRL);
794 reg |= PCI12XX_CBCTRL_CSC;
795 pci_conf_write(pc, tag, PCI_CBCTRL, reg);
796 break;
797
798 case CB_TOPIC95B:
799 reg = pci_conf_read(pc, tag, TOPIC_SOCKET_CTRL);
800 reg |= TOPIC_SOCKET_CTRL_SCR_IRQSEL;
801 pci_conf_write(pc, tag, TOPIC_SOCKET_CTRL, reg);
802
803 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
804 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
805 sc->sc_dev.dv_xname, reg));
806 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
807 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
808 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
809 DPRINTF(("0x%x\n", reg));
810 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
811 break;
812
813 case CB_TOPIC97:
814 reg = pci_conf_read(pc, tag, TOPIC_SLOT_CTRL);
815 DPRINTF(("%s: topic slot ctrl reg 0x%x -> ",
816 sc->sc_dev.dv_xname, reg));
817 reg |= (TOPIC_SLOT_CTRL_SLOTON | TOPIC_SLOT_CTRL_SLOTEN |
818 TOPIC_SLOT_CTRL_ID_LOCK | TOPIC_SLOT_CTRL_CARDBUS);
819 reg &= ~TOPIC_SLOT_CTRL_SWDETECT;
820 reg |= TOPIC97_SLOT_CTRL_PCIINT;
821 reg &= ~(TOPIC97_SLOT_CTRL_STSIRQP | TOPIC97_SLOT_CTRL_IRQP);
822 DPRINTF(("0x%x\n", reg));
823 pci_conf_write(pc, tag, TOPIC_SLOT_CTRL, reg);
824
825 /* make sure to assert LV card support bits */
826 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
827 0x800 + 0x3e, bus_space_read_1(sc->sc_base_memt,
828 sc->sc_base_memh, 0x800 + 0x3e) | 0x03);
829
830 /* Power on the controller if the BIOS didn't */
831 reg = pci_conf_read(pc, tag, TOPIC100_PMCSR);
832 if ((reg & TOPIC100_PMCSR_MASK) != TOPIC100_PMCSR_D0)
833 pci_conf_write(pc, tag, TOPIC100_PMCSR,
834 (reg & ~TOPIC100_PMCSR_MASK) | TOPIC100_PMCSR_D0);
835 break;
836 }
837
838 /* Close all memory and I/O windows. */
839 pci_conf_write(pc, tag, PCI_CB_MEMBASE0, 0xffffffff);
840 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT0, 0);
841 pci_conf_write(pc, tag, PCI_CB_MEMBASE1, 0xffffffff);
842 pci_conf_write(pc, tag, PCI_CB_MEMLIMIT1, 0);
843 pci_conf_write(pc, tag, PCI_CB_IOBASE0, 0xffffffff);
844 pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
845 pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
846 pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
847
848 /* reset 16-bit pcmcia bus */
849 bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
850 0x800 + PCIC_INTR,
851 bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
852 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
853
854 /* turn off power */
855 pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
856 }
857
858
859
860
861 /*
862 * void pccbb_pcmcia_attach_setup(struct pccbb_softc *sc,
863 * struct pcmciabus_attach_args *paa)
864 *
865 * This function attaches 16-bit PCcard bus.
866 */
867 void
pccbb_pcmcia_attach_setup(sc,paa)868 pccbb_pcmcia_attach_setup(sc, paa)
869 struct pccbb_softc *sc;
870 struct pcmciabus_attach_args *paa;
871 {
872 struct pcic_handle *ph = &sc->sc_pcmcia_h;
873 #if rbus
874 rbus_tag_t rb;
875 #endif
876
877 /* initialize pcmcia part in pccbb_softc */
878 ph->ph_parent = (struct device *)sc;
879 ph->sock = sc->sc_function;
880 ph->flags = 0;
881 ph->shutdown = 0;
882 ph->ih_irq = sc->sc_intrline;
883 ph->ph_bus_t = sc->sc_base_memt;
884 ph->ph_bus_h = sc->sc_base_memh;
885 ph->ph_read = pccbb_pcmcia_read;
886 ph->ph_write = pccbb_pcmcia_write;
887 sc->sc_pct = &pccbb_pcmcia_funcs;
888
889 /*
890 * We need to do a few things here:
891 * 1) Disable routing of CSC and functional interrupts to ISA IRQs by
892 * setting the IRQ numbers to 0.
893 * 2) Set bit 4 of PCIC_INTR, which is needed on some chips to enable
894 * routing of CSC interrupts (e.g. card removal) to PCI while in
895 * PCMCIA mode. We just leave this set all the time.
896 * 3) Enable card insertion/removal interrupts in case the chip also
897 * needs that while in PCMCIA mode.
898 * 4) Clear any pending CSC interrupt.
899 */
900 Pcic_write(ph, PCIC_INTR, PCIC_INTR_ENABLE | PCIC_INTR_RESET);
901 if (sc->sc_chipset == CB_TI113X) {
902 Pcic_write(ph, PCIC_CSC_INTR, 0);
903 } else {
904 Pcic_write(ph, PCIC_CSC_INTR, PCIC_CSC_INTR_CD_ENABLE);
905 Pcic_read(ph, PCIC_CSC);
906 }
907
908 /* initialize pcmcia bus attachment */
909 paa->paa_busname = "pcmcia";
910 paa->pct = sc->sc_pct;
911 paa->pch = ph;
912 paa->iobase = 0; /* I don't use them */
913 paa->iosize = 0;
914 #if rbus
915 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
916 paa->iobase = rb->rb_start + rb->rb_offset;
917 paa->iosize = rb->rb_end - rb->rb_start;
918 #endif
919
920 return;
921 }
922
923 #if 0
924 void
925 pccbb_pcmcia_attach_card(ph)
926 struct pcic_handle *ph;
927 {
928 if (ph->flags & PCIC_FLAG_CARDP) {
929 panic("pccbb_pcmcia_attach_card: already attached");
930 }
931
932 /* call the MI attach function */
933 pcmcia_card_attach(ph->pcmcia);
934
935 ph->flags |= PCIC_FLAG_CARDP;
936 }
937
938 void
939 pccbb_pcmcia_detach_card(ph, flags)
940 struct pcic_handle *ph;
941 int flags;
942 {
943 if (!(ph->flags & PCIC_FLAG_CARDP)) {
944 panic("pccbb_pcmcia_detach_card: already detached");
945 }
946
947 ph->flags &= ~PCIC_FLAG_CARDP;
948
949 /* call the MI detach function */
950 pcmcia_card_detach(ph->pcmcia, flags);
951 }
952 #endif
953
954 /*
955 * int pccbbintr(arg)
956 * void *arg;
957 * This routine handles the interrupt from Yenta PCI-CardBus bridge
958 * itself.
959 */
960 int
pccbbintr(arg)961 pccbbintr(arg)
962 void *arg;
963 {
964 struct pccbb_softc *sc = (struct pccbb_softc *)arg;
965 u_int32_t sockevent, sockstate;
966 bus_space_tag_t memt = sc->sc_base_memt;
967 bus_space_handle_t memh = sc->sc_base_memh;
968 struct pcic_handle *ph = &sc->sc_pcmcia_h;
969
970 if (!sc->sc_ints_on)
971 return 0;
972
973 sockevent = bus_space_read_4(memt, memh, CB_SOCKET_EVENT);
974 bus_space_write_4(memt, memh, CB_SOCKET_EVENT, sockevent);
975 Pcic_read(ph, PCIC_CSC);
976
977 if (sockevent == 0) {
978 /* This intr is not for me: it may be for my child devices. */
979 if (sc->sc_pil_intr_enable) {
980 return pccbbintr_function(sc);
981 } else {
982 return 0;
983 }
984 }
985
986 if (sockevent & CB_SOCKET_EVENT_CD) {
987 sockstate = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
988 if (CB_SOCKET_STAT_CD == (sockstate & CB_SOCKET_STAT_CD)) {
989 /* A card should be removed. */
990 if (sc->sc_flags & CBB_CARDEXIST) {
991 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname,
992 sockevent));
993 DPRINTF((" card removed, 0x%08x\n", sockstate));
994 sc->sc_flags &= ~CBB_CARDEXIST;
995 if (sc->sc_csc->sc_status &
996 CARDSLOT_STATUS_CARD_16) {
997 #if 0
998 struct pcic_handle *ph =
999 &sc->sc_pcmcia_h;
1000
1001 pcmcia_card_deactivate(ph->pcmcia);
1002 pccbb_pcmcia_socket_disable(ph);
1003 pccbb_pcmcia_detach_card(ph,
1004 DETACH_FORCE);
1005 #endif
1006 cardslot_event_throw(sc->sc_csc,
1007 CARDSLOT_EVENT_REMOVAL_16);
1008 } else if (sc->sc_csc->sc_status &
1009 CARDSLOT_STATUS_CARD_CB) {
1010 /* Cardbus intr removed */
1011 cardslot_event_throw(sc->sc_csc,
1012 CARDSLOT_EVENT_REMOVAL_CB);
1013 }
1014 }
1015 } else if (0x00 == (sockstate & CB_SOCKET_STAT_CD) &&
1016 /*
1017 * The pccbbintr may called from powerdown hook when
1018 * the system resumed, to detect the card
1019 * insertion/removal during suspension.
1020 */
1021 (sc->sc_flags & CBB_CARDEXIST) == 0) {
1022 if (sc->sc_flags & CBB_INSERTING) {
1023 timeout_del(&sc->sc_ins_tmo);
1024 }
1025 timeout_add(&sc->sc_ins_tmo, hz / 10);
1026 sc->sc_flags |= CBB_INSERTING;
1027 }
1028 }
1029
1030 return (1);
1031 }
1032
1033 /*
1034 * int pccbbintr_function(struct pccbb_softc *sc)
1035 *
1036 * This function calls each interrupt handler registered at the
1037 * bridge. The interrupt handlers are called in registered order.
1038 */
1039 int
pccbbintr_function(sc)1040 pccbbintr_function(sc)
1041 struct pccbb_softc *sc;
1042 {
1043 int retval = 0, val;
1044 struct pccbb_intrhand_list *pil;
1045 int s, splchanged;
1046
1047 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {
1048 /*
1049 * XXX priority change. gross. I use if-else
1050 * sentense instead of switch-case sentense because of
1051 * avoiding duplicate case value error. More than one
1052 * IPL_XXX use same value. It depends on
1053 * implementation.
1054 */
1055 splchanged = 1;
1056 #if 0
1057 if (pil->pil_level == IPL_SERIAL) {
1058 s = splserial();
1059 } else if (pil->pil_level == IPL_HIGH) {
1060 #endif
1061 if (pil->pil_level == IPL_HIGH) {
1062 s = splhigh();
1063 } else if (pil->pil_level == IPL_CLOCK) {
1064 s = splclock();
1065 } else if (pil->pil_level == IPL_AUDIO) {
1066 s = splaudio();
1067 #ifdef IPL_IMP
1068 } else if (pil->pil_level == IPL_IMP) {
1069 s = splimp();
1070 #endif
1071 } else if (pil->pil_level == IPL_TTY) {
1072 s = spltty();
1073 #if 0
1074 } else if (pil->pil_level == IPL_SOFTSERIAL) {
1075 s = splsoftserial();
1076 #endif
1077 } else if (pil->pil_level == IPL_NET) {
1078 s = splnet();
1079 } else {
1080 splchanged = 0;
1081 /* XXX: ih lower than IPL_BIO runs w/ IPL_BIO. */
1082 }
1083
1084 val = (*pil->pil_func)(pil->pil_arg);
1085
1086 if (splchanged != 0) {
1087 splx(s);
1088 }
1089
1090 retval = retval == 1 ? 1 :
1091 retval == 0 ? val : val != 0 ? val : retval;
1092 }
1093
1094 return retval;
1095 }
1096
1097 void
pci113x_insert(arg)1098 pci113x_insert(arg)
1099 void *arg;
1100 {
1101 struct pccbb_softc *sc = (struct pccbb_softc *)arg;
1102 u_int32_t sockevent, sockstate;
1103
1104 sockevent = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1105 CB_SOCKET_EVENT);
1106 sockstate = bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1107 CB_SOCKET_STAT);
1108
1109 if (0 == (sockstate & CB_SOCKET_STAT_CD)) { /* card exist */
1110 DPRINTF(("%s: 0x%08x", sc->sc_dev.dv_xname, sockevent));
1111 DPRINTF((" card inserted, 0x%08x\n", sockstate));
1112 sc->sc_flags |= CBB_CARDEXIST;
1113 /* call pccard interrupt handler here */
1114 if (sockstate & CB_SOCKET_STAT_16BIT) {
1115 /* 16-bit card found */
1116 /* pccbb_pcmcia_attach_card(&sc->sc_pcmcia_h); */
1117 cardslot_event_throw(sc->sc_csc,
1118 CARDSLOT_EVENT_INSERTION_16);
1119 } else if (sockstate & CB_SOCKET_STAT_CB) {
1120 /* cardbus card found */
1121 /* cardbus_attach_card(sc->sc_csc); */
1122 cardslot_event_throw(sc->sc_csc,
1123 CARDSLOT_EVENT_INSERTION_CB);
1124 } else {
1125 /* who are you? */
1126 }
1127 } else {
1128 timeout_add(&sc->sc_ins_tmo, hz / 10);
1129 }
1130 }
1131
1132 #define PCCBB_PCMCIA_OFFSET 0x800
1133 u_int8_t
pccbb_pcmcia_read(ph,reg)1134 pccbb_pcmcia_read(ph, reg)
1135 struct pcic_handle *ph;
1136 int reg;
1137 {
1138 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
1139 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_READ);
1140
1141 return bus_space_read_1(ph->ph_bus_t, ph->ph_bus_h,
1142 PCCBB_PCMCIA_OFFSET + reg);
1143 }
1144
1145 void
pccbb_pcmcia_write(ph,reg,val)1146 pccbb_pcmcia_write(ph, reg, val)
1147 struct pcic_handle *ph;
1148 int reg;
1149 u_int8_t val;
1150 {
1151 bus_space_barrier(ph->ph_bus_t, ph->ph_bus_h,
1152 PCCBB_PCMCIA_OFFSET + reg, 1, BUS_SPACE_BARRIER_WRITE);
1153
1154 bus_space_write_1(ph->ph_bus_t, ph->ph_bus_h, PCCBB_PCMCIA_OFFSET + reg,
1155 val);
1156 }
1157
1158 /*
1159 * int pccbb_ctrl(cardbus_chipset_tag_t, int)
1160 */
1161 int
pccbb_ctrl(ct,command)1162 pccbb_ctrl(ct, command)
1163 cardbus_chipset_tag_t ct;
1164 int command;
1165 {
1166 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1167
1168 switch (command) {
1169 case CARDBUS_CD:
1170 if (2 == pccbb_detect_card(sc)) {
1171 int retval = 0;
1172 int status = cb_detect_voltage(sc);
1173 if (PCCARD_VCC_5V & status) {
1174 retval |= CARDBUS_5V_CARD;
1175 }
1176 if (PCCARD_VCC_3V & status) {
1177 retval |= CARDBUS_3V_CARD;
1178 }
1179 if (PCCARD_VCC_XV & status) {
1180 retval |= CARDBUS_XV_CARD;
1181 }
1182 if (PCCARD_VCC_YV & status) {
1183 retval |= CARDBUS_YV_CARD;
1184 }
1185 return retval;
1186 } else {
1187 return 0;
1188 }
1189 break;
1190 case CARDBUS_RESET:
1191 return cb_reset(sc);
1192 break;
1193 case CARDBUS_IO_ENABLE: /* fallthrough */
1194 case CARDBUS_IO_DISABLE: /* fallthrough */
1195 case CARDBUS_MEM_ENABLE: /* fallthrough */
1196 case CARDBUS_MEM_DISABLE: /* fallthrough */
1197 case CARDBUS_BM_ENABLE: /* fallthrough */
1198 case CARDBUS_BM_DISABLE: /* fallthrough */
1199 return pccbb_cardenable(sc, command);
1200 break;
1201 }
1202
1203 return 0;
1204 }
1205
1206 /*
1207 * int pccbb_power(cardbus_chipset_tag_t, int)
1208 * This function returns true when it succeeds and returns false when
1209 * it fails.
1210 */
1211 int
pccbb_power(ct,command)1212 pccbb_power(ct, command)
1213 cardbus_chipset_tag_t ct;
1214 int command;
1215 {
1216 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1217
1218 u_int32_t status, sock_ctrl;
1219 bus_space_tag_t memt = sc->sc_base_memt;
1220 bus_space_handle_t memh = sc->sc_base_memh;
1221
1222 DPRINTF(("pccbb_power: %s and %s [%x]\n",
1223 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" :
1224 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" :
1225 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" :
1226 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" :
1227 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" :
1228 (command & CARDBUS_VCCMASK) == CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" :
1229 "UNKNOWN",
1230 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" :
1231 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" :
1232 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" :
1233 (command & CARDBUS_VPPMASK) == CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" :
1234 "UNKNOWN", command));
1235
1236 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1237 sock_ctrl = bus_space_read_4(memt, memh, CB_SOCKET_CTRL);
1238
1239 switch (command & CARDBUS_VCCMASK) {
1240 case CARDBUS_VCC_UC:
1241 break;
1242 case CARDBUS_VCC_5V:
1243 if (CB_SOCKET_STAT_5VCARD & status) { /* check 5 V card */
1244 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1245 sock_ctrl |= CB_SOCKET_CTRL_VCC_5V;
1246 } else {
1247 printf("%s: BAD voltage request: no 5 V card\n",
1248 sc->sc_dev.dv_xname);
1249 }
1250 break;
1251 case CARDBUS_VCC_3V:
1252 if (CB_SOCKET_STAT_3VCARD & status) {
1253 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1254 sock_ctrl |= CB_SOCKET_CTRL_VCC_3V;
1255 } else {
1256 printf("%s: BAD voltage request: no 3.3 V card\n",
1257 sc->sc_dev.dv_xname);
1258 }
1259 break;
1260 case CARDBUS_VCC_0V:
1261 sock_ctrl &= ~CB_SOCKET_CTRL_VCCMASK;
1262 break;
1263 default:
1264 return 0; /* power NEVER changed */
1265 break;
1266 }
1267
1268 switch (command & CARDBUS_VPPMASK) {
1269 case CARDBUS_VPP_UC:
1270 break;
1271 case CARDBUS_VPP_0V:
1272 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1273 break;
1274 case CARDBUS_VPP_VCC:
1275 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1276 sock_ctrl |= ((sock_ctrl >> 4) & 0x07);
1277 break;
1278 case CARDBUS_VPP_12V:
1279 sock_ctrl &= ~CB_SOCKET_CTRL_VPPMASK;
1280 sock_ctrl |= CB_SOCKET_CTRL_VPP_12V;
1281 break;
1282 }
1283
1284 #if 0
1285 DPRINTF(("sock_ctrl: %x\n", sock_ctrl));
1286 #endif
1287 bus_space_write_4(memt, memh, CB_SOCKET_CTRL, sock_ctrl);
1288 status = bus_space_read_4(memt, memh, CB_SOCKET_STAT);
1289
1290 if (status & CB_SOCKET_STAT_BADVCC) { /* bad Vcc request */
1291 printf
1292 ("%s: bad Vcc request. sock_ctrl 0x%x, sock_status 0x%x\n",
1293 sc->sc_dev.dv_xname, sock_ctrl, status);
1294 DPRINTF(("pccbb_power: %s and %s [%x]\n",
1295 (command & CARDBUS_VCCMASK) ==
1296 CARDBUS_VCC_UC ? "CARDBUS_VCC_UC" : (command &
1297 CARDBUS_VCCMASK) ==
1298 CARDBUS_VCC_5V ? "CARDBUS_VCC_5V" : (command &
1299 CARDBUS_VCCMASK) ==
1300 CARDBUS_VCC_3V ? "CARDBUS_VCC_3V" : (command &
1301 CARDBUS_VCCMASK) ==
1302 CARDBUS_VCC_XV ? "CARDBUS_VCC_XV" : (command &
1303 CARDBUS_VCCMASK) ==
1304 CARDBUS_VCC_YV ? "CARDBUS_VCC_YV" : (command &
1305 CARDBUS_VCCMASK) ==
1306 CARDBUS_VCC_0V ? "CARDBUS_VCC_0V" : "UNKNOWN",
1307 (command & CARDBUS_VPPMASK) ==
1308 CARDBUS_VPP_UC ? "CARDBUS_VPP_UC" : (command &
1309 CARDBUS_VPPMASK) ==
1310 CARDBUS_VPP_12V ? "CARDBUS_VPP_12V" : (command &
1311 CARDBUS_VPPMASK) ==
1312 CARDBUS_VPP_VCC ? "CARDBUS_VPP_VCC" : (command &
1313 CARDBUS_VPPMASK) ==
1314 CARDBUS_VPP_0V ? "CARDBUS_VPP_0V" : "UNKNOWN", command));
1315 #if 0
1316 if (command == (CARDBUS_VCC_0V | CARDBUS_VPP_0V)) {
1317 u_int32_t force =
1318 bus_space_read_4(memt, memh, CB_SOCKET_FORCE);
1319 /* Reset Bad Vcc request */
1320 force &= ~CB_SOCKET_FORCE_BADVCC;
1321 bus_space_write_4(memt, memh, CB_SOCKET_FORCE, force);
1322 printf("new status 0x%x\n", bus_space_read_4(memt, memh,
1323 CB_SOCKET_STAT));
1324 return 1;
1325 }
1326 #endif
1327 return 0;
1328 }
1329
1330 /*
1331 * XXX delay 300 ms: though the standard defines that the Vcc set-up
1332 * time is 20 ms, some PC-Card bridge requires longer duration.
1333 */
1334 delay(300 * 1000);
1335
1336 return 1; /* power changed correctly */
1337 }
1338
1339 #if defined CB_PCMCIA_POLL
1340 struct cb_poll_str {
1341 void *arg;
1342 int (*func)(void *);
1343 int level;
1344 pccard_chipset_tag_t ct;
1345 int count;
1346 };
1347
1348 static struct cb_poll_str cb_poll[10];
1349 static int cb_poll_n = 0;
1350 static struct timeout cb_poll_timeout;
1351
1352 void cb_pcmcia_poll(void *arg);
1353
1354 void
cb_pcmcia_poll(arg)1355 cb_pcmcia_poll(arg)
1356 void *arg;
1357 {
1358 struct cb_poll_str *poll = arg;
1359 struct cbb_pcmcia_softc *psc = (void *)poll->ct->v;
1360 struct pccbb_softc *sc = psc->cpc_parent;
1361 int s;
1362 u_int32_t spsr; /* socket present-state reg */
1363
1364 timeout_set(&cb_poll_timeout, cb_pcmcia_poll, arg);
1365 timeout_add(&cb_poll_timeout, hz / 10);
1366 switch (poll->level) {
1367 case IPL_NET:
1368 s = splnet();
1369 break;
1370 case IPL_BIO:
1371 s = splbio();
1372 break;
1373 case IPL_TTY: /* fallthrough */
1374 default:
1375 s = spltty();
1376 break;
1377 }
1378
1379 spsr =
1380 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
1381 CB_SOCKET_STAT);
1382
1383 #if defined CB_PCMCIA_POLL_ONLY && defined LEVEL2
1384 if (!(spsr & 0x40)) { /* CINT low */
1385 #else
1386 if (1) {
1387 #endif
1388 if ((*poll->func) (poll->arg) == 1) {
1389 ++poll->count;
1390 printf("intr: reported from poller, 0x%x\n", spsr);
1391 #if defined LEVEL2
1392 } else {
1393 printf("intr: miss! 0x%x\n", spsr);
1394 #endif
1395 }
1396 }
1397 splx(s);
1398 }
1399 #endif /* defined CB_PCMCIA_POLL */
1400
1401 /*
1402 * int pccbb_detect_card(struct pccbb_softc *sc)
1403 * return value: 0 if no card exists.
1404 * 1 if 16-bit card exists.
1405 * 2 if cardbus card exists.
1406 */
1407 int
pccbb_detect_card(sc)1408 pccbb_detect_card(sc)
1409 struct pccbb_softc *sc;
1410 {
1411 bus_space_handle_t base_memh = sc->sc_base_memh;
1412 bus_space_tag_t base_memt = sc->sc_base_memt;
1413 u_int32_t sockstat =
1414 bus_space_read_4(base_memt, base_memh, CB_SOCKET_STAT);
1415 int retval = 0;
1416
1417 /*
1418 * The SCM Microsystems TI1225-based PCI-CardBus dock card that
1419 * ships with some Lucent WaveLAN cards has only one physical slot
1420 * but OpenBSD probes two. The phantom card in the second slot can
1421 * be ignored by punting on unsupported voltages.
1422 */
1423 if (sockstat & CB_SOCKET_STAT_XVCARD)
1424 return 0;
1425
1426 /* CD1 and CD2 asserted */
1427 if (0x00 == (sockstat & CB_SOCKET_STAT_CD)) {
1428 /* card must be present */
1429 if (!(CB_SOCKET_STAT_NOTCARD & sockstat)) {
1430 /* NOTACARD DEASSERTED */
1431 if (CB_SOCKET_STAT_CB & sockstat) {
1432 /* CardBus mode */
1433 retval = 2;
1434 } else if (CB_SOCKET_STAT_16BIT & sockstat) {
1435 /* 16-bit mode */
1436 retval = 1;
1437 }
1438 }
1439 }
1440 return retval;
1441 }
1442
1443 /*
1444 * int cb_reset(struct pccbb_softc *sc)
1445 * This function resets CardBus card.
1446 */
1447 int
cb_reset(sc)1448 cb_reset(sc)
1449 struct pccbb_softc *sc;
1450 {
1451 /*
1452 * Reset Assert at least 20 ms
1453 * Some machines request longer duration.
1454 */
1455 int reset_duration =
1456 (sc->sc_chipset == CB_RX5C47X ? 400 * 1000 : 40 * 1000);
1457 u_int32_t bcr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
1458
1459 /* Reset bit Assert (bit 6 at 0x3E) */
1460 bcr |= CB_BCR_RESET_ENABLE;
1461 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
1462 delay(reset_duration);
1463
1464 if (CBB_CARDEXIST & sc->sc_flags) { /* A card exists. Reset it! */
1465 /* Reset bit Deassert (bit 6 at 0x3E) */
1466 bcr &= ~CB_BCR_RESET_ENABLE;
1467 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, bcr);
1468 delay(reset_duration);
1469 }
1470 /* No card found on the slot. Keep Reset. */
1471 return 1;
1472 }
1473
1474 /*
1475 * int cb_detect_voltage(struct pccbb_softc *sc)
1476 * This function detect card Voltage.
1477 */
1478 int
cb_detect_voltage(sc)1479 cb_detect_voltage(sc)
1480 struct pccbb_softc *sc;
1481 {
1482 u_int32_t psr; /* socket present-state reg */
1483 bus_space_tag_t iot = sc->sc_base_memt;
1484 bus_space_handle_t ioh = sc->sc_base_memh;
1485 int vol = PCCARD_VCC_UKN; /* set 0 */
1486
1487 psr = bus_space_read_4(iot, ioh, CB_SOCKET_STAT);
1488
1489 if (0x400u & psr) {
1490 vol |= PCCARD_VCC_5V;
1491 }
1492 if (0x800u & psr) {
1493 vol |= PCCARD_VCC_3V;
1494 }
1495
1496 return vol;
1497 }
1498
1499 int
cbbprint(aux,pcic)1500 cbbprint(aux, pcic)
1501 void *aux;
1502 const char *pcic;
1503 {
1504 /*
1505 struct cbslot_attach_args *cba = aux;
1506
1507 if (cba->cba_slot >= 0) {
1508 printf(" slot %d", cba->cba_slot);
1509 }
1510 */
1511 return UNCONF;
1512 }
1513
1514 /*
1515 * int pccbb_cardenable(struct pccbb_softc *sc, int function)
1516 * This function enables and disables the card
1517 */
1518 int
pccbb_cardenable(sc,function)1519 pccbb_cardenable(sc, function)
1520 struct pccbb_softc *sc;
1521 int function;
1522 {
1523 u_int32_t command =
1524 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
1525
1526 DPRINTF(("pccbb_cardenable:"));
1527 switch (function) {
1528 case CARDBUS_IO_ENABLE:
1529 command |= PCI_COMMAND_IO_ENABLE;
1530 break;
1531 case CARDBUS_IO_DISABLE:
1532 command &= ~PCI_COMMAND_IO_ENABLE;
1533 break;
1534 case CARDBUS_MEM_ENABLE:
1535 command |= PCI_COMMAND_MEM_ENABLE;
1536 break;
1537 case CARDBUS_MEM_DISABLE:
1538 command &= ~PCI_COMMAND_MEM_ENABLE;
1539 break;
1540 case CARDBUS_BM_ENABLE:
1541 command |= PCI_COMMAND_MASTER_ENABLE;
1542 break;
1543 case CARDBUS_BM_DISABLE:
1544 command &= ~PCI_COMMAND_MASTER_ENABLE;
1545 break;
1546 default:
1547 return 0;
1548 }
1549
1550 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, command);
1551 DPRINTF((" command reg 0x%x\n", command));
1552 return 1;
1553 }
1554
1555 #if !rbus
1556 /*
1557 * int pccbb_io_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)
1558 */
1559 int
pccbb_io_open(ct,win,start,end)1560 pccbb_io_open(ct, win, start, end)
1561 cardbus_chipset_tag_t ct;
1562 int win;
1563 u_int32_t start, end;
1564 {
1565 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1566 int basereg;
1567 int limitreg;
1568
1569 if ((win < 0) || (win > 2)) {
1570 #if defined DIAGNOSTIC
1571 printf("cardbus_io_open: window out of range %d\n", win);
1572 #endif
1573 return 0;
1574 }
1575
1576 basereg = win * 8 + 0x2c;
1577 limitreg = win * 8 + 0x30;
1578
1579 DPRINTF(("pccbb_io_open: 0x%x[0x%x] - 0x%x[0x%x]\n",
1580 start, basereg, end, limitreg));
1581
1582 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);
1583 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);
1584 return 1;
1585 }
1586
1587 /*
1588 * int pccbb_io_close(cardbus_chipset_tag_t, int)
1589 */
1590 int
pccbb_io_close(ct,win)1591 pccbb_io_close(ct, win)
1592 cardbus_chipset_tag_t ct;
1593 int win;
1594 {
1595 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1596 int basereg;
1597 int limitreg;
1598
1599 if ((win < 0) || (win > 2)) {
1600 #if defined DIAGNOSTIC
1601 printf("cardbus_io_close: window out of range %d\n", win);
1602 #endif
1603 return 0;
1604 }
1605
1606 basereg = win * 8 + 0x2c;
1607 limitreg = win * 8 + 0x30;
1608
1609 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);
1610 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);
1611 return 1;
1612 }
1613
1614 /*
1615 * int pccbb_mem_open(cardbus_chipset_tag_t, int, u_int32_t, u_int32_t)
1616 */
1617 int
pccbb_mem_open(ct,win,start,end)1618 pccbb_mem_open(ct, win, start, end)
1619 cardbus_chipset_tag_t ct;
1620 int win;
1621 u_int32_t start, end;
1622 {
1623 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1624 int basereg;
1625 int limitreg;
1626
1627 if ((win < 0) || (win > 2)) {
1628 #if defined DIAGNOSTIC
1629 printf("cardbus_mem_open: window out of range %d\n", win);
1630 #endif
1631 return 0;
1632 }
1633
1634 basereg = win * 8 + 0x1c;
1635 limitreg = win * 8 + 0x20;
1636
1637 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, start);
1638 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, end);
1639 return 1;
1640 }
1641
1642 /*
1643 * int pccbb_mem_close(cardbus_chipset_tag_t, int)
1644 */
1645 int
pccbb_mem_close(ct,win)1646 pccbb_mem_close(ct, win)
1647 cardbus_chipset_tag_t ct;
1648 int win;
1649 {
1650 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1651 int basereg;
1652 int limitreg;
1653
1654 if ((win < 0) || (win > 2)) {
1655 #if defined DIAGNOSTIC
1656 printf("cardbus_mem_close: window out of range %d\n", win);
1657 #endif
1658 return 0;
1659 }
1660
1661 basereg = win * 8 + 0x1c;
1662 limitreg = win * 8 + 0x20;
1663
1664 pci_conf_write(sc->sc_pc, sc->sc_tag, basereg, 0);
1665 pci_conf_write(sc->sc_pc, sc->sc_tag, limitreg, 0);
1666 return 1;
1667 }
1668 #endif
1669
1670 /*
1671 * void *pccbb_cb_intr_establish(cardbus_chipset_tag_t ct,
1672 * int irq,
1673 * int level,
1674 * int (* func)(void *),
1675 * void *arg)
1676 *
1677 * This function registers an interrupt handler at the bridge, in
1678 * order not to call the interrupt handlers of child devices when
1679 * a card-deletion interrupt occurs.
1680 *
1681 * The arguments irq is not used because pccbb selects intr vector.
1682 */
1683 void *
pccbb_cb_intr_establish(ct,irq,level,func,arg)1684 pccbb_cb_intr_establish(ct, irq, level, func, arg)
1685 cardbus_chipset_tag_t ct;
1686 int irq, level;
1687 int (*func)(void *);
1688 void *arg;
1689 {
1690 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1691
1692 return pccbb_intr_establish(sc, irq, level, func, arg);
1693 }
1694
1695
1696 /*
1697 * void *pccbb_cb_intr_disestablish(cardbus_chipset_tag_t ct,
1698 * void *ih)
1699 *
1700 * This function removes an interrupt handler pointed by ih.
1701 */
1702 void
pccbb_cb_intr_disestablish(ct,ih)1703 pccbb_cb_intr_disestablish(ct, ih)
1704 cardbus_chipset_tag_t ct;
1705 void *ih;
1706 {
1707 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
1708
1709 pccbb_intr_disestablish(sc, ih);
1710 }
1711
1712
1713 /*
1714 * void *pccbb_intr_establish(struct pccbb_softc *sc,
1715 * int irq,
1716 * int level,
1717 * int (* func)(void *),
1718 * void *arg)
1719 *
1720 * This function registers an interrupt handler at the bridge, in
1721 * order not to call the interrupt handlers of child devices when
1722 * a card-deletion interrupt occurs.
1723 *
1724 * The arguments irq and level are not used.
1725 */
1726 void *
pccbb_intr_establish(sc,irq,level,func,arg)1727 pccbb_intr_establish(sc, irq, level, func, arg)
1728 struct pccbb_softc *sc;
1729 int irq, level;
1730 int (*func)(void *);
1731 void *arg;
1732 {
1733 struct pccbb_intrhand_list *pil, *newpil;
1734 pcireg_t reg;
1735
1736 DPRINTF(("pccbb_intr_establish start. %p\n", sc->sc_pil));
1737
1738 if (sc->sc_pil == NULL) {
1739 /* initialize bridge intr routing */
1740 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
1741 reg &= ~CB_BCR_INTR_IREQ_ENABLE;
1742 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
1743
1744 switch (sc->sc_chipset) {
1745 case CB_TI113X:
1746 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
1747 /* functional intr enabled */
1748 reg |= PCI113X_CBCTRL_PCI_INTR;
1749 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
1750 break;
1751 default:
1752 break;
1753 }
1754 }
1755
1756 /*
1757 * Allocate a room for interrupt handler structure.
1758 */
1759 newpil = (struct pccbb_intrhand_list *)
1760 malloc(sizeof(struct pccbb_intrhand_list), M_DEVBUF, M_WAITOK);
1761
1762 newpil->pil_func = func;
1763 newpil->pil_arg = arg;
1764 newpil->pil_level = level;
1765 newpil->pil_next = NULL;
1766
1767 if (sc->sc_pil == NULL) {
1768 sc->sc_pil = newpil;
1769 } else {
1770 for (pil = sc->sc_pil; pil->pil_next != NULL;
1771 pil = pil->pil_next);
1772 pil->pil_next = newpil;
1773 }
1774
1775 DPRINTF(("pccbb_intr_establish add pil. %p\n", sc->sc_pil));
1776
1777 return newpil;
1778 }
1779
1780 /*
1781 * void *pccbb_intr_disestablish(struct pccbb_softc *sc,
1782 * void *ih)
1783 *
1784 * This function removes an interrupt handler pointed by ih.
1785 */
1786 void
pccbb_intr_disestablish(sc,ih)1787 pccbb_intr_disestablish(sc, ih)
1788 struct pccbb_softc *sc;
1789 void *ih;
1790 {
1791 struct pccbb_intrhand_list *pil, **pil_prev;
1792 pcireg_t reg;
1793
1794 DPRINTF(("pccbb_intr_disestablish start. %p\n", sc->sc_pil));
1795
1796 pil_prev = &sc->sc_pil;
1797
1798 for (pil = sc->sc_pil; pil != NULL; pil = pil->pil_next) {
1799 if (pil == ih) {
1800 *pil_prev = pil->pil_next;
1801 free(pil, M_DEVBUF);
1802 DPRINTF(("pccbb_intr_disestablish frees one pil\n"));
1803 break;
1804 }
1805 pil_prev = &pil->pil_next;
1806 }
1807
1808 if (sc->sc_pil == NULL) {
1809 /* No interrupt handlers */
1810
1811 DPRINTF(("pccbb_intr_disestablish: no interrupt handler\n"));
1812
1813 /* stop routing PCI intr */
1814 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR);
1815 reg |= CB_BCR_INTR_IREQ_ENABLE;
1816 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_BCR_INTR, reg);
1817
1818 switch (sc->sc_chipset) {
1819 case CB_TI113X:
1820 reg = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_CBCTRL);
1821 /* functional intr disabled */
1822 reg &= ~PCI113X_CBCTRL_PCI_INTR;
1823 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_CBCTRL, reg);
1824 break;
1825 default:
1826 break;
1827 }
1828 }
1829 }
1830
1831 #if defined SHOW_REGS
1832 void
cb_show_regs(pc,tag,memt,memh)1833 cb_show_regs(pc, tag, memt, memh)
1834 pci_chipset_tag_t pc;
1835 pcitag_t tag;
1836 bus_space_tag_t memt;
1837 bus_space_handle_t memh;
1838 {
1839 int i;
1840 printf("PCI config regs:");
1841 for (i = 0; i < 0x50; i += 4) {
1842 if (i % 16 == 0) {
1843 printf("\n 0x%02x:", i);
1844 }
1845 printf(" %08x", pci_conf_read(pc, tag, i));
1846 }
1847 for (i = 0x80; i < 0xb0; i += 4) {
1848 if (i % 16 == 0) {
1849 printf("\n 0x%02x:", i);
1850 }
1851 printf(" %08x", pci_conf_read(pc, tag, i));
1852 }
1853
1854 if (memh == 0) {
1855 printf("\n");
1856 return;
1857 }
1858
1859 printf("\nsocket regs:");
1860 for (i = 0; i <= 0x10; i += 0x04) {
1861 printf(" %08x", bus_space_read_4(memt, memh, i));
1862 }
1863 printf("\nExCA regs:");
1864 for (i = 0; i < 0x08; ++i) {
1865 printf(" %02x", bus_space_read_1(memt, memh, 0x800 + i));
1866 }
1867 printf("\n");
1868 return;
1869 }
1870 #endif
1871
1872 /*
1873 * cardbustag_t pccbb_make_tag(cardbus_chipset_tag_t cc,
1874 * int busno, int devno, int function)
1875 * This is the function to make a tag to access config space of
1876 * a CardBus Card. It works same as pci_conf_read.
1877 */
1878 cardbustag_t
pccbb_make_tag(cc,busno,devno,function)1879 pccbb_make_tag(cc, busno, devno, function)
1880 cardbus_chipset_tag_t cc;
1881 int busno, devno, function;
1882 {
1883 struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1884
1885 return pci_make_tag(sc->sc_pc, busno, devno, function);
1886 }
1887
1888 void
pccbb_free_tag(cc,tag)1889 pccbb_free_tag(cc, tag)
1890 cardbus_chipset_tag_t cc;
1891 cardbustag_t tag;
1892 {
1893 }
1894
1895 /*
1896 * cardbusreg_t pccbb_conf_read(cardbus_chipset_tag_t cc,
1897 * cardbustag_t tag, int offset)
1898 * This is the function to read the config space of a CardBus Card.
1899 * It works same as pci_conf_read.
1900 */
1901 cardbusreg_t
pccbb_conf_read(cc,tag,offset)1902 pccbb_conf_read(cc, tag, offset)
1903 cardbus_chipset_tag_t cc;
1904 cardbustag_t tag;
1905 int offset; /* register offset */
1906 {
1907 struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1908
1909 return pci_conf_read(sc->sc_pc, tag, offset);
1910 }
1911
1912 /*
1913 * void pccbb_conf_write(cardbus_chipset_tag_t cc, cardbustag_t tag,
1914 * int offs, cardbusreg_t val)
1915 * This is the function to write the config space of a CardBus Card.
1916 * It works same as pci_conf_write.
1917 */
1918 void
pccbb_conf_write(cc,tag,reg,val)1919 pccbb_conf_write(cc, tag, reg, val)
1920 cardbus_chipset_tag_t cc;
1921 cardbustag_t tag;
1922 int reg; /* register offset */
1923 cardbusreg_t val;
1924 {
1925 struct pccbb_softc *sc = (struct pccbb_softc *)cc;
1926
1927 pci_conf_write(sc->sc_pc, tag, reg, val);
1928 }
1929
1930 #if 0
1931 int
1932 pccbb_new_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
1933 bus_addr_t start, bus_size_t size, bus_size_t align, bus_addr_t mask,
1934 int speed, int flags,
1935 bus_space_handle_t * iohp)
1936 #endif
1937 /*
1938 * int pccbb_pcmcia_io_alloc(pcmcia_chipset_handle_t pch,
1939 * bus_addr_t start, bus_size_t size,
1940 * bus_size_t align,
1941 * struct pcmcia_io_handle *pcihp
1942 *
1943 * This function only allocates I/O region for pccard. This function
1944 * never maps the allocated region to pccard I/O area.
1945 *
1946 * XXX: The interface of this function is not very good, I believe.
1947 */
1948 int
pccbb_pcmcia_io_alloc(pch,start,size,align,pcihp)1949 pccbb_pcmcia_io_alloc(pch, start, size, align, pcihp)
1950 pcmcia_chipset_handle_t pch;
1951 bus_addr_t start; /* start address */
1952 bus_size_t size;
1953 bus_size_t align;
1954 struct pcmcia_io_handle *pcihp;
1955 {
1956 struct pcic_handle *ph = (struct pcic_handle *)pch;
1957 bus_addr_t ioaddr;
1958 int flags = 0;
1959 bus_space_tag_t iot;
1960 bus_space_handle_t ioh;
1961 #if rbus
1962 rbus_tag_t rb;
1963 #endif
1964 if (align == 0) {
1965 align = size; /* XXX: funny??? */
1966 }
1967
1968 /*
1969 * Allocate some arbitrary I/O space.
1970 */
1971
1972 iot = ((struct pccbb_softc *)(ph->ph_parent))->sc_iot;
1973
1974 #if rbus
1975 rb = ((struct pccbb_softc *)(ph->ph_parent))->sc_rbus_iot;
1976 /* XXX: I assume all card decode lower 10 bits by its hardware */
1977 if (rbus_space_alloc(rb, start, size, 0x3ff, align, 0, &ioaddr, &ioh)) {
1978 return 1;
1979 }
1980 #else
1981 if (start) {
1982 ioaddr = start;
1983 if (bus_space_map(iot, start, size, 0, &ioh)) {
1984 return 1;
1985 }
1986 DPRINTF(("pccbb_pcmcia_io_alloc map port %lx+%lx\n",
1987 (u_long) ioaddr, (u_long) size));
1988 } else {
1989 flags |= PCMCIA_IO_ALLOCATED;
1990 if (bus_space_alloc(iot, 0x700 /* ph->sc->sc_iobase */ ,
1991 0x800, /* ph->sc->sc_iobase + ph->sc->sc_iosize */
1992 size, align, 0, 0, &ioaddr, &ioh)) {
1993 /* No room be able to be get. */
1994 return 1;
1995 }
1996 DPRINTF(("pccbb_pcmmcia_io_alloc alloc port 0x%lx+0x%lx\n",
1997 (u_long) ioaddr, (u_long) size));
1998 }
1999 #endif
2000
2001 pcihp->iot = iot;
2002 pcihp->ioh = ioh;
2003 pcihp->addr = ioaddr;
2004 pcihp->size = size;
2005 pcihp->flags = flags;
2006
2007 return 0;
2008 }
2009
2010 /*
2011 * int pccbb_pcmcia_io_free(pcmcia_chipset_handle_t pch,
2012 * struct pcmcia_io_handle *pcihp)
2013 *
2014 * This function only frees I/O region for pccard.
2015 *
2016 * XXX: The interface of this function is not very good, I believe.
2017 */
2018 void
pccbb_pcmcia_io_free(pch,pcihp)2019 pccbb_pcmcia_io_free(pch, pcihp)
2020 pcmcia_chipset_handle_t pch;
2021 struct pcmcia_io_handle *pcihp;
2022 {
2023 #if !rbus
2024 bus_space_tag_t iot = pcihp->iot;
2025 #endif
2026 bus_space_handle_t ioh = pcihp->ioh;
2027 bus_size_t size = pcihp->size;
2028
2029 #if rbus
2030 struct pccbb_softc *sc =
2031 (struct pccbb_softc *)((struct pcic_handle *)pch)->ph_parent;
2032 rbus_tag_t rb = sc->sc_rbus_iot;
2033
2034 rbus_space_free(rb, ioh, size, NULL);
2035 #else
2036 if (pcihp->flags & PCMCIA_IO_ALLOCATED)
2037 bus_space_free(iot, ioh, size);
2038 else
2039 bus_space_unmap(iot, ioh, size);
2040 #endif
2041 }
2042
2043 /*
2044 * int pccbb_pcmcia_io_map(pcmcia_chipset_handle_t pch, int width,
2045 * bus_addr_t offset, bus_size_t size,
2046 * struct pcmcia_io_handle *pcihp,
2047 * int *windowp)
2048 *
2049 * This function maps the allocated I/O region to pccard. This function
2050 * never allocates any I/O region for pccard I/O area. I don't
2051 * understand why the original authors of pcmciabus separated alloc and
2052 * map. I believe the two must be unite.
2053 *
2054 * XXX: no wait timing control?
2055 */
2056 int
pccbb_pcmcia_io_map(pch,width,offset,size,pcihp,windowp)2057 pccbb_pcmcia_io_map(pch, width, offset, size, pcihp, windowp)
2058 pcmcia_chipset_handle_t pch;
2059 int width;
2060 bus_addr_t offset;
2061 bus_size_t size;
2062 struct pcmcia_io_handle *pcihp;
2063 int *windowp;
2064 {
2065 struct pcic_handle *ph = (struct pcic_handle *)pch;
2066 bus_addr_t ioaddr = pcihp->addr + offset;
2067 int i, win;
2068 #if defined CBB_DEBUG
2069 static char *width_names[] = { "dynamic", "io8", "io16" };
2070 #endif
2071
2072 /* Sanity check I/O handle. */
2073
2074 if (((struct pccbb_softc *)ph->ph_parent)->sc_iot != pcihp->iot) {
2075 panic("pccbb_pcmcia_io_map iot is bogus");
2076 }
2077
2078 /* XXX Sanity check offset/size. */
2079
2080 win = -1;
2081 for (i = 0; i < PCIC_IO_WINS; i++) {
2082 if ((ph->ioalloc & (1 << i)) == 0) {
2083 win = i;
2084 ph->ioalloc |= (1 << i);
2085 break;
2086 }
2087 }
2088
2089 if (win == -1) {
2090 return 1;
2091 }
2092
2093 *windowp = win;
2094
2095 /* XXX this is pretty gross */
2096
2097 DPRINTF(("pccbb_pcmcia_io_map window %d %s port %lx+%lx\n",
2098 win, width_names[width], (u_long) ioaddr, (u_long) size));
2099
2100 /* XXX wtf is this doing here? */
2101
2102 #if 0
2103 printf(" port 0x%lx", (u_long) ioaddr);
2104 if (size > 1) {
2105 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1);
2106 }
2107 #endif
2108
2109 ph->io[win].addr = ioaddr;
2110 ph->io[win].size = size;
2111 ph->io[win].width = width;
2112
2113 /* actual dirty register-value changing in the function below. */
2114 pccbb_pcmcia_do_io_map(ph, win);
2115
2116 return 0;
2117 }
2118
2119 /*
2120 * void pccbb_pcmcia_do_io_map(struct pcic_handle *h, int win)
2121 *
2122 * This function changes register-value to map I/O region for pccard.
2123 */
2124 void
pccbb_pcmcia_do_io_map(ph,win)2125 pccbb_pcmcia_do_io_map(ph, win)
2126 struct pcic_handle *ph;
2127 int win;
2128 {
2129 static u_int8_t pcic_iowidth[3] = {
2130 PCIC_IOCTL_IO0_IOCS16SRC_CARD,
2131 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
2132 PCIC_IOCTL_IO0_DATASIZE_8BIT,
2133 PCIC_IOCTL_IO0_IOCS16SRC_DATASIZE |
2134 PCIC_IOCTL_IO0_DATASIZE_16BIT,
2135 };
2136
2137 #define PCIC_SIA_START_LOW 0
2138 #define PCIC_SIA_START_HIGH 1
2139 #define PCIC_SIA_STOP_LOW 2
2140 #define PCIC_SIA_STOP_HIGH 3
2141
2142 int regbase_win = 0x8 + win * 0x04;
2143 u_int8_t ioctl, enable;
2144
2145 DPRINTF(
2146 ("pccbb_pcmcia_do_io_map win %d addr 0x%lx size 0x%lx width %d\n",
2147 win, (long)ph->io[win].addr, (long)ph->io[win].size,
2148 ph->io[win].width * 8));
2149
2150 Pcic_write(ph, regbase_win + PCIC_SIA_START_LOW,
2151 ph->io[win].addr & 0xff);
2152 Pcic_write(ph, regbase_win + PCIC_SIA_START_HIGH,
2153 (ph->io[win].addr >> 8) & 0xff);
2154
2155 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_LOW,
2156 (ph->io[win].addr + ph->io[win].size - 1) & 0xff);
2157 Pcic_write(ph, regbase_win + PCIC_SIA_STOP_HIGH,
2158 ((ph->io[win].addr + ph->io[win].size - 1) >> 8) & 0xff);
2159
2160 ioctl = Pcic_read(ph, PCIC_IOCTL);
2161 enable = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2162 switch (win) {
2163 case 0:
2164 ioctl &= ~(PCIC_IOCTL_IO0_WAITSTATE | PCIC_IOCTL_IO0_ZEROWAIT |
2165 PCIC_IOCTL_IO0_IOCS16SRC_MASK |
2166 PCIC_IOCTL_IO0_DATASIZE_MASK);
2167 ioctl |= pcic_iowidth[ph->io[win].width];
2168 enable |= PCIC_ADDRWIN_ENABLE_IO0;
2169 break;
2170 case 1:
2171 ioctl &= ~(PCIC_IOCTL_IO1_WAITSTATE | PCIC_IOCTL_IO1_ZEROWAIT |
2172 PCIC_IOCTL_IO1_IOCS16SRC_MASK |
2173 PCIC_IOCTL_IO1_DATASIZE_MASK);
2174 ioctl |= (pcic_iowidth[ph->io[win].width] << 4);
2175 enable |= PCIC_ADDRWIN_ENABLE_IO1;
2176 break;
2177 }
2178 Pcic_write(ph, PCIC_IOCTL, ioctl);
2179 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, enable);
2180 #if defined CBB_DEBUG
2181 {
2182 u_int8_t start_low =
2183 Pcic_read(ph, regbase_win + PCIC_SIA_START_LOW);
2184 u_int8_t start_high =
2185 Pcic_read(ph, regbase_win + PCIC_SIA_START_HIGH);
2186 u_int8_t stop_low =
2187 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_LOW);
2188 u_int8_t stop_high =
2189 Pcic_read(ph, regbase_win + PCIC_SIA_STOP_HIGH);
2190 printf
2191 (" start %02x %02x, stop %02x %02x, ioctl %02x enable %02x\n",
2192 start_low, start_high, stop_low, stop_high, ioctl, enable);
2193 }
2194 #endif
2195 }
2196
2197 /*
2198 * void pccbb_pcmcia_io_unmap(pcmcia_chipset_handle_t *h, int win)
2199 *
2200 * This function unmaps I/O region. No return value.
2201 */
2202 void
pccbb_pcmcia_io_unmap(pch,win)2203 pccbb_pcmcia_io_unmap(pch, win)
2204 pcmcia_chipset_handle_t pch;
2205 int win;
2206 {
2207 struct pcic_handle *ph = (struct pcic_handle *)pch;
2208 int reg;
2209
2210 if (win >= PCIC_IO_WINS || win < 0) {
2211 panic("pccbb_pcmcia_io_unmap: window out of range");
2212 }
2213
2214 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2215 switch (win) {
2216 case 0:
2217 reg &= ~PCIC_ADDRWIN_ENABLE_IO0;
2218 break;
2219 case 1:
2220 reg &= ~PCIC_ADDRWIN_ENABLE_IO1;
2221 break;
2222 }
2223 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
2224
2225 ph->ioalloc &= ~(1 << win);
2226 }
2227
2228 /*
2229 * void pccbb_pcmcia_wait_ready(struct pcic_handle *ph)
2230 *
2231 * This function enables the card. All information is stored in
2232 * the first argument, pcmcia_chipset_handle_t.
2233 */
2234 void
pccbb_pcmcia_wait_ready(ph)2235 pccbb_pcmcia_wait_ready(ph)
2236 struct pcic_handle *ph;
2237 {
2238 int i;
2239
2240 DPRINTF(("pccbb_pcmcia_wait_ready: status 0x%02x\n",
2241 Pcic_read(ph, PCIC_IF_STATUS)));
2242
2243 for (i = 0; i < 10000; i++) {
2244 if (Pcic_read(ph, PCIC_IF_STATUS) & PCIC_IF_STATUS_READY) {
2245 return;
2246 }
2247 delay(500);
2248 #ifdef CBB_DEBUG
2249 if ((i > 5000) && (i % 100 == 99))
2250 printf(".");
2251 #endif
2252 }
2253
2254 #ifdef DIAGNOSTIC
2255 printf("pcic_wait_ready: ready never happened, status = %02x\n",
2256 Pcic_read(ph, PCIC_IF_STATUS));
2257 #endif
2258 }
2259
2260 /*
2261 * void pccbb_pcmcia_socket_enable(pcmcia_chipset_handle_t pch)
2262 *
2263 * This function enables the card. All information is stored in
2264 * the first argument, pcmcia_chipset_handle_t.
2265 */
2266 void
pccbb_pcmcia_socket_enable(pch)2267 pccbb_pcmcia_socket_enable(pch)
2268 pcmcia_chipset_handle_t pch;
2269 {
2270 struct pcic_handle *ph = (struct pcic_handle *)pch;
2271 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2272 int cardtype, win;
2273 u_int8_t power, intr;
2274 pcireg_t spsr;
2275 int voltage;
2276
2277 /* this bit is mostly stolen from pcic_attach_card */
2278
2279 DPRINTF(("pccbb_pcmcia_socket_enable: "));
2280
2281 /* get card Vcc info */
2282
2283 spsr =
2284 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
2285 CB_SOCKET_STAT);
2286 if (spsr & CB_SOCKET_STAT_5VCARD) {
2287 DPRINTF(("5V card\n"));
2288 voltage = CARDBUS_VCC_5V | CARDBUS_VPP_VCC;
2289 } else if (spsr & CB_SOCKET_STAT_3VCARD) {
2290 DPRINTF(("3V card\n"));
2291 voltage = CARDBUS_VCC_3V | CARDBUS_VPP_VCC;
2292 } else {
2293 printf("?V card, 0x%x\n", spsr); /* XXX */
2294 return;
2295 }
2296
2297 /* disable socket i/o: negate output enable bit */
2298
2299 power = 0;
2300 Pcic_write(ph, PCIC_PWRCTL, power);
2301
2302 /* power down the socket to reset it, clear the card reset pin */
2303
2304 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2305
2306 /*
2307 * wait 200ms until power fails (Tpf). Then, wait 100ms since
2308 * we are changing Vcc (Toff).
2309 */
2310 /* delay(300*1000); too much */
2311
2312 /* assert reset bit */
2313 intr = Pcic_read(ph, PCIC_INTR);
2314 intr &= ~(PCIC_INTR_RESET | PCIC_INTR_CARDTYPE_MASK);
2315 Pcic_write(ph, PCIC_INTR, intr);
2316
2317 /* power up the socket and output enable */
2318 power = Pcic_read(ph, PCIC_PWRCTL);
2319 power |= PCIC_PWRCTL_OE;
2320 Pcic_write(ph, PCIC_PWRCTL, power);
2321 pccbb_power(sc, voltage);
2322
2323 /*
2324 * hold RESET at least 10us.
2325 */
2326 delay(10);
2327 delay(2 * 1000); /* XXX: TI1130 requires it. */
2328 delay(20 * 1000); /* XXX: TI1130 requires it. */
2329
2330 /* clear the reset flag */
2331
2332 intr |= PCIC_INTR_RESET;
2333 Pcic_write(ph, PCIC_INTR, intr);
2334
2335 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */
2336
2337 delay(20000);
2338
2339 /* wait for the chip to finish initializing */
2340
2341 pccbb_pcmcia_wait_ready(ph);
2342
2343 /* zero out the address windows */
2344
2345 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, 0);
2346
2347 /* set the card type */
2348
2349 cardtype = pcmcia_card_gettype(ph->pcmcia);
2350
2351 intr |= ((cardtype == PCMCIA_IFTYPE_IO) ?
2352 PCIC_INTR_CARDTYPE_IO : PCIC_INTR_CARDTYPE_MEM);
2353 Pcic_write(ph, PCIC_INTR, intr);
2354
2355 DPRINTF(("%s: pccbb_pcmcia_socket_enable %02x cardtype %s %02x\n",
2356 ph->ph_parent->dv_xname, ph->sock,
2357 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), intr));
2358
2359 /* reinstall all the memory and io mappings */
2360
2361 for (win = 0; win < PCIC_MEM_WINS; ++win) {
2362 if (ph->memalloc & (1 << win)) {
2363 pccbb_pcmcia_do_mem_map(ph, win);
2364 }
2365 }
2366
2367 for (win = 0; win < PCIC_IO_WINS; ++win) {
2368 if (ph->ioalloc & (1 << win)) {
2369 pccbb_pcmcia_do_io_map(ph, win);
2370 }
2371 }
2372 }
2373
2374 /*
2375 * void pccbb_pcmcia_socket_disable(pcmcia_chipset_handle_t *ph)
2376 *
2377 * This function disables the card. All information is stored in
2378 * the first argument, pcmcia_chipset_handle_t.
2379 */
2380 void
pccbb_pcmcia_socket_disable(pch)2381 pccbb_pcmcia_socket_disable(pch)
2382 pcmcia_chipset_handle_t pch;
2383 {
2384 struct pcic_handle *ph = (struct pcic_handle *)pch;
2385 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2386 u_int8_t power, intr;
2387
2388 DPRINTF(("pccbb_pcmcia_socket_disable\n"));
2389
2390 /* reset signal asserting... */
2391
2392 intr = Pcic_read(ph, PCIC_INTR);
2393 intr &= ~(PCIC_INTR_CARDTYPE_MASK);
2394 Pcic_write(ph, PCIC_INTR, intr);
2395 delay(2 * 1000);
2396
2397 /* power down the socket */
2398 power = Pcic_read(ph, PCIC_PWRCTL);
2399 power &= ~PCIC_PWRCTL_OE;
2400 Pcic_write(ph, PCIC_PWRCTL, power);
2401 pccbb_power(sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
2402 /*
2403 * wait 300ms until power fails (Tpf).
2404 */
2405 delay(300 * 1000);
2406 }
2407
2408 /*
2409 * int pccbb_pcmcia_card_detect(pcmcia_chipset_handle_t *ph)
2410 *
2411 * This function detects whether a card is in the slot or not.
2412 * If a card is inserted, return 1. Otherwise, return 0.
2413 */
2414 int
pccbb_pcmcia_card_detect(pch)2415 pccbb_pcmcia_card_detect(pch)
2416 pcmcia_chipset_handle_t pch;
2417 {
2418 struct pcic_handle *ph = (struct pcic_handle *)pch;
2419 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2420
2421 DPRINTF(("pccbb_pcmcia_card_detect\n"));
2422 return pccbb_detect_card(sc) == 1 ? 1 : 0;
2423 }
2424
2425 #if 0
2426 int
2427 pccbb_new_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
2428 bus_addr_t start, bus_size_t size, bus_size_t align, int speed, int flags,
2429 bus_space_tag_t * memtp bus_space_handle_t * memhp)
2430 #endif
2431 /*
2432 * int pccbb_pcmcia_mem_alloc(pcmcia_chipset_handle_t pch,
2433 * bus_size_t size,
2434 * struct pcmcia_mem_handle *pcmhp)
2435 *
2436 * This function only allocates memory region for pccard. This
2437 * function never maps the allocated region to pccard memory area.
2438 *
2439 * XXX: Why the argument of start address is not in?
2440 */
2441 int
pccbb_pcmcia_mem_alloc(pch,size,pcmhp)2442 pccbb_pcmcia_mem_alloc(pch, size, pcmhp)
2443 pcmcia_chipset_handle_t pch;
2444 bus_size_t size;
2445 struct pcmcia_mem_handle *pcmhp;
2446 {
2447 struct pcic_handle *ph = (struct pcic_handle *)pch;
2448 bus_space_handle_t memh;
2449 bus_addr_t addr;
2450 bus_size_t sizepg;
2451 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2452 #if rbus
2453 rbus_tag_t rb;
2454 #endif
2455
2456 /* out of sc->memh, allocate as many pages as necessary */
2457
2458 /* convert size to PCIC pages */
2459 /*
2460 * This is not enough; when the requested region is on the page
2461 * boundaries, this may calculate wrong result.
2462 */
2463 sizepg = (size + (PCIC_MEM_PAGESIZE - 1)) / PCIC_MEM_PAGESIZE;
2464 #if 0
2465 if (sizepg > PCIC_MAX_MEM_PAGES) {
2466 return 1;
2467 }
2468 #endif
2469
2470 if (!(sc->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32)) {
2471 return 1;
2472 }
2473
2474 addr = 0; /* XXX gcc -Wuninitialized */
2475
2476 #if rbus
2477 rb = sc->sc_rbus_memt;
2478 if (rbus_space_alloc(rb, 0, sizepg * PCIC_MEM_PAGESIZE,
2479 sizepg * PCIC_MEM_PAGESIZE - 1, PCIC_MEM_PAGESIZE, 0,
2480 &addr, &memh)) {
2481 return 1;
2482 }
2483 #else
2484 if (bus_space_alloc(sc->sc_memt, sc->sc_mem_start, sc->sc_mem_end,
2485 sizepg * PCIC_MEM_PAGESIZE, PCIC_MEM_PAGESIZE,
2486 0, /* boundary */
2487 0, /* flags */
2488 &addr, &memh)) {
2489 return 1;
2490 }
2491 #endif
2492
2493 DPRINTF(
2494 ("pccbb_pcmcia_alloc_mem: addr 0x%lx size 0x%lx, realsize 0x%lx\n",
2495 addr, size, sizepg * PCIC_MEM_PAGESIZE));
2496
2497 pcmhp->memt = sc->sc_memt;
2498 pcmhp->memh = memh;
2499 pcmhp->addr = addr;
2500 pcmhp->size = size;
2501 pcmhp->realsize = sizepg * PCIC_MEM_PAGESIZE;
2502 /* What is mhandle? I feel it is very dirty and it must go trush. */
2503 pcmhp->mhandle = 0;
2504 /* No offset??? Funny. */
2505
2506 return 0;
2507 }
2508
2509 /*
2510 * void pccbb_pcmcia_mem_free(pcmcia_chipset_handle_t pch,
2511 * struct pcmcia_mem_handle *pcmhp)
2512 *
2513 * This function release the memory space allocated by the function
2514 * pccbb_pcmcia_mem_alloc().
2515 */
2516 void
pccbb_pcmcia_mem_free(pch,pcmhp)2517 pccbb_pcmcia_mem_free(pch, pcmhp)
2518 pcmcia_chipset_handle_t pch;
2519 struct pcmcia_mem_handle *pcmhp;
2520 {
2521 #if rbus
2522 struct pcic_handle *ph = (struct pcic_handle *)pch;
2523 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2524
2525 rbus_space_free(sc->sc_rbus_memt, pcmhp->memh, pcmhp->realsize, NULL);
2526 #else
2527 bus_space_free(pcmhp->memt, pcmhp->memh, pcmhp->realsize);
2528 #endif
2529 }
2530
2531 /*
2532 * void pccbb_pcmcia_do_mem_map(struct pcic_handle *ph, int win)
2533 *
2534 * This function release the memory space allocated by the function
2535 * pccbb_pcmcia_mem_alloc().
2536 */
2537 void
pccbb_pcmcia_do_mem_map(ph,win)2538 pccbb_pcmcia_do_mem_map(ph, win)
2539 struct pcic_handle *ph;
2540 int win;
2541 {
2542 int regbase_win;
2543 bus_addr_t phys_addr;
2544 bus_addr_t phys_end;
2545
2546 #define PCIC_SMM_START_LOW 0
2547 #define PCIC_SMM_START_HIGH 1
2548 #define PCIC_SMM_STOP_LOW 2
2549 #define PCIC_SMM_STOP_HIGH 3
2550 #define PCIC_CMA_LOW 4
2551 #define PCIC_CMA_HIGH 5
2552
2553 u_int8_t start_low, start_high = 0;
2554 u_int8_t stop_low, stop_high;
2555 u_int8_t off_low, off_high;
2556 u_int8_t mem_window;
2557 int reg;
2558
2559 regbase_win = 0x10 + win * 0x08;
2560
2561 phys_addr = ph->mem[win].addr;
2562 phys_end = phys_addr + ph->mem[win].size;
2563
2564 DPRINTF(("pccbb_pcmcia_do_mem_map: start 0x%lx end 0x%lx off 0x%lx\n",
2565 phys_addr, phys_end, ph->mem[win].offset));
2566
2567 #define PCIC_MEMREG_LSB_SHIFT PCIC_SYSMEM_ADDRX_SHIFT
2568 #define PCIC_MEMREG_MSB_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 8)
2569 #define PCIC_MEMREG_WIN_SHIFT (PCIC_SYSMEM_ADDRX_SHIFT + 12)
2570
2571 /* bit 19:12 */
2572 start_low = (phys_addr >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
2573 /* bit 23:20 and bit 7 on */
2574 start_high = ((phys_addr >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
2575 | PCIC_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT; /* bit 7 on */
2576 /* bit 31:24, for 32-bit address */
2577 mem_window = (phys_addr >> PCIC_MEMREG_WIN_SHIFT) & 0xff;
2578
2579 Pcic_write(ph, regbase_win + PCIC_SMM_START_LOW, start_low);
2580 Pcic_write(ph, regbase_win + PCIC_SMM_START_HIGH, start_high);
2581
2582 if (((struct pccbb_softc *)ph->
2583 ph_parent)->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2584 Pcic_write(ph, 0x40 + win, mem_window);
2585 }
2586
2587 stop_low = (phys_end >> PCIC_MEMREG_LSB_SHIFT) & 0xff;
2588 stop_high = ((phys_end >> PCIC_MEMREG_MSB_SHIFT) & 0x0f)
2589 | PCIC_SYSMEM_ADDRX_STOP_MSB_WAIT2; /* wait 2 cycles */
2590 /* XXX Geee, WAIT2!! Crazy!! I must rewrite this routine. */
2591
2592 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_LOW, stop_low);
2593 Pcic_write(ph, regbase_win + PCIC_SMM_STOP_HIGH, stop_high);
2594
2595 off_low = (ph->mem[win].offset >> PCIC_CARDMEM_ADDRX_SHIFT) & 0xff;
2596 off_high = ((ph->mem[win].offset >> (PCIC_CARDMEM_ADDRX_SHIFT + 8))
2597 & PCIC_CARDMEM_ADDRX_MSB_ADDR_MASK)
2598 | ((ph->mem[win].kind == PCMCIA_MEM_ATTR) ?
2599 PCIC_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0);
2600
2601 Pcic_write(ph, regbase_win + PCIC_CMA_LOW, off_low);
2602 Pcic_write(ph, regbase_win + PCIC_CMA_HIGH, off_high);
2603
2604 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2605 reg |= ((1 << win) | PCIC_ADDRWIN_ENABLE_MEMCS16);
2606 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
2607
2608 #if defined CBB_DEBUG
2609 {
2610 int r1, r2, r3, r4, r5, r6, r7 = 0;
2611
2612 r1 = Pcic_read(ph, regbase_win + PCIC_SMM_START_LOW);
2613 r2 = Pcic_read(ph, regbase_win + PCIC_SMM_START_HIGH);
2614 r3 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_LOW);
2615 r4 = Pcic_read(ph, regbase_win + PCIC_SMM_STOP_HIGH);
2616 r5 = Pcic_read(ph, regbase_win + PCIC_CMA_LOW);
2617 r6 = Pcic_read(ph, regbase_win + PCIC_CMA_HIGH);
2618 if (((struct pccbb_softc *)(ph->
2619 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2620 r7 = Pcic_read(ph, 0x40 + win);
2621 }
2622
2623 DPRINTF(("pccbb_pcmcia_do_mem_map window %d: %02x%02x %02x%02x "
2624 "%02x%02x", win, r1, r2, r3, r4, r5, r6));
2625 if (((struct pccbb_softc *)(ph->
2626 ph_parent))->sc_pcmcia_flags & PCCBB_PCMCIA_MEM_32) {
2627 DPRINTF((" %02x", r7));
2628 }
2629 DPRINTF(("\n"));
2630 }
2631 #endif
2632 }
2633
2634 /*
2635 * int pccbb_pcmcia_mem_map(pcmcia_chipset_handle_t pch, int kind,
2636 * bus_addr_t card_addr, bus_size_t size,
2637 * struct pcmcia_mem_handle *pcmhp,
2638 * bus_addr_t *offsetp, int *windowp)
2639 *
2640 * This function maps memory space allocated by the function
2641 * pccbb_pcmcia_mem_alloc().
2642 */
2643 int
pccbb_pcmcia_mem_map(pch,kind,card_addr,size,pcmhp,offsetp,windowp)2644 pccbb_pcmcia_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp)
2645 pcmcia_chipset_handle_t pch;
2646 int kind;
2647 bus_addr_t card_addr;
2648 bus_size_t size;
2649 struct pcmcia_mem_handle *pcmhp;
2650 bus_addr_t *offsetp;
2651 int *windowp;
2652 {
2653 struct pcic_handle *ph = (struct pcic_handle *)pch;
2654 bus_addr_t busaddr;
2655 long card_offset;
2656 int win;
2657
2658 for (win = 0; win < PCIC_MEM_WINS; ++win) {
2659 if ((ph->memalloc & (1 << win)) == 0) {
2660 ph->memalloc |= (1 << win);
2661 break;
2662 }
2663 }
2664
2665 if (win == PCIC_MEM_WINS) {
2666 return 1;
2667 }
2668
2669 *windowp = win;
2670
2671 /* XXX this is pretty gross */
2672
2673 if (((struct pccbb_softc *)ph->ph_parent)->sc_memt != pcmhp->memt) {
2674 panic("pccbb_pcmcia_mem_map memt is bogus");
2675 }
2676
2677 busaddr = pcmhp->addr;
2678
2679 /*
2680 * compute the address offset to the pcmcia address space for the
2681 * pcic. this is intentionally signed. The masks and shifts below
2682 * will cause TRT to happen in the pcic registers. Deal with making
2683 * sure the address is aligned, and return the alignment offset.
2684 */
2685
2686 *offsetp = card_addr % PCIC_MEM_PAGESIZE;
2687 card_addr -= *offsetp;
2688
2689 DPRINTF(("pccbb_pcmcia_mem_map window %d bus %lx+%lx+%lx at card addr "
2690 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size,
2691 (u_long) card_addr));
2692
2693 /*
2694 * include the offset in the size, and decrement size by one, since
2695 * the hw wants start/stop
2696 */
2697 size += *offsetp - 1;
2698
2699 card_offset = (((long)card_addr) - ((long)busaddr));
2700
2701 ph->mem[win].addr = busaddr;
2702 ph->mem[win].size = size;
2703 ph->mem[win].offset = card_offset;
2704 ph->mem[win].kind = kind;
2705
2706 pccbb_pcmcia_do_mem_map(ph, win);
2707
2708 return 0;
2709 }
2710
2711 /*
2712 * int pccbb_pcmcia_mem_unmap(pcmcia_chipset_handle_t pch,
2713 * int window)
2714 *
2715 * This function unmaps memory space which mapped by the function
2716 * pccbb_pcmcia_mem_map().
2717 */
2718 void
pccbb_pcmcia_mem_unmap(pch,window)2719 pccbb_pcmcia_mem_unmap(pch, window)
2720 pcmcia_chipset_handle_t pch;
2721 int window;
2722 {
2723 struct pcic_handle *ph = (struct pcic_handle *)pch;
2724 int reg;
2725
2726 if (window >= PCIC_MEM_WINS) {
2727 panic("pccbb_pcmcia_mem_unmap: window out of range");
2728 }
2729
2730 reg = Pcic_read(ph, PCIC_ADDRWIN_ENABLE);
2731 reg &= ~(1 << window);
2732 Pcic_write(ph, PCIC_ADDRWIN_ENABLE, reg);
2733
2734 ph->memalloc &= ~(1 << window);
2735 }
2736
2737 #if defined PCCBB_PCMCIA_POLL
2738 struct pccbb_poll_str {
2739 void *arg;
2740 int (*func)(void *);
2741 int level;
2742 struct pcic_handle *ph;
2743 int count;
2744 int num;
2745 };
2746
2747 static struct pccbb_poll_str pccbb_poll[10];
2748 static int pccbb_poll_n = 0;
2749 static struct timeout pccbb_poll_timeout;
2750
2751 void pccbb_pcmcia_poll(void *arg);
2752
2753 void
pccbb_pcmcia_poll(arg)2754 pccbb_pcmcia_poll(arg)
2755 void *arg;
2756 {
2757 struct pccbb_poll_str *poll = arg;
2758 struct pcic_handle *ph = poll->ph;
2759 struct pccbb_softc *sc = ph->sc;
2760 int s;
2761 u_int32_t spsr; /* socket present-state reg */
2762
2763 timeout_set(&pccbb_poll_timeout, pccbb_pcmcia_poll, arg);
2764 timeout_add(&pccbb_poll_timeout, hz * 2);
2765 switch (poll->level) {
2766 case IPL_NET:
2767 s = splnet();
2768 break;
2769 case IPL_BIO:
2770 s = splbio();
2771 break;
2772 case IPL_TTY: /* fallthrough */
2773 default:
2774 s = spltty();
2775 break;
2776 }
2777
2778 spsr =
2779 bus_space_read_4(sc->sc_base_memt, sc->sc_base_memh,
2780 CB_SOCKET_STAT);
2781
2782 #if defined PCCBB_PCMCIA_POLL_ONLY && defined LEVEL2
2783 if (!(spsr & 0x40)) /* CINT low */
2784 #else
2785 if (1)
2786 #endif
2787 {
2788 if ((*poll->func) (poll->arg) > 0) {
2789 ++poll->count;
2790 /* printf("intr: reported from poller, 0x%x\n", spsr); */
2791 #if defined LEVEL2
2792 } else {
2793 printf("intr: miss! 0x%x\n", spsr);
2794 #endif
2795 }
2796 }
2797 splx(s);
2798 }
2799 #endif /* defined CB_PCMCIA_POLL */
2800
2801 /*
2802 * void *pccbb_pcmcia_intr_establish(pcmcia_chipset_handle_t pch,
2803 * struct pcmcia_function *pf,
2804 * int ipl,
2805 * int (*func)(void *),
2806 * void *arg);
2807 *
2808 * This function enables PC-Card interrupt. PCCBB uses PCI interrupt line.
2809 */
2810 void *
pccbb_pcmcia_intr_establish(pch,pf,ipl,func,arg,xname)2811 pccbb_pcmcia_intr_establish(pch, pf, ipl, func, arg, xname)
2812 pcmcia_chipset_handle_t pch;
2813 struct pcmcia_function *pf;
2814 int ipl;
2815 int (*func)(void *);
2816 void *arg;
2817 char *xname;
2818 {
2819 struct pcic_handle *ph = (struct pcic_handle *)pch;
2820 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2821
2822 if (!(pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) {
2823 /* what should I do? */
2824 if ((pf->cfe->flags & PCMCIA_CFE_IRQLEVEL)) {
2825 DPRINTF(
2826 ("%s does not provide edge nor pulse interrupt\n",
2827 sc->sc_dev.dv_xname));
2828 return NULL;
2829 }
2830 /*
2831 * XXX Noooooo! The interrupt flag must set properly!!
2832 * dumb pcmcia driver!!
2833 */
2834 }
2835
2836 return pccbb_intr_establish(sc, IST_LEVEL, ipl, func, arg);
2837 }
2838
2839 /*
2840 * void pccbb_pcmcia_intr_disestablish(pcmcia_chipset_handle_t pch,
2841 * void *ih)
2842 *
2843 * This function disables PC-Card interrupt.
2844 */
2845 void
pccbb_pcmcia_intr_disestablish(pch,ih)2846 pccbb_pcmcia_intr_disestablish(pch, ih)
2847 pcmcia_chipset_handle_t pch;
2848 void *ih;
2849 {
2850 struct pcic_handle *ph = (struct pcic_handle *)pch;
2851 struct pccbb_softc *sc = (struct pccbb_softc *)ph->ph_parent;
2852
2853 pccbb_intr_disestablish(sc, ih);
2854 }
2855
2856 const char *
pccbb_pcmcia_intr_string(pch,ih)2857 pccbb_pcmcia_intr_string(pch, ih)
2858 pcmcia_chipset_handle_t pch;
2859 void *ih;
2860 {
2861 if (ih == NULL)
2862 return "couldn't establish interrupt";
2863 else
2864 return ""; /* card shares interrupt of the bridge */
2865 }
2866
2867 #if rbus
2868 /*
2869 * int
2870 * pccbb_rbus_cb_space_alloc(cardbus_chipset_tag_t ct, rbus_tag_t rb,
2871 * bus_addr_t addr, bus_size_t size,
2872 * bus_addr_t mask, bus_size_t align,
2873 * int flags, bus_addr_t *addrp;
2874 * bus_space_handle_t *bshp)
2875 *
2876 * This function allocates a portion of memory or io space for
2877 * clients. This function is called from CardBus card drivers.
2878 */
2879 int
pccbb_rbus_cb_space_alloc(ct,rb,addr,size,mask,align,flags,addrp,bshp)2880 pccbb_rbus_cb_space_alloc(ct, rb, addr, size, mask, align, flags, addrp, bshp)
2881 cardbus_chipset_tag_t ct;
2882 rbus_tag_t rb;
2883 bus_addr_t addr;
2884 bus_size_t size;
2885 bus_addr_t mask;
2886 bus_size_t align;
2887 int flags;
2888 bus_addr_t *addrp;
2889 bus_space_handle_t *bshp;
2890 {
2891 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
2892
2893 DPRINTF(
2894 ("pccbb_rbus_cb_space_alloc: adr %lx, size %lx, mask %lx, align %lx\n",
2895 addr, size, mask, align));
2896
2897 if (align == 0) {
2898 align = size;
2899 }
2900
2901 if (rb->rb_bt == sc->sc_memt) {
2902 if (align < 16) {
2903 return 1;
2904 }
2905 } else if (rb->rb_bt == sc->sc_iot) {
2906 if (align < 4) {
2907 return 1;
2908 }
2909 /* XXX: hack for avoiding ISA image */
2910 if (mask < 0x0100) {
2911 mask = 0x3ff;
2912 addr = 0x300;
2913 }
2914
2915 } else {
2916 DPRINTF(
2917 ("pccbb_rbus_cb_space_alloc: Bus space tag %x is NOT used.\n",
2918 rb->rb_bt));
2919 return 1;
2920 /* XXX: panic here? */
2921 }
2922
2923 if (rbus_space_alloc(rb, addr, size, mask, align, flags, addrp, bshp)) {
2924 printf("%s: <rbus> no bus space\n", sc->sc_dev.dv_xname);
2925 return 1;
2926 }
2927
2928 pccbb_open_win(sc, rb->rb_bt, *addrp, size, *bshp, 0);
2929
2930 return 0;
2931 }
2932
2933 /*
2934 * int
2935 * pccbb_rbus_cb_space_free(cardbus_chipset_tag_t *ct, rbus_tag_t rb,
2936 * bus_space_handle_t *bshp, bus_size_t size);
2937 *
2938 * This function is called from CardBus card drivers.
2939 */
2940 int
pccbb_rbus_cb_space_free(ct,rb,bsh,size)2941 pccbb_rbus_cb_space_free(ct, rb, bsh, size)
2942 cardbus_chipset_tag_t ct;
2943 rbus_tag_t rb;
2944 bus_space_handle_t bsh;
2945 bus_size_t size;
2946 {
2947 struct pccbb_softc *sc = (struct pccbb_softc *)ct;
2948 bus_space_tag_t bt = rb->rb_bt;
2949
2950 pccbb_close_win(sc, bt, bsh, size);
2951
2952 if (bt == sc->sc_memt) {
2953 } else if (bt == sc->sc_iot) {
2954 } else {
2955 return 1;
2956 /* XXX: panic here? */
2957 }
2958
2959 return rbus_space_free(rb, bsh, size, NULL);
2960 }
2961 #endif /* rbus */
2962
2963 #if rbus
2964
2965 int
pccbb_open_win(sc,bst,addr,size,bsh,flags)2966 pccbb_open_win(sc, bst, addr, size, bsh, flags)
2967 struct pccbb_softc *sc;
2968 bus_space_tag_t bst;
2969 bus_addr_t addr;
2970 bus_size_t size;
2971 bus_space_handle_t bsh;
2972 int flags;
2973 {
2974 struct pccbb_win_chain_head *head;
2975 bus_addr_t align;
2976
2977 head = &sc->sc_iowindow;
2978 align = 0x04;
2979 if (sc->sc_memt == bst) {
2980 head = &sc->sc_memwindow;
2981 align = 0x1000;
2982 DPRINTF(("using memory window, %x %x %x\n\n",
2983 sc->sc_iot, sc->sc_memt, bst));
2984 }
2985
2986 if (pccbb_winlist_insert(head, addr, size, bsh, flags)) {
2987 printf("%s: pccbb_open_win: %s winlist insert failed\n",
2988 sc->sc_dev.dv_xname,
2989 (head == &sc->sc_memwindow) ? "mem" : "io");
2990 }
2991 pccbb_winset(align, sc, bst);
2992
2993 return 0;
2994 }
2995
2996 int
pccbb_close_win(sc,bst,bsh,size)2997 pccbb_close_win(sc, bst, bsh, size)
2998 struct pccbb_softc *sc;
2999 bus_space_tag_t bst;
3000 bus_space_handle_t bsh;
3001 bus_size_t size;
3002 {
3003 struct pccbb_win_chain_head *head;
3004 bus_addr_t align;
3005
3006 head = &sc->sc_iowindow;
3007 align = 0x04;
3008 if (sc->sc_memt == bst) {
3009 head = &sc->sc_memwindow;
3010 align = 0x1000;
3011 }
3012
3013 if (pccbb_winlist_delete(head, bsh, size)) {
3014 printf("%s: pccbb_close_win: %s winlist delete failed\n",
3015 sc->sc_dev.dv_xname,
3016 (head == &sc->sc_memwindow) ? "mem" : "io");
3017 }
3018 pccbb_winset(align, sc, bst);
3019
3020 return 0;
3021 }
3022
3023 int
pccbb_winlist_insert(head,start,size,bsh,flags)3024 pccbb_winlist_insert(head, start, size, bsh, flags)
3025 struct pccbb_win_chain_head *head;
3026 bus_addr_t start;
3027 bus_size_t size;
3028 bus_space_handle_t bsh;
3029 int flags;
3030 {
3031 struct pccbb_win_chain *chainp, *elem;
3032
3033 if ((elem = malloc(sizeof(struct pccbb_win_chain), M_DEVBUF,
3034 M_NOWAIT)) == NULL)
3035 return (1); /* fail */
3036
3037 elem->wc_start = start;
3038 elem->wc_end = start + (size - 1);
3039 elem->wc_handle = bsh;
3040 elem->wc_flags = flags;
3041
3042 for (chainp = TAILQ_FIRST(head); chainp != NULL;
3043 chainp = TAILQ_NEXT(chainp, wc_list)) {
3044 if (chainp->wc_end < start)
3045 continue;
3046 TAILQ_INSERT_AFTER(head, chainp, elem, wc_list);
3047 return (0);
3048 }
3049
3050 TAILQ_INSERT_TAIL(head, elem, wc_list);
3051 return (0);
3052 }
3053
3054 int
pccbb_winlist_delete(head,bsh,size)3055 pccbb_winlist_delete(head, bsh, size)
3056 struct pccbb_win_chain_head *head;
3057 bus_space_handle_t bsh;
3058 bus_size_t size;
3059 {
3060 struct pccbb_win_chain *chainp;
3061
3062 for (chainp = TAILQ_FIRST(head); chainp != NULL;
3063 chainp = TAILQ_NEXT(chainp, wc_list)) {
3064 if (chainp->wc_handle != bsh)
3065 continue;
3066 if ((chainp->wc_end - chainp->wc_start) != (size - 1)) {
3067 printf("pccbb_winlist_delete: window 0x%lx size "
3068 "inconsistent: 0x%lx, 0x%lx\n",
3069 chainp->wc_start,
3070 chainp->wc_end - chainp->wc_start,
3071 size - 1);
3072 return 1;
3073 }
3074
3075 TAILQ_REMOVE(head, chainp, wc_list);
3076 free(chainp, M_DEVBUF);
3077
3078 return 0;
3079 }
3080
3081 return 1; /* fail: no candidate to remove */
3082 }
3083
3084 void
pccbb_winset(align,sc,bst)3085 pccbb_winset(align, sc, bst)
3086 bus_addr_t align;
3087 struct pccbb_softc *sc;
3088 bus_space_tag_t bst;
3089 {
3090 pci_chipset_tag_t pc;
3091 pcitag_t tag;
3092 bus_addr_t mask = ~(align - 1);
3093 struct {
3094 cardbusreg_t win_start;
3095 cardbusreg_t win_limit;
3096 int win_flags;
3097 } win[2];
3098 struct pccbb_win_chain *chainp;
3099 int offs;
3100
3101 win[0].win_start = win[1].win_start = 0xffffffff;
3102 win[0].win_limit = win[1].win_limit = 0;
3103 win[0].win_flags = win[1].win_flags = 0;
3104
3105 chainp = TAILQ_FIRST(&sc->sc_iowindow);
3106 offs = 0x2c;
3107 if (sc->sc_memt == bst) {
3108 chainp = TAILQ_FIRST(&sc->sc_memwindow);
3109 offs = 0x1c;
3110 }
3111
3112 if (chainp != NULL) {
3113 win[0].win_start = chainp->wc_start & mask;
3114 win[0].win_limit = chainp->wc_end & mask;
3115 win[0].win_flags = chainp->wc_flags;
3116 chainp = TAILQ_NEXT(chainp, wc_list);
3117 }
3118
3119 for (; chainp != NULL; chainp = TAILQ_NEXT(chainp, wc_list)) {
3120 if (win[1].win_start == 0xffffffff) {
3121 /* window 1 is not used */
3122 if ((win[0].win_flags == chainp->wc_flags) &&
3123 (win[0].win_limit + align >=
3124 (chainp->wc_start & mask))) {
3125 /* concatenate */
3126 win[0].win_limit = chainp->wc_end & mask;
3127 } else {
3128 /* make new window */
3129 win[1].win_start = chainp->wc_start & mask;
3130 win[1].win_limit = chainp->wc_end & mask;
3131 win[1].win_flags = chainp->wc_flags;
3132 }
3133 continue;
3134 }
3135
3136 /* Both windows are engaged. */
3137 if (win[0].win_flags == win[1].win_flags) {
3138 /* same flags */
3139 if (win[0].win_flags == chainp->wc_flags) {
3140 if (win[1].win_start - (win[0].win_limit +
3141 align) <
3142 (chainp->wc_start & mask) -
3143 ((chainp->wc_end & mask) + align)) {
3144 /*
3145 * merge window 0 and 1, and set win1
3146 * to chainp
3147 */
3148 win[0].win_limit = win[1].win_limit;
3149 win[1].win_start =
3150 chainp->wc_start & mask;
3151 win[1].win_limit =
3152 chainp->wc_end & mask;
3153 } else {
3154 win[1].win_limit =
3155 chainp->wc_end & mask;
3156 }
3157 } else {
3158 /* different flags */
3159
3160 /* concatenate win0 and win1 */
3161 win[0].win_limit = win[1].win_limit;
3162 /* allocate win[1] to new space */
3163 win[1].win_start = chainp->wc_start & mask;
3164 win[1].win_limit = chainp->wc_end & mask;
3165 win[1].win_flags = chainp->wc_flags;
3166 }
3167 } else {
3168 /* the flags of win[0] and win[1] is different */
3169 if (win[0].win_flags == chainp->wc_flags) {
3170 win[0].win_limit = chainp->wc_end & mask;
3171 /*
3172 * XXX this creates overlapping windows, so
3173 * what should the poor bridge do if one is
3174 * cachable, and the other is not?
3175 */
3176 printf("%s: overlapping windows\n",
3177 sc->sc_dev.dv_xname);
3178 } else {
3179 win[1].win_limit = chainp->wc_end & mask;
3180 }
3181 }
3182 }
3183
3184 pc = sc->sc_pc;
3185 tag = sc->sc_tag;
3186 pci_conf_write(pc, tag, offs, win[0].win_start);
3187 pci_conf_write(pc, tag, offs + 4, win[0].win_limit);
3188 pci_conf_write(pc, tag, offs + 8, win[1].win_start);
3189 pci_conf_write(pc, tag, offs + 12, win[1].win_limit);
3190 DPRINTF(("--pccbb_winset: win0 [%x, %lx), win1 [%x, %lx)\n",
3191 pci_conf_read(pc, tag, offs),
3192 pci_conf_read(pc, tag, offs + 4) + align,
3193 pci_conf_read(pc, tag, offs + 8),
3194 pci_conf_read(pc, tag, offs + 12) + align));
3195
3196 if (bst == sc->sc_memt) {
3197 pcireg_t bcr = pci_conf_read(pc, tag, PCI_BCR_INTR);
3198
3199 bcr &= ~(CB_BCR_PREFETCH_MEMWIN0 | CB_BCR_PREFETCH_MEMWIN1);
3200 if (win[0].win_flags & PCCBB_MEM_CACHABLE)
3201 bcr |= CB_BCR_PREFETCH_MEMWIN0;
3202 if (win[1].win_flags & PCCBB_MEM_CACHABLE)
3203 bcr |= CB_BCR_PREFETCH_MEMWIN1;
3204 pci_conf_write(pc, tag, PCI_BCR_INTR, bcr);
3205 }
3206 }
3207
3208 #endif /* rbus */
3209
3210 void
pccbb_powerhook(why,arg)3211 pccbb_powerhook(why, arg)
3212 int why;
3213 void *arg;
3214 {
3215 struct pccbb_softc *sc = arg;
3216 u_int32_t reg;
3217 bus_space_tag_t base_memt = sc->sc_base_memt; /* socket regs memory */
3218 bus_space_handle_t base_memh = sc->sc_base_memh;
3219
3220 DPRINTF(("%s: power: why %d\n", sc->sc_dev.dv_xname, why));
3221
3222 if (why == PWR_SUSPEND || why == PWR_STANDBY) {
3223 DPRINTF(("%s: power: why %d stopping intr\n",
3224 sc->sc_dev.dv_xname, why));
3225 if (sc->sc_pil_intr_enable) {
3226 (void)pccbbintr_function(sc);
3227 }
3228 sc->sc_pil_intr_enable = 0;
3229
3230 /* ToDo: deactivate or suspend child devices */
3231
3232 }
3233
3234 if (why == PWR_RESUME) {
3235 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_SOCKBASE) == 0)
3236 /* BIOS did not recover this register */
3237 pci_conf_write (sc->sc_pc, sc->sc_tag,
3238 PCI_SOCKBASE, sc->sc_sockbase);
3239 if (pci_conf_read (sc->sc_pc, sc->sc_tag, PCI_BUSNUM) == 0)
3240 /* BIOS did not recover this register */
3241 pci_conf_write (sc->sc_pc, sc->sc_tag,
3242 PCI_BUSNUM, sc->sc_busnum);
3243 /* CSC Interrupt: Card detect interrupt on */
3244 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_MASK);
3245 /* Card detect intr is turned on. */
3246 reg |= CB_SOCKET_MASK_CD;
3247 bus_space_write_4(base_memt, base_memh, CB_SOCKET_MASK, reg);
3248 /* reset interrupt */
3249 reg = bus_space_read_4(base_memt, base_memh, CB_SOCKET_EVENT);
3250 bus_space_write_4(base_memt, base_memh, CB_SOCKET_EVENT, reg);
3251
3252 /*
3253 * check for card insertion or removal during suspend period.
3254 * XXX: the code can't cope with card swap (remove then
3255 * insert). how can we detect such situation?
3256 */
3257 (void)pccbbintr(sc);
3258
3259 sc->sc_pil_intr_enable = 1;
3260 DPRINTF(("%s: power: RESUME enabling intr\n",
3261 sc->sc_dev.dv_xname));
3262
3263 /* ToDo: activate or wakeup child devices */
3264 }
3265 }
3266