1 /* $MirOS: src/sys/dev/pci/isesreg.h,v 1.2 2013/10/31 20:06:55 tg Exp $ */ 2 /* $OpenBSD: isesreg.h,v 1.9 2003/06/07 11:31:24 ho Exp $ $ */ 3 4 /* 5 * Copyright © 2013 6 * Thorsten “mirabilos” Glaser <tg@mirbsd.org> 7 * Copyright (c) 2000 H�kan Olsson (ho@crt.se) 8 * Copyright (c) 2000 Theo de Raadt 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Register definitions for Pijnenburg PCC-ISES crypto chip. 34 * Definitions from revision 1.6 of the product datasheet. 35 */ 36 37 /* 38 * PCC-ISES Evaluation board DMA offsets 39 */ 40 #define ISES_DMA_READ_COUNT 0x0100 /* bit 31-16 */ 41 #define ISES_DMA_RCOUNT(x) ((x) << 16) 42 #define ISES_DMA_WRITE_COUNT 0x0100 /* bit 15-0 */ 43 #define ISES_DMA_WCOUNT(x) ((x) & 0x00FF) 44 45 #define ISES_DMA_WRITE_START 0x0104 46 #define ISES_DMA_READ_START 0x0108 47 #define ISES_DMA_CTRL 0x010C 48 #define ISES_DMA_STATUS ISES_DMA_CTRL 49 #define ISES_DMA_RESET 0x0110 50 51 #define ISES_DMA_CTRL_ILT 0x40000000 /* Ignore Latency Timer */ 52 #define ISES_DMA_CTRL_RMULT 0x0D000000 /* Enable PCI Read Multiple */ 53 #define ISES_DMA_CTRL_RLINE 0x09000000 /* Enable PCI Read Line */ 54 #define ISES_DMA_CTRL_READ 0x01000000 /* Enable PCI Read */ 55 #define ISES_DMA_CTRL_WRITE 0x00000100 /* Enable PCI Write */ 56 57 #define ISES_DMA_STATUS_R_RUN 0x01000000 /* PCI Read running */ 58 #define ISES_DMA_STATUS_R_ERR 0x02000000 /* PCI Read error */ 59 #define ISES_DMA_STATUS_W_RUN 0x00000100 /* PCI Write running */ 60 #define ISES_DMA_STATUS_W_ERR 0x00000200 /* PCI Write error */ 61 62 /* 63 * PCC-ISES A-interface 64 */ 65 66 #define ISES_A_OFFSET 0x0200 67 #define ISES_A(x) (ISES_A_OFFSET + (x)) 68 69 #define ISES_A_STAT ISES_A(0x00) /* status register */ 70 #define ISES_A_INTS ISES_A(0x04) /* interupt status register */ 71 #define ISES_A_INTE ISES_A(0x08) /* interupt enable register */ 72 #define ISES_A_SREQ ISES_A(0x0C) /* service request (read) */ 73 #define ISES_A_CTRL ISES_A_SREQ /* control register (write) */ 74 #define ISES_A_OQD ISES_A(0x10) /* Output Queue Data (read) */ 75 #define ISES_A_IQD ISES_A_OQD /* Input Queue Data (write) */ 76 #define ISES_A_OQS ISES_A(0x14) /* Output Queue Semaphore */ 77 #define ISES_A_IQS ISES_A(0x18) /* Input Queue Semaphore */ 78 #define ISES_A_OQF ISES_A(0x1C) /* Output Queue Filled (ro) */ 79 #define ISES_A_IQF ISES_A(0x20) /* Input Queue Free (ro) */ 80 81 /* 82 * PCC-ISES B-interface 83 */ 84 85 #define ISES_B_OFFSET 0x0300 86 #define ISES_B(x) (ISES_B_OFFSET + (x)) 87 88 #define ISES_B_BDATAIN ISES_B(0x0) 89 #define ISES_B_BDATAOUT ISES_B(0x4) 90 #define ISES_B_STAT ISES_B(0x8) 91 92 /* 93 * PCC-ISES I-interface (not used) 94 */ 95 96 #define ISES_I_OFFSET 0x0400 97 98 /* 99 * PCC-ISES board registers 100 */ 101 102 #define ISES_BO_OFFSET 0x0500 103 #define ISES_BO(x) (ISES_BO_OFFSET + (x)) 104 105 #define ISES_BO_STAT ISES_BO(0x0) 106 #define ISES_BO_LOOPCOUNTER ISES_BO(0x4) 107 #define ISES_BO_TESTREG ISES_BO(0x8) 108 109 #define ISES_BO_STAT_LOOP 0x00000001 /* B-interface LoopMode */ 110 #define ISES_BO_STAT_TAMPER 0x00000002 /* Set tamper */ 111 #define ISES_BO_STAT_POWERDOWN 0x00000004 /* Set power down */ 112 #define ISES_BO_STAT_ACONF 0x00000008 /* Set A-intf access to 16b */ 113 #define ISES_BO_STAT_HWRESET 0x00000010 /* Reset PCC-ISES (hw) */ 114 #define ISES_BO_STAT_AIRQ 0x00000020 /* A-interface interrupt (ro)*/ 115 116 /* 117 * PCC-ISES A-interface STAT register bits 118 */ 119 120 #define ISES_STAT_LNAU_MASKED 0x00000001 /* LNAU flags masked, this bit 121 must be zero for the other 122 LNAU flags to be read 123 correctly. */ 124 #define ISES_STAT_LNAU_BUSY_1 0x00000002 /* LNAU unit 1 is busy */ 125 #define ISES_STAT_LNAU_ERR_1 0x00000004 /* LNAU unit 1 error */ 126 #define ISES_STAT_LNAU_BUSY_2 0x00000008 /* LNAU unit 2 is busy */ 127 #define ISES_STAT_LNAU_ERR_2 0x00000010 /* LNAU unit 2 error */ 128 #define ISES_STAT_BCHU_MASKED 0x00000020 /* BCHU flags masked */ 129 #define ISES_STAT_BCHU_BUSY 0x00000040 /* BCHU is busy */ 130 #define ISES_STAT_BCHU_ERR 0x00000080 /* BCHU error flag */ 131 #define ISES_STAT_BCHU_SCIF 0x00000100 /* symm. crypto inoperative */ 132 #define ISES_STAT_BCHU_HIF 0x00000200 /* hash unit inoperative */ 133 #define ISES_STAT_BCHU_DDB 0x00000400 /* discard data blocks */ 134 #define ISES_STAT_BCHU_IRF 0x00000800 /* input request flag */ 135 #define ISES_STAT_BCHU_OAF 0x00001000 /* output available flag */ 136 #define ISES_STAT_BCHU_DIE 0x00002000 /* data input enabled */ 137 #define ISES_STAT_BCHU_UE 0x00004000 /* unit enable bit */ 138 #define ISES_STAT_BCHU_IFE 0x00008000 /* input FIFO empty */ 139 #define ISES_STAT_BCHU_IFHE 0x00010000 /* input FIFO half emtpy */ 140 #define ISES_STAT_BCHU_IFF 0x00020000 /* input FIFO full */ 141 #define ISES_STAT_BCHU_OFE 0x00040000 /* output FIFO emtpy */ 142 #define ISES_STAT_BCHU_OFHF 0x00080000 /* output FIFO half full */ 143 #define ISES_STAT_BCHU_OFF 0x00100000 /* output FIFO full */ 144 #define ISES_STAT_HW_DA 0x00200000 /* downloaded appl flag */ 145 #define ISES_STAT_HW_ACONF 0x00400000 /* A-intf configuration flag */ 146 #define ISES_STAT_SW_WFOQ 0x00800000 /* SW: Waiting for out queue */ 147 #define ISES_STAT_SW_OQSINC 0x08000000 /* SW 2.x: OQS increased */ 148 149 #define ISES_STAT_IDP_MASK 0x0f000000 /* IDP state mask (HW_DA=0) */ 150 #define ISES_STAT_IDP_STATE(x) (((x) & ISES_STAT_IDP_MASK) >> 24) 151 #define ISES_IDP_WFPL 0x4 /* Waiting for pgm len state */ 152 153 static const char *ises_idp_state[] = 154 { 155 "reset state", /* 0x0 */ 156 "testing NSRAM", /* 0x1 */ 157 "checking for firmware", /* 0x2 */ 158 "clearing NSRAM", /* 0x3 */ 159 "waiting for program length", /* 0x4 */ 160 "waiting for program data", /* 0x5 */ 161 "waiting for program CRC", /* 0x6 */ 162 "functional test program", /* 0x7 */ 163 0, 0, 0, 0, 0, 0, 0, /* 0x8-0xe */ 164 "Error: NSRAM or firmware failed" /* 0xf */ 165 }; 166 167 #define ISES_STAT_SW_MASK 0x03000000 /* SW mode (HW_DA=1) */ 168 #define ISES_STAT_SW_MODE(x) (((x) & ISES_STAT_SW_MASK) >> 24) 169 170 #define ISES_A_CTRL_RESET 0x0000 /* SW reset (go to ST mode) */ 171 #define ISES_A_CTRL_CONTINUE 0x0001 /* Return to CMD from WFC */ 172 173 #ifdef ISESDEBUG 174 static const char *ises_sw_mode[] = 175 { 176 "ST (SelfTest)", /* 0x0 */ 177 "CMD", /* 0x1 (normal) */ 178 "WFC (Wait for continue)", /* 0x2 */ 179 "CMD (Wait for reset)" /* 0x3 */ 180 }; 181 #endif 182 183 /* BERR (BCHU Error Register) */ 184 #define ISES_BERR_DPAR 0x00000001 /* DES parity error */ 185 #define ISES_BERR_IDESBCP 0x00000002 /* illegal DES mode value */ 186 #define ISES_BERR_ISFRBCP 0x00000004 /* illegal SAFER rounds spec */ 187 #define ISES_BERR_INCMBCP 0x00000008 /* illegal non-crypto mode */ 188 #define ISES_BERR_IBCF 0x00000010 /* illegal value in BCFR */ 189 #define ISES_BERR_reserved 0x00000020 /* reserved */ 190 #define ISES_BERR_SRB 0x00000040 /* write SCU while busy */ 191 #define ISES_BERR_HRB 0x00000080 /* write HU while busy */ 192 #define ISES_BERR_IHFR 0x00000100 /* illegal value in HFR */ 193 #define ISES_BERR_PADERR 0x00000200 /* padding error */ 194 #define ISES_BERR_BIDM 0x00000400 /* B-interface input data 195 misalignment */ 196 /* BCHCR (BCHU Control Register) */ 197 #define ISES_BCHCR_BCHU_DIE 0x00000001 /* data input enabled */ 198 #define ISES_BCHCR_BCHU_UE 0x00000002 /* unit enable */ 199 #define ISES_BCHCR_BCHU_RST 0x00000004 /* BCHU reset */ 200 201 /* 202 * OMR (Operation Method Register) 203 */ 204 /* -- SELR (Selector Register) */ 205 #define ISES_SELR_BCHU_EH 0x80000000 /* stop/continue on error */ 206 #define ISES_SELR_BCHU_HISOF 0x01000000 /* HU input is SCU output */ 207 #define ISES_SELR_BCHU_DIS 0x02000000 /* data interface select */ 208 209 /* -- HOMR (HU Operation Mode Register) */ 210 #define ISES_HOMR_HMTR 0x00800000 /* hash message type reg bit */ 211 #define ISES_HOMR_ER 0x00300000 /* BE/LE, 2bit mask */ 212 213 #define ISES_HOMR_HFR 0x00070000 /* Hash function mask, 3bits */ 214 #define ISES_HOMR_HFR_NOP 0x00000000 /* NOP */ 215 #define ISES_HOMR_HFR_MD5 0x00010000 /* MD5 */ 216 #define ISES_HOMR_HFR_RMD160 0x00020000 /* RIPEMD-160 */ 217 #define ISES_HOMR_HFR_RMD128 0x00030000 /* RIPEMD-128 */ 218 #define ISES_HOMR_HFR_SHA1 0x00040000 /* SHA-1 */ 219 220 /* -- SOMR (Symmetric crypto Operation Method Register) */ 221 #define ISES_SOMR_BCFR 0x0000f000 /* block cipher function reg */ 222 #define ISES_SOMR_BCPR 0x00000ff0 /* block cipher parameters */ 223 #define ISES_SOMR_BOMR (ISES_SOMR_BCFR | ISES_SOMR_BCPR) 224 #define ISES_SOMR_BOMR_NOP 0x00000000 /* NOP */ 225 #define ISES_SOMR_BOMR_TRANSPARENT 0x00000010 /* Transparent */ 226 #define ISES_SOMR_BOMR_DES 0x00001000 /* DES */ 227 #define ISES_SOMR_BOMR_3DES2 0x00001010 /* 3DES-2 */ 228 #define ISES_SOMR_BOMR_3DES 0x00001020 /* 3DES-3 */ 229 #define ISES_SOMR_BOMR_SAFER 0x00002000 /* SAFER (actually more) */ 230 #define ISES_SOMR_EDR 0x00000008 /* Encrypt/Decrypt register */ 231 #define ISES_SOMR_FMR 0x00000003 /* feedback mode mask */ 232 #define ISES_SOMR_FMR_ECB 0x00000000 /* EBC */ 233 #define ISES_SOMR_FMR_CBC 0x00000001 /* CBC */ 234 #define ISES_SOMR_FMR_CFB64 0x00000002 /* CFB64 */ 235 #define ISES_SOMR_FMR_OFB64 0x00000003 /* OFB64 */ 236 237 /* 238 * HRNG (Hardware Random Number Generator) 239 */ 240 #define ISES_OFFSET_HRNG_CTRL 0x00 /* Control register */ 241 #define ISES_OFFSET_HRNG_LFSR 0x04 /* Linear feedback shift reg */ 242 #define ISES_HRNG_CTRL_HE 0x00000001 /* HRNG enable */ 243 244 /* 245 * A-interface commands 246 */ 247 #define ISES_MKCMD(cmd,len) (cmd | cmd << 16 | len << 8 | len << 24) 248 #define ISES_CMD_NONE -1 249 250 /* Command name Code Len RLen Desc */ 251 #define ISES_CMD_CHIP_ID 0x00 /* 0 3 Read chipID */ 252 /* LNAU commands - LNAU 1 */ 253 #define ISES_CMD_LRESET_1 0x01 /* 0 0 LNAU reset */ 254 #define ISES_CMD_LRSFLG_1 0x02 /* 0 0 LNAU flags reset */ 255 #define ISES_CMD_LUPLOAD_1 0x03 /* 0 64 Upload result */ 256 #define ISES_CMD_LW_A_1 0x04 /* ?64 0 Load A register */ 257 #define ISES_CMD_LW_B_1 0x05 /* ?64 0 Load B register */ 258 #define ISES_CMD_LW_N_1 0x06 /* ?64 0 Load N register */ 259 #define ISES_CMD_LW_Bq_1 0x07 /* ?32 0 Load Bq register */ 260 #define ISES_CMD_LW_Nq_1 0x08 /* ?32 0 Load Nq register */ 261 #define ISES_CMD_LW_Bp_1 0x09 /* ?34 0 Load Bp register */ 262 #define ISES_CMD_LW_Np_1 0x0a /* ?34 0 Load Np register */ 263 #define ISES_CMD_LW_U_1 0x0b /* ?34 0 Load U register */ 264 #define ISES_CMD_LMOD_1 0x0c /* 0 0 Start A % N */ 265 #define ISES_CMD_LMULMOD_1 0x0d /* 0 0 Start (A*B) % N */ 266 #define ISES_CMD_LEXPMOD_1 0x0e /* 0 0 Start (A^B) % N */ 267 #define ISES_CMD_LEXPCRTMOD_1 0x0f /* 0 0 Start (A^B)%N w/ CRT */ 268 /* LNAU commands - LNAU 2 */ 269 #define ISES_CMD_LRESET_2 0x10 /* 0 0 Reset */ 270 #define ISES_CMD_LRSFLG_2 0x11 /* 0 0 Flags reset */ 271 #define ISES_CMD_LUPLOAD_2 0x12 /* 0 64 Upload result */ 272 #define ISES_CMD_LW_A_2 0x13 /* ?64 0 Load A register */ 273 #define ISES_CMD_LW_B_2 0x14 /* ?64 0 Load B register */ 274 #define ISES_CMD_LW_N_2 0x15 /* ?64 0 Load N register */ 275 #define ISES_CMD_LW_Bq_2 0x16 /* ?32 0 Load Bq register */ 276 #define ISES_CMD_LW_Nq_2 0x17 /* ?32 0 Load Nq register */ 277 #define ISES_CMD_LW_Bp_2 0x18 /* ?34 0 Load Bp register */ 278 #define ISES_CMD_LW_Np_2 0x19 /* ?34 0 Load Np register */ 279 #define ISES_CMD_LW_U_2 0x1a /* ?34 0 Load U register */ 280 #define ISES_CMD_LMOD_2 0x1b /* 0 0 Start A % N */ 281 #define ISES_CMD_LMULMOD_2 0x1c /* 0 0 Start (A*B) % N */ 282 #define ISES_CMD_LEXPMOD_2 0x1d /* 0 0 Start (A^B) % N */ 283 #define ISES_CMD_LEXPCRTMOD_2 0x1e /* 0 0 Start (A^B)%N w/ CRT */ 284 /* BCHU commands */ 285 #define ISES_CMD_RST_BERR 0x1f /* 0 0 Reset BERR */ 286 #define ISES_CMD_BR_BERR 0x20 /* 0 0 Read BERR */ 287 #define ISES_CMD_BW_DATA 0x21 /* 2 0 Write DATA */ 288 #define ISES_CMD_BR_DATA 0x22 /* 0 2 Read DATA */ 289 #define ISES_CMD_BW_BCHCR 0x23 /* 1 0 Write BCHCR */ 290 #define ISES_CMD_BR_BCHCR 0x24 /* 0 0 Read BCHCR */ 291 #define ISES_CMD_BW_OMR 0x25 /* 1 0 Write OMR */ 292 #define ISES_CMD_BR_OMR 0x26 /* 0 1 Read OMR */ 293 #define ISES_CMD_BW_KR0 0x27 /* 2 0 Write key 0 */ 294 #define ISES_CMD_BR_KR0 0x28 /* 0 2 Read key 0 */ 295 #define ISES_CMD_BW_KR1 0x29 /* 2 0 Write key 1 */ 296 #define ISES_CMD_BR_KR1 0x2a /* 0 2 Read key 1 */ 297 #define ISES_CMD_BW_KR2 0x2b /* 2 0 Write key 2 */ 298 #define ISES_CMD_BR_KR2 0x2c /* 0 2 Read key 2 */ 299 #define ISES_CMD_BW_SCCR 0x2d /* 2 0 Write SCCR */ 300 #define ISES_CMD_BR_SCCR 0x2e /* 0 2 Read SCCR */ 301 #define ISES_CMD_BW_DBCR 0x2f /* 2 0 Write DBCR */ 302 #define ISES_CMD_BR_DBCR 0x30 /* 0 2 Read DBCR */ 303 #define ISES_CMD_BW_HMLR 0x31 /* 2 0 Write HMLR */ 304 #define ISES_CMD_BR_HMLR 0x32 /* 0 2 Read HMLR */ 305 #define ISES_CMD_BW_CVR 0x33 /* 5 0 Write CVR */ 306 #define ISES_CMD_BR_CVR 0x34 /* 0 5 Read CVR */ 307 #define ISES_CMD_BPROC 0x35 /* ?255 ?255 Process data blocks */ 308 #define ISES_CMD_BTERM 0x36 /* 0 0 Terminate session */ 309 #define ISES_CMD_BSWITCH 0x37 /* 18 18 Switch BCHU session */ 310 /* HRNG commands */ 311 #define ISES_CMD_HSTART 0x38 /* 0 0 Start RBG unit */ 312 #define ISES_CMD_HSTOP 0x39 /* 0 0 Stop RGB unit */ 313 #define ISES_CMD_HSEED 0x3a /* 1 0 Seed LFSR */ 314 #define ISES_CMD_HBITS 0x3b /* 1 ?255 Return n*32 rnd bits */ 315 316 /* Command return codes (RC) */ 317 #define ISES_RC_MASK 0x0000ffff 318 #define ISES_RC_SUCCESS 0x0000 /* success */ 319 #define ISES_RC_CMDERR 0x0001 /* cmd interpretation error */ 320 #define ISES_RC_QERR 0x0002 /* queue handling error */ 321 #define ISES_RC_LNAU_ERR 0x0003 /* LNAU cmd proc error */ 322 #define ISES_RC_BCHU_ERR 0x0004 /* BCHU cmd proc error */ 323 #define ISES_RC_BCHU_BIFCSEL 0x0005 /* OMR says B-if, must be A */ 324 #define ISES_RC_BCHU_ODD 0x0006 /* odd #words in param list */ 325 #define ISES_RC_HRNG_ILLEN 0x0007 /* too large bitstream */ 326 327 /* Interrupt bits, IRQE, IRQES, IRQEC, IRQSS, IRQ registers */ 328 #define ISES_IRQ_TIMER_1 0x00000001 /* Timer 1 reached zero */ 329 #define ISES_IRQ_TIMER_2 0x00000002 /* Timer 2 reached zero */ 330 #define ISES_IRQ_I_IIN0 0x00000004 /* I-int 'Iin0' */ 331 #define ISES_IRQ_I_IIN1 0x00000008 /* I-int 'Iin1' */ 332 #define ISES_IRQ_I_IIN2 0x00000010 /* I-int 'Iin2' */ 333 #define ISES_IRQ_I_IIN3 0x00000020 /* I-int 'Iin3' */ 334 #define ISES_IRQ_LNAU_1_ERROR 0x00000040 /* LNAU 1 op error/abort */ 335 #define ISES_IRQ_LNAU_1_DONE 0x00000080 /* LNAU 1 op done */ 336 #define ISES_IRQ_LNAU_2_ERROR 0x00000100 /* LNAU 2 op error/abort */ 337 #define ISES_IRQ_LNAU_2_DONE 0x00000200 /* LNAU 1 op done */ 338 #define ISES_IRQ_BCHU_DONE 0x00000400 /* BCHU operation done */ 339 #define ISES_IRQ_BCHU_ERROR 0x00000800 /* BCHU operation error/abrt */ 340 #define ISES_IRQ_BCHU_IRF 0x00001000 /* BCHU input request flag >1*/ 341 #define ISES_IRQ_BCHU_OAF 0x00002000 /* BCHU output avail flag >1 */ 342 #define ISES_IRQ_BCHU_IEF 0x00004000 /* BCHU input empty flag >1 */ 343 #define ISES_IRQ_A_WCTRL 0x00008000 /* A-int CTRL reg was written*/ 344 #define ISES_IRQ_A_RSREQ 0x00010000 /* A-int SREQ reg was read */ 345 #define ISES_IRQ_A_DIQ 0x00020000 /* in queue emtpy, IQD write */ 346 #define ISES_IRQ_A_CIQ 0x00040000 /* in queue has complete cmd */ 347 #define ISES_IRQ_A_OQF 0x00080000 /* output queue full */ 348 349 #define ISES_SESSION(sid) ( (sid) & 0x0fffffff) 350 #define ISES_CARD(sid) (((sid) & 0xf0000000) >> 28) 351 #define ISES_SID(crd,ses) (((crd) << 28) | ((ses) & 0x0fffffff)) 352 353 /* Size and layout of ises_session is firmware dependent. */ 354 /* This structure should be usable for the SWITCH_SESSION command. */ 355 struct ises_session { 356 u_int32_t kr[6]; /* Key register KR2,KR1,KR0 */ 357 u_int32_t omr; /* Operation method register */ 358 359 /* The following values (on-chip) are cleared after an OMR write */ 360 u_int32_t sccr[2]; /* Symm. crypto chaining reg. (IV) */ 361 u_int32_t cvr[5]; /* Chaining variables reg. */ 362 u_int32_t dbcr[2]; /* Data block count register */ 363 u_int32_t hmlr[2]; /* Hash message length reg. */ 364 } __attribute__((__packed__)); 365 366 #define ISES_B_DATASIZE 4096 367