1 /* ISDN4BSD code */
2 /* $MirOS: src/sys/dev/pci/ifpci.c,v 1.1.7.1 2005/03/06 16:33:47 tg Exp $ */
3 /*
4 * Copyright (c) 1999 Gary Jennejohn. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the author nor the names of any co-contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 * 4. Altered versions must be plainly marked as such, and must not be
19 * misrepresented as being the original software and/or documentation.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 *---------------------------------------------------------------------------
34 * a lot of code was borrowed from i4b_bchan.c and i4b_hscx.c
35 *---------------------------------------------------------------------------
36 *
37 * Fritz!Card PCI driver
38 * ------------------------------------------------
39 *
40 * $Id: ifpci.c,v 1.4 2003/10/03 17:24:12 tg Stab $
41 *
42 * last edit-date: [Fri Jan 5 11:38:58 2001]
43 *
44 *---------------------------------------------------------------------------*/
45
46 #include <sys/cdefs.h>
47
48
49 #include <sys/param.h>
50 #include <sys/ioctl.h>
51 #include <sys/kernel.h>
52 #include <sys/systm.h>
53 #include <sys/mbuf.h>
54
55 #include <machine/bus.h>
56 #include <sys/device.h>
57
58 #include <sys/socket.h>
59 #include <net/if.h>
60
61 #include <sys/timeout.h>
62
63 #include <dev/pci/pcireg.h>
64 #include <dev/pci/pcivar.h>
65 #include <dev/pci/pcidevs.h>
66 #include <netisdn/i4b_debug.h>
67 #include <netisdn/i4b_ioctl.h>
68
69 #include <netisdn/i4b_global.h>
70 #include <netisdn/i4b_l2.h>
71 #include <netisdn/i4b_l1l2.h>
72 #include <netisdn/i4b_trace.h>
73 #include <netisdn/i4b_mbuf.h>
74
75 #include <dev/ic/isic_l1.h>
76 #include <dev/ic/isac.h>
77 #include <dev/ic/hscx.h>
78
79 #include <dev/pci/isic_pci.h>
80
81 /* PCI config map to use (only one in this driver) */
82 #define FRITZPCI_PORT0_IO_MAPOFF PCI_MAPREG_START+4
83 #define FRITZPCI_PORT0_MEM_MAPOFF PCI_MAPREG_START
84
85 static isdn_link_t *avma1pp_ret_linktab(void *token, int channel);
86 static void avma1pp_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc);
87
88 void n_connect_request(struct call_desc *cd);
89 void n_connect_response(struct call_desc *cd, int response, int cause);
90 void n_disconnect_request(struct call_desc *cd, int cause);
91 void n_alert_request(struct call_desc *cd);
92 void n_mgmt_command(struct isdn_l3_driver *drv, int cmd, void *parm);
93
94 extern const struct isdn_layer1_isdnif_driver isic_std_driver;
95
96 const struct isdn_l3_driver_functions
97 ifpci_l3_driver = {
98 avma1pp_ret_linktab,
99 avma1pp_set_link,
100 n_connect_request,
101 n_connect_response,
102 n_disconnect_request,
103 n_alert_request,
104 NULL,
105 NULL,
106 n_mgmt_command
107 };
108
109 struct ifpci_softc {
110 struct isic_softc sc_isic; /* parent class */
111
112 /* PCI-specific goo */
113 void *sc_ih; /* interrupt handler */
114 bus_addr_t sc_base;
115 bus_size_t sc_size;
116 pci_chipset_tag_t sc_pc;
117 };
118
119 /* prototypes */
120 static void avma1pp_disable(struct isic_softc *);
121 static int isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc);
122
123 static int avma1pp_intr(void*);
124 static void avma1pp_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size);
125 static void avma1pp_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size);
126 static void avma1pp_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data);
127 static u_int8_t avma1pp_read_reg(struct isic_softc *sc, int what, bus_size_t offs);
128 static void hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc);
129 static void hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc);
130 static void hscx_write_reg(int chan, u_int off, u_int val, struct isic_softc *sc);
131 static u_char hscx_read_reg(int chan, u_int off, struct isic_softc *sc);
132 static u_int hscx_read_reg_int(int chan, u_int off, struct isic_softc *sc);
133 static void avma1pp_bchannel_stat(isdn_layer1token, int h_chan, bchan_statistics_t *bsp);
134 static void avma1pp_map_int(struct ifpci_softc *sc, struct pci_attach_args *pa);
135 static void avma1pp_bchannel_setup(isdn_layer1token, int h_chan, int bprot, int activate);
136 static void avma1pp_init_linktab(struct isic_softc *);
137 static int ifpci_match(struct device *parent, struct cfdata *match, void *aux);
138 static void ifpci_attach(struct device *parent, struct device *self, void *aux);
139 static int ifpci_detach(struct device *self, int flags);
140 static int ifpci_activate(struct device *self, enum devact act);
141
142 CFATTACH_DECL(ifpci, sizeof(struct ifpci_softc),
143 ifpci_match, ifpci_attach, ifpci_detach, ifpci_activate);
144
145 struct cfdriver ifpci_cd = {
146 NULL, "ifpci", DV_IFNET
147 };
148
149 /*---------------------------------------------------------------------------*
150 * AVM PCI Fritz!Card special registers
151 *---------------------------------------------------------------------------*/
152
153 /*
154 * register offsets from i/o base
155 */
156 #define STAT0_OFFSET 0x02
157 #define STAT1_OFFSET 0x03
158 #define ADDR_REG_OFFSET 0x04
159 /*#define MODREG_OFFSET 0x06
160 #define VERREG_OFFSET 0x07*/
161
162 /* these 2 are used to select an ISAC register set */
163 #define ISAC_LO_REG_OFFSET 0x04
164 #define ISAC_HI_REG_OFFSET 0x06
165
166 /* offset higher than this goes to the HI register set */
167 #define MAX_LO_REG_OFFSET 0x2f
168
169 /* mask for the offset */
170 #define ISAC_REGSET_MASK 0x0f
171
172 /* the offset from the base to the ISAC registers */
173 #define ISAC_REG_OFFSET 0x10
174
175 /* the offset from the base to the ISAC FIFO */
176 #define ISAC_FIFO 0x02
177
178 /* not really the HSCX, but sort of */
179 #define HSCX_FIFO 0x00
180 #define HSCX_STAT 0x04
181
182 /*
183 * AVM PCI Status Latch 0 read only bits
184 */
185 #define ASL_IRQ_ISAC 0x01 /* ISAC interrupt, active low */
186 #define ASL_IRQ_HSCX 0x02 /* HSX interrupt, active low */
187 #define ASL_IRQ_TIMER 0x04 /* Timer interrupt, active low */
188 #define ASL_IRQ_BCHAN ASL_IRQ_HSCX
189 /* actually active LOW */
190 #define ASL_IRQ_Pending (ASL_IRQ_ISAC | ASL_IRQ_HSCX | ASL_IRQ_TIMER)
191
192 /*
193 * AVM Status Latch 0 write only bits
194 */
195 #define ASL_RESET_ALL 0x01 /* reset siemens IC's, active 1 */
196 #define ASL_TIMERDISABLE 0x02 /* active high */
197 #define ASL_TIMERRESET 0x04 /* active high */
198 #define ASL_ENABLE_INT 0x08 /* active high */
199 #define ASL_TESTBIT 0x10 /* active high */
200
201 /*
202 * AVM Status Latch 1 write only bits
203 */
204 #define ASL1_INTSEL 0x0f /* active high */
205 #define ASL1_ENABLE_IOM 0x80 /* active high */
206
207 /*
208 * "HSCX" mode bits
209 */
210 #define HSCX_MODE_ITF_FLG 0x01
211 #define HSCX_MODE_TRANS 0x02
212 #define HSCX_MODE_CCR_7 0x04
213 #define HSCX_MODE_CCR_16 0x08
214 #define HSCX_MODE_TESTLOOP 0x80
215
216 /*
217 * "HSCX" status bits
218 */
219 #define HSCX_STAT_RME 0x01
220 #define HSCX_STAT_RDO 0x10
221 #define HSCX_STAT_CRCVFRRAB 0x0E
222 #define HSCX_STAT_CRCVFR 0x06
223 #define HSCX_STAT_RML_MASK 0x3f00
224
225 /*
226 * "HSCX" interrupt bits
227 */
228 #define HSCX_INT_XPR 0x80
229 #define HSCX_INT_XDU 0x40
230 #define HSCX_INT_RPR 0x20
231 #define HSCX_INT_MASK 0xE0
232
233 /*
234 * "HSCX" command bits
235 */
236 #define HSCX_CMD_XRS 0x80
237 #define HSCX_CMD_XME 0x01
238 #define HSCX_CMD_RRS 0x20
239 #define HSCX_CMD_XML_MASK 0x3f00
240
241 /*
242 * Commands and parameters are sent to the "HSCX" as a long, but the
243 * fields are handled as bytes.
244 *
245 * The long contains:
246 * (prot << 16)|(txl << 8)|cmd
247 *
248 * where:
249 * prot = protocol to use
250 * txl = transmit length
251 * cmd = the command to be executed
252 *
253 * The fields are defined as u_char in struct isic_softc.
254 *
255 * Macro to coalesce the byte fields into a u_int
256 */
257 #define AVMA1PPSETCMDLONG(f) (f) = ((sc->avma1pp_cmd) | (sc->avma1pp_txl << 8) \
258 | (sc->avma1pp_prot << 16))
259
260 /*
261 * to prevent deactivating the "HSCX" when both channels are active we
262 * define an HSCX_ACTIVE flag which is or'd into the channel's state
263 * flag in avma1pp_bchannel_setup upon active and cleared upon deactivation.
264 * It is set high to allow room for new flags.
265 */
266 #define HSCX_AVMA1PP_ACTIVE 0x1000
267
268 static int
ifpci_match(struct device * parent,struct cfdata * match,void * aux)269 ifpci_match(struct device *parent, struct cfdata *match, void *aux)
270 {
271 struct pci_attach_args *pa = aux;
272
273 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AVM &&
274 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AVM_FRITZ_CARD)
275 return 1;
276 return 0;
277 }
278
279 static void
ifpci_attach(struct device * parent,struct device * self,void * aux)280 ifpci_attach(struct device *parent, struct device *self, void *aux)
281 {
282 struct ifpci_softc *psc = (void*)self;
283 struct pci_attach_args *pa = aux;
284 struct isic_softc *sc = &psc->sc_isic;
285 struct isdn_l3_driver *drv;
286 u_int v;
287
288 /* announce */
289 printf(": Fritz!PCI card\n");
290
291 /* init higher protocol layers */
292 drv = isdn_attach_isdnif(sc->sc_dev.dv_xname,
293 "AVM Fritz!PCI", &sc->sc_l2, &ifpci_l3_driver, NBCH_BRI);
294 sc->sc_l3token = drv;
295 sc->sc_l2.driver = &isic_std_driver;
296 sc->sc_l2.l1_token = sc;
297 sc->sc_l2.drv = drv;
298
299 /* setup io mappings */
300 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
301 sc->sc_num_mappings = 1;
302 MALLOC_MAPS(sc);
303 sc->sc_maps[0].size = 0;
304 if (pci_mapreg_map(pa, FRITZPCI_PORT0_MEM_MAPOFF, PCI_MAPREG_TYPE_MEM, 0,
305 &sc->sc_maps[0].t, &sc->sc_maps[0].h, &psc->sc_base, &psc->sc_size, 0) != 0
306 && pci_mapreg_map(pa, FRITZPCI_PORT0_IO_MAPOFF, PCI_MAPREG_TYPE_IO, 0,
307 &sc->sc_maps[0].t, &sc->sc_maps[0].h, &psc->sc_base, &psc->sc_size, 0) != 0) {
308 printf("%s: can't map card\n", sc->sc_dev.dv_xname);
309 return;
310 }
311
312 /* setup access routines */
313
314 sc->clearirq = NULL;
315 sc->readreg = avma1pp_read_reg;
316 sc->writereg = avma1pp_write_reg;
317
318 sc->readfifo = avma1pp_read_fifo;
319 sc->writefifo = avma1pp_write_fifo;
320
321
322 /* setup card type */
323
324 sc->sc_cardtyp = CARD_TYPEP_AVMA1PCI;
325
326 /* setup IOM bus type */
327
328 sc->sc_bustyp = BUS_TYPE_IOM2;
329
330 /* this is no IPAC based card */
331 sc->sc_ipac = 0;
332 sc->sc_bfifolen = HSCX_FIFO_LEN;
333
334 /* setup interrupt mapping */
335 avma1pp_map_int(psc, pa);
336
337 /* init the card */
338 /* the Linux driver does this to clear any pending ISAC interrupts */
339 /* see if it helps any - XXXX */
340 v = 0;
341 v = ISAC_READ(I_STAR);
342 v = ISAC_READ(I_MODE);
343 v = ISAC_READ(I_ADF2);
344 v = ISAC_READ(I_ISTA);
345 if (v & ISAC_ISTA_EXI)
346 {
347 v = ISAC_READ(I_EXIR);
348 }
349 v = ISAC_READ(I_CIRR);
350 ISAC_WRITE(I_MASK, 0xff);
351 /* the Linux driver does this to clear any pending HSCX interrupts */
352 v = hscx_read_reg_int(0, HSCX_STAT, sc);
353 v = hscx_read_reg_int(1, HSCX_STAT, sc);
354
355 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
356 DELAY(SEC_DELAY/100); /* 10 ms */
357 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_TIMERRESET|ASL_ENABLE_INT|ASL_TIMERDISABLE);
358 DELAY(SEC_DELAY/100); /* 10 ms */
359
360 /* setup i4b infrastructure (have to roll our own here) */
361
362 /* sc->sc_isac_version = ((ISAC_READ(I_RBCH)) >> 5) & 0x03; */
363 printf("%s: ISAC %s (IOM-%c)\n", sc->sc_dev.dv_xname,
364 "2085 Version A1/A2 or 2086/2186 Version 1.1",
365 sc->sc_bustyp == BUS_TYPE_IOM1 ? '1' : '2');
366
367 /* init the ISAC */
368 isic_isac_init(sc);
369
370 /* init the "HSCX" */
371 avma1pp_bchannel_setup(sc, HSCX_CH_A, BPROT_NONE, 0);
372
373 avma1pp_bchannel_setup(sc, HSCX_CH_B, BPROT_NONE, 0);
374
375 /* can't use the normal B-Channel stuff */
376 avma1pp_init_linktab(sc);
377
378 /* set trace level */
379
380 sc->sc_trace = TRACE_OFF;
381
382 sc->sc_state = ISAC_IDLE;
383
384 sc->sc_ibuf = NULL;
385 sc->sc_ib = NULL;
386 sc->sc_ilen = 0;
387
388 sc->sc_obuf = NULL;
389 sc->sc_op = NULL;
390 sc->sc_ol = 0;
391 sc->sc_freeflag = 0;
392
393 sc->sc_obuf2 = NULL;
394 sc->sc_freeflag2 = 0;
395
396 /* Activate higher protocol layers */
397 isdn_layer2_status_ind(&sc->sc_l2, drv, STI_ATTACH, 1);
398 isdn_isdnif_ready(drv->isdnif);
399 }
400
401 static int
ifpci_detach(self,flags)402 ifpci_detach(self, flags)
403 struct device *self;
404 int flags;
405 {
406 struct ifpci_softc *psc = (struct ifpci_softc *)self;
407
408 bus_space_unmap(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
409 bus_space_free(psc->sc_isic.sc_maps[0].t, psc->sc_isic.sc_maps[0].h, psc->sc_size);
410 pci_intr_disestablish(psc->sc_pc, psc->sc_ih);
411
412 return (0);
413 }
414
415 int
ifpci_activate(self,act)416 ifpci_activate(self, act)
417 struct device *self;
418 enum devact act;
419 {
420 struct ifpci_softc *psc = (struct ifpci_softc *)self;
421 int error = 0, s;
422
423 s = splnet();
424 switch (act) {
425 case DVACT_ACTIVATE:
426 error = EOPNOTSUPP;
427 break;
428
429 case DVACT_DEACTIVATE:
430 psc->sc_isic.sc_intr_valid = ISIC_INTR_DYING;
431 isdn_layer2_status_ind(&psc->sc_isic.sc_l2, psc->sc_isic.sc_l3token, STI_ATTACH, 0);
432 isdn_detach_isdnif(psc->sc_isic.sc_l3token);
433 psc->sc_isic.sc_l3token = NULL;
434 break;
435 }
436 splx(s);
437 return (error);
438 }
439
440 /*---------------------------------------------------------------------------*
441 * AVM read fifo routines
442 *---------------------------------------------------------------------------*/
443
444 static void
avma1pp_read_fifo(struct isic_softc * sc,int what,void * buf,size_t size)445 avma1pp_read_fifo(struct isic_softc *sc, int what, void *buf, size_t size)
446 {
447 switch (what) {
448 case ISIC_WHAT_ISAC:
449 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, ISAC_FIFO);
450 bus_space_read_multi_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET, buf, size);
451 break;
452 case ISIC_WHAT_HSCXA:
453 hscx_read_fifo(0, buf, size, sc);
454 break;
455 case ISIC_WHAT_HSCXB:
456 hscx_read_fifo(1, buf, size, sc);
457 break;
458 }
459 }
460
461 static void
hscx_read_fifo(int chan,void * buf,size_t len,struct isic_softc * sc)462 hscx_read_fifo(int chan, void *buf, size_t len, struct isic_softc *sc)
463 {
464 u_int32_t *ip;
465 size_t cnt;
466
467 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, chan);
468 ip = (u_int32_t *)buf;
469 cnt = 0;
470 /* what if len isn't a multiple of sizeof(int) and buf is */
471 /* too small ???? */
472 while (cnt < len)
473 {
474 *ip++ = bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET);
475 cnt += 4;
476 }
477 }
478
479 /*---------------------------------------------------------------------------*
480 * AVM write fifo routines
481 *---------------------------------------------------------------------------*/
482
483 static void
avma1pp_write_fifo(struct isic_softc * sc,int what,const void * buf,size_t size)484 avma1pp_write_fifo(struct isic_softc *sc, int what, const void *buf, size_t size)
485 {
486 switch (what) {
487 case ISIC_WHAT_ISAC:
488 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, ISAC_FIFO);
489 bus_space_write_multi_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET, (u_int8_t*)buf, size);
490 break;
491 case ISIC_WHAT_HSCXA:
492 hscx_write_fifo(0, buf, size, sc);
493 break;
494 case ISIC_WHAT_HSCXB:
495 hscx_write_fifo(1, buf, size, sc);
496 break;
497 }
498 }
499
500 static void
hscx_write_fifo(int chan,const void * buf,size_t len,struct isic_softc * sc)501 hscx_write_fifo(int chan, const void *buf, size_t len, struct isic_softc *sc)
502 {
503 u_int32_t *ip;
504 size_t cnt;
505 l1_bchan_state_t *Bchan = &sc->sc_chan[chan];
506
507 sc->avma1pp_cmd &= ~HSCX_CMD_XME;
508 sc->avma1pp_txl = 0;
509 if (Bchan->out_mbuf_cur == NULL)
510 {
511 if (Bchan->bprot != BPROT_NONE)
512 sc->avma1pp_cmd |= HSCX_CMD_XME;
513 }
514 if (len != sc->sc_bfifolen)
515 sc->avma1pp_txl = len;
516
517 cnt = 0; /* borrow cnt */
518 AVMA1PPSETCMDLONG(cnt);
519 hscx_write_reg(chan, HSCX_STAT, cnt, sc);
520
521 ip = (u_int32_t *)buf;
522 cnt = 0;
523 while (cnt < len)
524 {
525 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET, *ip);
526 ip++;
527 cnt += 4;
528 }
529 }
530
531 /*---------------------------------------------------------------------------*
532 * AVM write register routines
533 *---------------------------------------------------------------------------*/
534
535 static void
avma1pp_write_reg(struct isic_softc * sc,int what,bus_size_t offs,u_int8_t data)536 avma1pp_write_reg(struct isic_softc *sc, int what, bus_size_t offs, u_int8_t data)
537 {
538 u_char reg_bank;
539 switch (what) {
540 case ISIC_WHAT_ISAC:
541 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
542 /* set the register bank */
543 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, reg_bank);
544 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET + (offs & ISAC_REGSET_MASK), data);
545 break;
546 case ISIC_WHAT_HSCXA:
547 hscx_write_reg(0, offs, data, sc);
548 break;
549 case ISIC_WHAT_HSCXB:
550 hscx_write_reg(1, offs, data, sc);
551 break;
552 }
553 }
554
555 static void
hscx_write_reg(int chan,u_int off,u_int val,struct isic_softc * sc)556 hscx_write_reg(int chan, u_int off, u_int val, struct isic_softc *sc)
557 {
558 /* HACK */
559 if (off == H_MASK)
560 return;
561 /* point at the correct channel */
562 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, chan);
563 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET + off, val);
564 }
565
566 /*---------------------------------------------------------------------------*
567 * AVM read register routines
568 *---------------------------------------------------------------------------*/
569
570 static u_int8_t
avma1pp_read_reg(struct isic_softc * sc,int what,bus_size_t offs)571 avma1pp_read_reg(struct isic_softc *sc, int what, bus_size_t offs)
572 {
573 u_char reg_bank;
574 switch (what) {
575 case ISIC_WHAT_ISAC:
576 reg_bank = (offs > MAX_LO_REG_OFFSET) ? ISAC_HI_REG_OFFSET:ISAC_LO_REG_OFFSET;
577 /* set the register bank */
578 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, reg_bank);
579 return(bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET +
580 (offs & ISAC_REGSET_MASK)));
581 case ISIC_WHAT_HSCXA:
582 return hscx_read_reg(0, offs, sc);
583 case ISIC_WHAT_HSCXB:
584 return hscx_read_reg(1, offs, sc);
585 }
586 return 0;
587 }
588
589 static u_char
hscx_read_reg(int chan,u_int off,struct isic_softc * sc)590 hscx_read_reg(int chan, u_int off, struct isic_softc *sc)
591 {
592 return(hscx_read_reg_int(chan, off, sc) & 0xff);
593 }
594
595 /*
596 * need to be able to return an int because the RBCH is in the 2nd
597 * byte.
598 */
599 static u_int
hscx_read_reg_int(int chan,u_int off,struct isic_softc * sc)600 hscx_read_reg_int(int chan, u_int off, struct isic_softc *sc)
601 {
602 /* HACK */
603 if (off == H_ISTA)
604 return(0);
605 /* point at the correct channel */
606 bus_space_write_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ADDR_REG_OFFSET, chan);
607 return(bus_space_read_4(sc->sc_maps[0].t, sc->sc_maps[0].h, ISAC_REG_OFFSET + off));
608 }
609
610 /*
611 * this is the real interrupt routine
612 */
613 static void
avma1pp_hscx_intr(int h_chan,u_int stat,struct isic_softc * sc)614 avma1pp_hscx_intr(int h_chan, u_int stat, struct isic_softc *sc)
615 {
616 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
617 int activity = -1;
618 u_int param = 0;
619
620 NDBGL1(L1_H_IRQ, "%#x", stat);
621
622 if((stat & HSCX_INT_XDU) && (chan->bprot != BPROT_NONE))/* xmit data underrun */
623 {
624 chan->stat_XDU++;
625 NDBGL1(L1_H_XFRERR, "xmit data underrun");
626 /* abort the transmission */
627 sc->avma1pp_txl = 0;
628 sc->avma1pp_cmd |= HSCX_CMD_XRS;
629 AVMA1PPSETCMDLONG(param);
630 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
631 sc->avma1pp_cmd &= ~HSCX_CMD_XRS;
632 AVMA1PPSETCMDLONG(param);
633 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
634
635 if (chan->out_mbuf_head != NULL) /* don't continue to transmit this buffer */
636 {
637 i4b_Bfreembuf(chan->out_mbuf_head);
638 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
639 }
640 }
641
642 /*
643 * The following is based on examination of the Linux driver.
644 *
645 * The logic here is different than with a "real" HSCX; all kinds
646 * of information (interrupt/status bits) are in stat.
647 * HSCX_INT_RPR indicates a receive interrupt
648 * HSCX_STAT_RDO indicates an overrun condition, abort -
649 * otherwise read the bytes ((stat & HSCX_STZT_RML_MASK) >> 8)
650 * HSCX_STAT_RME indicates end-of-frame and apparently any
651 * CRC/framing errors are only reported in this state.
652 * if ((stat & HSCX_STAT_CRCVFRRAB) != HSCX_STAT_CRCVFR)
653 * CRC/framing error
654 */
655
656 if(stat & HSCX_INT_RPR)
657 {
658 register int fifo_data_len;
659 int error = 0;
660 /* always have to read the FIFO, so use a scratch buffer */
661 u_char scrbuf[HSCX_FIFO_LEN];
662
663 if(stat & HSCX_STAT_RDO)
664 {
665 chan->stat_RDO++;
666 NDBGL1(L1_H_XFRERR, "receive data overflow");
667 error++;
668 }
669
670 /*
671 * check whether we're receiving data for an inactive B-channel
672 * and discard it. This appears to happen for telephony when
673 * both B-channels are active and one is deactivated. Since
674 * it is not really possible to deactivate the channel in that
675 * case (the ASIC seems to deactivate _both_ channels), the
676 * "deactivated" channel keeps receiving data which can lead
677 * to exhaustion of mbufs and a kernel panic.
678 *
679 * This is a hack, but it's the only solution I can think of
680 * without having the documentation for the ASIC.
681 * GJ - 28 Nov 1999
682 */
683 if (chan->state == HSCX_IDLE)
684 {
685 NDBGL1(L1_H_XFRERR, "toss data from %d", h_chan);
686 error++;
687 }
688
689 fifo_data_len = ((stat & HSCX_STAT_RML_MASK) >> 8);
690
691 if(fifo_data_len == 0)
692 fifo_data_len = sc->sc_bfifolen;
693
694 /* ALWAYS read data from HSCX fifo */
695
696 HSCX_RDFIFO(h_chan, scrbuf, fifo_data_len);
697 chan->rxcount += fifo_data_len;
698
699 /* all error conditions checked, now decide and take action */
700
701 if(error == 0)
702 {
703 if(chan->in_mbuf == NULL)
704 {
705 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
706 panic("L1 avma1pp_hscx_intr: RME, cannot allocate mbuf!");
707 chan->in_cbptr = chan->in_mbuf->m_data;
708 chan->in_len = 0;
709 }
710
711 if((chan->in_len + fifo_data_len) <= BCH_MAX_DATALEN)
712 {
713 /* OK to copy the data */
714 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
715 chan->in_cbptr += fifo_data_len;
716 chan->in_len += fifo_data_len;
717
718 /* setup mbuf data length */
719
720 chan->in_mbuf->m_len = chan->in_len;
721 chan->in_mbuf->m_pkthdr.len = chan->in_len;
722
723 if(sc->sc_trace & TRACE_B_RX)
724 {
725 struct i4b_trace_hdr hdr;
726 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
727 hdr.dir = FROM_NT;
728 hdr.count = ++sc->sc_trace_bcount;
729 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
730 }
731
732 if (stat & HSCX_STAT_RME)
733 {
734 if((stat & HSCX_STAT_CRCVFRRAB) == HSCX_STAT_CRCVFR)
735 {
736 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
737 activity = ACT_RX;
738
739 /* mark buffer ptr as unused */
740
741 chan->in_mbuf = NULL;
742 chan->in_cbptr = NULL;
743 chan->in_len = 0;
744 }
745 else
746 {
747 chan->stat_CRC++;
748 NDBGL1(L1_H_XFRERR, "CRC/RAB");
749 if (chan->in_mbuf != NULL)
750 {
751 i4b_Bfreembuf(chan->in_mbuf);
752 chan->in_mbuf = NULL;
753 chan->in_cbptr = NULL;
754 chan->in_len = 0;
755 }
756 }
757 }
758 } /* END enough space in mbuf */
759 else
760 {
761 if(chan->bprot == BPROT_NONE)
762 {
763 /* setup mbuf data length */
764
765 chan->in_mbuf->m_len = chan->in_len;
766 chan->in_mbuf->m_pkthdr.len = chan->in_len;
767
768 if(sc->sc_trace & TRACE_B_RX)
769 {
770 struct i4b_trace_hdr hdr;
771 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
772 hdr.dir = FROM_NT;
773 hdr.count = ++sc->sc_trace_bcount;
774 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->in_mbuf->m_len, chan->in_mbuf->m_data);
775 }
776
777 if(!(isdn_bchan_silence(chan->in_mbuf->m_data, chan->in_mbuf->m_len)))
778 activity = ACT_RX;
779
780 /* move rx'd data to rx queue */
781
782 if (!(IF_QFULL(&chan->rx_queue)))
783 {
784 IF_ENQUEUE(&chan->rx_queue, chan->in_mbuf);
785 }
786 else
787 {
788 i4b_Bfreembuf(chan->in_mbuf);
789 }
790
791 /* signal upper layer that data are available */
792 (*chan->l4_driver->bch_rx_data_ready)(chan->l4_driver_softc);
793
794 /* alloc new buffer */
795
796 if((chan->in_mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
797 panic("L1 avma1pp_hscx_intr: RPF, cannot allocate new mbuf!");
798
799 /* setup new data ptr */
800
801 chan->in_cbptr = chan->in_mbuf->m_data;
802
803 /* OK to copy the data */
804 memcpy(chan->in_cbptr, scrbuf, fifo_data_len);
805
806 chan->in_cbptr += fifo_data_len;
807 chan->in_len = fifo_data_len;
808
809 chan->rxcount += fifo_data_len;
810 }
811 else
812 {
813 NDBGL1(L1_H_XFRERR, "RAWHDLC rx buffer overflow in RPF, in_len=%d", chan->in_len);
814 chan->in_cbptr = chan->in_mbuf->m_data;
815 chan->in_len = 0;
816 }
817 }
818 } /* if(error == 0) */
819 else
820 {
821 /* land here for RDO */
822 if (chan->in_mbuf != NULL)
823 {
824 i4b_Bfreembuf(chan->in_mbuf);
825 chan->in_mbuf = NULL;
826 chan->in_cbptr = NULL;
827 chan->in_len = 0;
828 }
829 sc->avma1pp_txl = 0;
830 sc->avma1pp_cmd |= HSCX_CMD_RRS;
831 AVMA1PPSETCMDLONG(param);
832 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
833 sc->avma1pp_cmd &= ~HSCX_CMD_RRS;
834 AVMA1PPSETCMDLONG(param);
835 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
836 }
837 }
838
839
840 /* transmit fifo empty, new data can be written to fifo */
841
842 if(stat & HSCX_INT_XPR)
843 {
844 /*
845 * for a description what is going on here, please have
846 * a look at isic_bchannel_start() in i4b_bchan.c !
847 */
848
849 NDBGL1(L1_H_IRQ, "%s: chan %d - XPR, Tx Fifo Empty!", sc->sc_dev.dv_xname, h_chan);
850
851 if(chan->out_mbuf_cur == NULL) /* last frame is transmitted */
852 {
853 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
854
855 if(chan->out_mbuf_head == NULL)
856 {
857 chan->state &= ~HSCX_TX_ACTIVE;
858 (*chan->l4_driver->bch_tx_queue_empty)(chan->l4_driver_softc);
859 }
860 else
861 {
862 chan->state |= HSCX_TX_ACTIVE;
863 chan->out_mbuf_cur = chan->out_mbuf_head;
864 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
865 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
866
867 if(sc->sc_trace & TRACE_B_TX)
868 {
869 struct i4b_trace_hdr hdr;
870 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
871 hdr.dir = FROM_TE;
872 hdr.count = ++sc->sc_trace_bcount;
873 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
874 }
875
876 if(chan->bprot == BPROT_NONE)
877 {
878 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
879 activity = ACT_TX;
880 }
881 else
882 {
883 activity = ACT_TX;
884 }
885 }
886 }
887
888 isic_hscx_fifo(chan, sc);
889 }
890
891 /* call timeout handling routine */
892
893 if(activity == ACT_RX || activity == ACT_TX)
894 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
895 }
896
897 /*
898 * this is the main routine which checks each channel and then calls
899 * the real interrupt routine as appropriate
900 */
901 static void
avma1pp_hscx_int_handler(struct isic_softc * sc)902 avma1pp_hscx_int_handler(struct isic_softc *sc)
903 {
904 u_int stat;
905
906 /* has to be a u_int because the byte count is in the 2nd byte */
907 stat = hscx_read_reg_int(0, HSCX_STAT, sc);
908 if (stat & HSCX_INT_MASK)
909 avma1pp_hscx_intr(0, stat, sc);
910 stat = hscx_read_reg_int(1, HSCX_STAT, sc);
911 if (stat & HSCX_INT_MASK)
912 avma1pp_hscx_intr(1, stat, sc);
913 }
914
915 static void
avma1pp_disable(struct isic_softc * sc)916 avma1pp_disable(struct isic_softc *sc)
917 {
918 bus_space_write_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET, ASL_RESET_ALL|ASL_TIMERDISABLE);
919 }
920
921 static int
avma1pp_intr(void * parm)922 avma1pp_intr(void * parm)
923 {
924 struct isic_softc *sc = parm;
925 int ret = 0;
926 #define OURS ret = 1
927 u_char stat;
928
929 if (sc->sc_intr_valid != ISIC_INTR_VALID)
930 return 0;
931
932 stat = bus_space_read_1(sc->sc_maps[0].t, sc->sc_maps[0].h, STAT0_OFFSET);
933 NDBGL1(L1_H_IRQ, "stat %x", stat);
934 /* was there an interrupt from this card ? */
935 if ((stat & ASL_IRQ_Pending) == ASL_IRQ_Pending)
936 return 0; /* no */
937 /* interrupts are low active */
938 if (!(stat & ASL_IRQ_TIMER))
939 NDBGL1(L1_H_IRQ, "timer interrupt ???");
940 if (!(stat & ASL_IRQ_HSCX))
941 {
942 NDBGL1(L1_H_IRQ, "HSCX");
943 avma1pp_hscx_int_handler(sc);
944 OURS;
945 }
946 if (!(stat & ASL_IRQ_ISAC))
947 {
948 NDBGL1(L1_H_IRQ, "ISAC");
949 for (;;) {
950 /* get isac irq status */
951 u_int8_t isac_irq_stat = ISAC_READ(I_ISTA);
952 if (!isac_irq_stat)
953 break;
954 isic_isac_irq(sc, isac_irq_stat);
955 }
956 OURS;
957 }
958 return ret;
959 }
960
961 static void
avma1pp_map_int(struct ifpci_softc * psc,struct pci_attach_args * pa)962 avma1pp_map_int(struct ifpci_softc *psc, struct pci_attach_args *pa)
963 {
964 struct isic_softc *sc = &psc->sc_isic;
965 pci_chipset_tag_t pc = pa->pa_pc;
966 pci_intr_handle_t ih;
967 const char *intrstr;
968
969 /* Map and establish the interrupt. */
970 if (pci_intr_map(pa, &ih)) {
971 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname);
972 avma1pp_disable(sc);
973 return;
974 }
975 psc->sc_pc = pc;
976 intrstr = pci_intr_string(pc, ih);
977 psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, avma1pp_intr, sc, sc->sc_dev.dv_xname);
978 if (psc->sc_ih == NULL) {
979 printf("%s: couldn't establish interrupt",
980 sc->sc_dev.dv_xname);
981 if (intrstr != NULL)
982 printf(" at %s", intrstr);
983 printf("\n");
984 avma1pp_disable(sc);
985 return;
986 }
987 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
988 }
989
990 static void
avma1pp_hscx_init(struct isic_softc * sc,int h_chan,int activate)991 avma1pp_hscx_init(struct isic_softc *sc, int h_chan, int activate)
992 {
993 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
994 u_int param = 0;
995
996 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
997 sc->sc_dev.dv_xname, h_chan, activate ? "activate" : "deactivate");
998
999 if (activate == 0)
1000 {
1001 /* only deactivate if both channels are idle */
1002 if (sc->sc_chan[HSCX_CH_A].state != HSCX_IDLE ||
1003 sc->sc_chan[HSCX_CH_B].state != HSCX_IDLE)
1004 {
1005 return;
1006 }
1007 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1008 sc->avma1pp_prot = HSCX_MODE_TRANS;
1009 AVMA1PPSETCMDLONG(param);
1010 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1011 return;
1012 }
1013 if(chan->bprot == BPROT_RHDLC)
1014 {
1015 NDBGL1(L1_BCHAN, "BPROT_RHDLC");
1016
1017 /* HDLC Frames, transparent mode 0 */
1018 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1019 sc->avma1pp_prot = HSCX_MODE_ITF_FLG;
1020 AVMA1PPSETCMDLONG(param);
1021 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1022 sc->avma1pp_cmd = HSCX_CMD_XRS;
1023 AVMA1PPSETCMDLONG(param);
1024 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1025 sc->avma1pp_cmd = 0;
1026 }
1027 else
1028 {
1029 NDBGL1(L1_BCHAN, "BPROT_NONE??");
1030
1031 /* Raw Telephony, extended transparent mode 1 */
1032 sc->avma1pp_cmd = HSCX_CMD_XRS|HSCX_CMD_RRS;
1033 sc->avma1pp_prot = HSCX_MODE_TRANS;
1034 AVMA1PPSETCMDLONG(param);
1035 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1036 sc->avma1pp_cmd = HSCX_CMD_XRS;
1037 AVMA1PPSETCMDLONG(param);
1038 hscx_write_reg(h_chan, HSCX_STAT, param, sc);
1039 sc->avma1pp_cmd = 0;
1040 }
1041 }
1042
1043 static void
avma1pp_bchannel_setup(isdn_layer1token t,int h_chan,int bprot,int activate)1044 avma1pp_bchannel_setup(isdn_layer1token t, int h_chan, int bprot, int activate)
1045 {
1046 struct isic_softc *sc = (struct isic_softc*)t;
1047 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1048
1049 int s = splnet();
1050
1051 if(activate == 0)
1052 {
1053 /* deactivation */
1054 chan->state = HSCX_IDLE;
1055 avma1pp_hscx_init(sc, h_chan, activate);
1056 }
1057
1058 NDBGL1(L1_BCHAN, "%s: channel=%d, %s",
1059 sc->sc_dev.dv_xname, h_chan, activate ? "activate" : "deactivate");
1060
1061 /* general part */
1062
1063 chan->channel = h_chan; /* B channel */
1064 chan->bprot = bprot; /* B channel protocol */
1065 chan->state = HSCX_IDLE; /* B channel state */
1066
1067 /* receiver part */
1068
1069 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1070
1071 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1072
1073 chan->rxcount = 0; /* reset rx counter */
1074
1075 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1076
1077 chan->in_mbuf = NULL; /* reset mbuf ptr */
1078 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1079 chan->in_len = 0; /* reset mbuf data len */
1080
1081 /* transmitter part */
1082
1083 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1084
1085 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1086
1087 chan->txcount = 0; /* reset tx counter */
1088
1089 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1090
1091 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1092 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1093 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1094 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1095
1096 if(activate != 0)
1097 {
1098 /* activation */
1099 avma1pp_hscx_init(sc, h_chan, activate);
1100 chan->state |= HSCX_AVMA1PP_ACTIVE;
1101 }
1102
1103 splx(s);
1104 }
1105
1106 static void
avma1pp_bchannel_start(isdn_layer1token t,int h_chan)1107 avma1pp_bchannel_start(isdn_layer1token t, int h_chan)
1108 {
1109 struct isic_softc *sc = (struct isic_softc*)t;
1110 register l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1111 int s;
1112 int activity = -1;
1113
1114 s = splnet(); /* enter critical section */
1115 if(chan->state & HSCX_TX_ACTIVE) /* already running ? */
1116 {
1117 splx(s);
1118 return; /* yes, leave */
1119 }
1120
1121 /* get next mbuf from queue */
1122
1123 IF_DEQUEUE(&chan->tx_queue, chan->out_mbuf_head);
1124
1125 if(chan->out_mbuf_head == NULL) /* queue empty ? */
1126 {
1127 splx(s); /* leave critical section */
1128 return; /* yes, exit */
1129 }
1130
1131 /* init current mbuf values */
1132
1133 chan->out_mbuf_cur = chan->out_mbuf_head;
1134 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1135 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1136
1137 /* activity indicator for timeout handling */
1138
1139 if(chan->bprot == BPROT_NONE)
1140 {
1141 if(!(isdn_bchan_silence(chan->out_mbuf_cur->m_data, chan->out_mbuf_cur->m_len)))
1142 activity = ACT_TX;
1143 }
1144 else
1145 {
1146 activity = ACT_TX;
1147 }
1148
1149 chan->state |= HSCX_TX_ACTIVE; /* we start transmitting */
1150
1151 if(sc->sc_trace & TRACE_B_TX) /* if trace, send mbuf to trace dev */
1152 {
1153 struct i4b_trace_hdr hdr;
1154 hdr.type = (h_chan == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1155 hdr.dir = FROM_TE;
1156 hdr.count = ++sc->sc_trace_bcount;
1157 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1158 }
1159
1160 isic_hscx_fifo(chan, sc);
1161
1162 /* call timeout handling routine */
1163
1164 if(activity == ACT_RX || activity == ACT_TX)
1165 (*chan->l4_driver->bch_activity)(chan->l4_driver_softc, activity);
1166
1167 splx(s);
1168 }
1169
1170 /*---------------------------------------------------------------------------*
1171 * return the address of isic drivers linktab
1172 *---------------------------------------------------------------------------*/
1173 static isdn_link_t *
avma1pp_ret_linktab(void * token,int channel)1174 avma1pp_ret_linktab(void *token, int channel)
1175 {
1176 struct l2_softc *l2sc = token;
1177 struct isic_softc *sc = l2sc->l1_token;
1178
1179 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1180
1181 return(&chan->isdn_linktab);
1182 }
1183
1184 /*---------------------------------------------------------------------------*
1185 * set the driver linktab in the b channel softc
1186 *---------------------------------------------------------------------------*/
1187 static void
avma1pp_set_link(void * token,int channel,const struct isdn_l4_driver_functions * l4_driver,void * l4_driver_softc)1188 avma1pp_set_link(void *token, int channel, const struct isdn_l4_driver_functions *l4_driver, void *l4_driver_softc)
1189 {
1190 struct l2_softc *l2sc = token;
1191 struct isic_softc *sc = l2sc->l1_token;
1192 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1193
1194 chan->l4_driver = l4_driver;
1195 chan->l4_driver_softc = l4_driver_softc;
1196 }
1197
1198 static const struct isdn_l4_bchannel_functions
1199 avma1pp_l4_bchannel_functions = {
1200 avma1pp_bchannel_setup,
1201 avma1pp_bchannel_start,
1202 avma1pp_bchannel_stat
1203 };
1204
1205 /*---------------------------------------------------------------------------*
1206 * initialize our local linktab
1207 *---------------------------------------------------------------------------*/
1208 static void
avma1pp_init_linktab(struct isic_softc * sc)1209 avma1pp_init_linktab(struct isic_softc *sc)
1210 {
1211 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
1212 isdn_link_t *lt = &chan->isdn_linktab;
1213
1214 /* local setup */
1215 lt->l1token = sc;
1216 lt->channel = HSCX_CH_A;
1217 lt->bchannel_driver = &avma1pp_l4_bchannel_functions;
1218 lt->tx_queue = &chan->tx_queue;
1219
1220 /* used by non-HDLC data transfers, i.e. telephony drivers */
1221 lt->rx_queue = &chan->rx_queue;
1222
1223 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1224 lt->rx_mbuf = &chan->in_mbuf;
1225
1226 chan = &sc->sc_chan[HSCX_CH_B];
1227 lt = &chan->isdn_linktab;
1228
1229 lt->l1token = sc;
1230 lt->channel = HSCX_CH_B;
1231 lt->bchannel_driver = &avma1pp_l4_bchannel_functions;
1232 lt->tx_queue = &chan->tx_queue;
1233
1234 /* used by non-HDLC data transfers, i.e. telephony drivers */
1235 lt->rx_queue = &chan->rx_queue;
1236
1237 /* used by HDLC data transfers, i.e. ipr and isp drivers */
1238 lt->rx_mbuf = &chan->in_mbuf;
1239 }
1240
1241 /*
1242 * use this instead of isic_bchannel_stat in i4b_bchan.c because it's static
1243 */
1244 static void
avma1pp_bchannel_stat(isdn_layer1token t,int h_chan,bchan_statistics_t * bsp)1245 avma1pp_bchannel_stat(isdn_layer1token t, int h_chan, bchan_statistics_t *bsp)
1246 {
1247 struct isic_softc *sc = (struct isic_softc*)t;
1248 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1249 int s;
1250
1251 s = splnet();
1252
1253 bsp->outbytes = chan->txcount;
1254 bsp->inbytes = chan->rxcount;
1255
1256 chan->txcount = 0;
1257 chan->rxcount = 0;
1258
1259 splx(s);
1260 }
1261
1262 /*---------------------------------------------------------------------------*
1263 * fill HSCX fifo with data from the current mbuf
1264 * Put this here until it can go into i4b_hscx.c
1265 *---------------------------------------------------------------------------*/
1266 static int
isic_hscx_fifo(l1_bchan_state_t * chan,struct isic_softc * sc)1267 isic_hscx_fifo(l1_bchan_state_t *chan, struct isic_softc *sc)
1268 {
1269 int len;
1270 int nextlen;
1271 int i;
1272 int cmd;
1273 /* using a scratch buffer simplifies writing to the FIFO */
1274 u_char scrbuf[HSCX_FIFO_LEN];
1275
1276 len = 0;
1277
1278 /*
1279 * fill the HSCX tx fifo with data from the current mbuf. if
1280 * current mbuf holds less data than HSCX fifo length, try to
1281 * get the next mbuf from (a possible) mbuf chain. if there is
1282 * not enough data in a single mbuf or in a chain, then this
1283 * is the last mbuf and we tell the HSCX that it has to send
1284 * CRC and closing flag
1285 */
1286
1287 while(chan->out_mbuf_cur && len != sc->sc_bfifolen)
1288 {
1289 nextlen = min(chan->out_mbuf_cur_len, sc->sc_bfifolen - len);
1290
1291 #ifdef NOTDEF
1292 printf("i:mh=%p, mc=%p, mcp=%p, mcl=%d l=%d nl=%d # ",
1293 chan->out_mbuf_head,
1294 chan->out_mbuf_cur,
1295 chan->out_mbuf_cur_ptr,
1296 chan->out_mbuf_cur_len,
1297 len,
1298 nextlen);
1299 #endif
1300
1301 cmd |= HSCX_CMDR_XTF;
1302 /* collect the data in the scratch buffer */
1303 for (i = 0; i < nextlen; i++)
1304 scrbuf[i + len] = chan->out_mbuf_cur_ptr[i];
1305
1306 len += nextlen;
1307 chan->txcount += nextlen;
1308
1309 chan->out_mbuf_cur_ptr += nextlen;
1310 chan->out_mbuf_cur_len -= nextlen;
1311
1312 if(chan->out_mbuf_cur_len == 0)
1313 {
1314 if((chan->out_mbuf_cur = chan->out_mbuf_cur->m_next) != NULL)
1315 {
1316 chan->out_mbuf_cur_ptr = chan->out_mbuf_cur->m_data;
1317 chan->out_mbuf_cur_len = chan->out_mbuf_cur->m_len;
1318
1319 if(sc->sc_trace & TRACE_B_TX)
1320 {
1321 struct i4b_trace_hdr hdr;
1322 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
1323 hdr.dir = FROM_TE;
1324 hdr.count = ++sc->sc_trace_bcount;
1325 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, chan->out_mbuf_cur->m_len, chan->out_mbuf_cur->m_data);
1326 }
1327 }
1328 else
1329 {
1330 if (chan->bprot != BPROT_NONE)
1331 cmd |= HSCX_CMDR_XME;
1332 i4b_Bfreembuf(chan->out_mbuf_head);
1333 chan->out_mbuf_head = NULL;
1334 }
1335 }
1336 }
1337 /* write what we have from the scratch buf to the HSCX fifo */
1338 if (len != 0)
1339 HSCX_WRFIFO(chan->channel, scrbuf, len);
1340 return(cmd);
1341 }
1342