1 /* $OpenBSD: if_wb.c,v 1.22 2003/08/19 14:01:35 mpech Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/pci/if_wb.c,v 1.26 1999/09/25 17:29:02 wpaul Exp $
35 */
36
37 /*
38 * Winbond fast ethernet PCI NIC driver
39 *
40 * Supports various cheap network adapters based on the Winbond W89C840F
41 * fast ethernet controller chip. This includes adapters manufactured by
42 * Winbond itself and some made by Linksys.
43 *
44 * Written by Bill Paul <wpaul@ctr.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
47 */
48
49 /*
50 * The Winbond W89C840F chip is a bus master; in some ways it resembles
51 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has
52 * one major difference which is that while the registers do many of
53 * the same things as a tulip adapter, the offsets are different: where
54 * tulip registers are typically spaced 8 bytes apart, the Winbond
55 * registers are spaced 4 bytes apart. The receiver filter is also
56 * programmed differently.
57 *
58 * Like the tulip, the Winbond chip uses small descriptors containing
59 * a status word, a control word and 32-bit areas that can either be used
60 * to point to two external data blocks, or to point to a single block
61 * and another descriptor in a linked list. Descriptors can be grouped
62 * together in blocks to form fixed length rings or can be chained
63 * together in linked lists. A single packet may be spread out over
64 * several descriptors if necessary.
65 *
66 * For the receive ring, this driver uses a linked list of descriptors,
67 * each pointing to a single mbuf cluster buffer, which us large enough
68 * to hold an entire packet. The link list is looped back to created a
69 * closed ring.
70 *
71 * For transmission, the driver creates a linked list of 'super descriptors'
72 * which each contain several individual descriptors linked toghether.
73 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we
74 * abuse as fragment pointers. This allows us to use a buffer management
75 * scheme very similar to that used in the ThunderLAN and Etherlink XL
76 * drivers.
77 *
78 * Autonegotiation is performed using the external PHY via the MII bus.
79 * The sample boards I have all use a Davicom PHY.
80 *
81 * Note: the author of the Linux driver for the Winbond chip alludes
82 * to some sort of flaw in the chip's design that seems to mandate some
83 * drastic workaround which signigicantly impairs transmit performance.
84 * I have no idea what he's on about: transmit performance with all
85 * three of my test boards seems fine.
86 */
87
88 #include "bpfilter.h"
89
90 #include <sys/param.h>
91 #include <sys/systm.h>
92 #include <sys/sockio.h>
93 #include <sys/mbuf.h>
94 #include <sys/malloc.h>
95 #include <sys/kernel.h>
96 #include <sys/socket.h>
97 #include <sys/device.h>
98 #include <sys/queue.h>
99 #include <sys/timeout.h>
100
101 #include <net/if.h>
102 #include <net/if_dl.h>
103 #include <net/if_types.h>
104
105 #ifdef INET
106 #include <netinet/in.h>
107 #include <netinet/in_systm.h>
108 #include <netinet/in_var.h>
109 #include <netinet/ip.h>
110 #include <netinet/if_ether.h>
111 #endif
112
113 #include <net/if_media.h>
114
115 #if NBPFILTER > 0
116 #include <net/bpf.h>
117 #endif
118
119 #include <uvm/uvm_extern.h> /* for vtophys */
120
121 #include <dev/mii/mii.h>
122 #include <dev/mii/miivar.h>
123 #include <dev/pci/pcireg.h>
124 #include <dev/pci/pcivar.h>
125 #include <dev/pci/pcidevs.h>
126
127 #define WB_USEIOSPACE
128
129 /* #define WB_BACKGROUND_AUTONEG */
130
131 #include <dev/pci/if_wbreg.h>
132
133 int wb_probe(struct device *, void *, void *);
134 void wb_attach(struct device *, struct device *, void *);
135
136 void wb_bfree(caddr_t, u_int, void *);
137 int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *,
138 struct mbuf *);
139 int wb_encap(struct wb_softc *, struct wb_chain *,
140 struct mbuf *);
141
142 void wb_rxeof(struct wb_softc *);
143 void wb_rxeoc(struct wb_softc *);
144 void wb_txeof(struct wb_softc *);
145 void wb_txeoc(struct wb_softc *);
146 int wb_intr(void *);
147 void wb_tick(void *);
148 void wb_start(struct ifnet *);
149 int wb_ioctl(struct ifnet *, u_long, caddr_t);
150 void wb_init(void *);
151 void wb_stop(struct wb_softc *);
152 void wb_watchdog(struct ifnet *);
153 void wb_shutdown(void *);
154 int wb_ifmedia_upd(struct ifnet *);
155 void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *);
156
157 void wb_eeprom_putbyte(struct wb_softc *, int);
158 void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *);
159 void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int);
160 void wb_mii_sync(struct wb_softc *);
161 void wb_mii_send(struct wb_softc *, u_int32_t, int);
162 int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *);
163 int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *);
164
165 void wb_setcfg(struct wb_softc *, u_int32_t);
166 u_int8_t wb_calchash(caddr_t);
167 void wb_setmulti(struct wb_softc *);
168 void wb_reset(struct wb_softc *);
169 void wb_fixmedia(struct wb_softc *);
170 int wb_list_rx_init(struct wb_softc *);
171 int wb_list_tx_init(struct wb_softc *);
172
173 int wb_miibus_readreg(struct device *, int, int);
174 void wb_miibus_writereg(struct device *, int, int, int);
175 void wb_miibus_statchg(struct device *);
176
177 #define WB_SETBIT(sc, reg, x) \
178 CSR_WRITE_4(sc, reg, \
179 CSR_READ_4(sc, reg) | x)
180
181 #define WB_CLRBIT(sc, reg, x) \
182 CSR_WRITE_4(sc, reg, \
183 CSR_READ_4(sc, reg) & ~x)
184
185 #define SIO_SET(x) \
186 CSR_WRITE_4(sc, WB_SIO, \
187 CSR_READ_4(sc, WB_SIO) | x)
188
189 #define SIO_CLR(x) \
190 CSR_WRITE_4(sc, WB_SIO, \
191 CSR_READ_4(sc, WB_SIO) & ~x)
192
193 /*
194 * Send a read command and address to the EEPROM, check for ACK.
195 */
wb_eeprom_putbyte(sc,addr)196 void wb_eeprom_putbyte(sc, addr)
197 struct wb_softc *sc;
198 int addr;
199 {
200 register int d, i;
201
202 d = addr | WB_EECMD_READ;
203
204 /*
205 * Feed in each bit and strobe the clock.
206 */
207 for (i = 0x400; i; i >>= 1) {
208 if (d & i) {
209 SIO_SET(WB_SIO_EE_DATAIN);
210 } else {
211 SIO_CLR(WB_SIO_EE_DATAIN);
212 }
213 DELAY(100);
214 SIO_SET(WB_SIO_EE_CLK);
215 DELAY(150);
216 SIO_CLR(WB_SIO_EE_CLK);
217 DELAY(100);
218 }
219
220 return;
221 }
222
223 /*
224 * Read a word of data stored in the EEPROM at address 'addr.'
225 */
wb_eeprom_getword(sc,addr,dest)226 void wb_eeprom_getword(sc, addr, dest)
227 struct wb_softc *sc;
228 int addr;
229 u_int16_t *dest;
230 {
231 register int i;
232 u_int16_t word = 0;
233
234 /* Enter EEPROM access mode. */
235 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
236
237 /*
238 * Send address of word we want to read.
239 */
240 wb_eeprom_putbyte(sc, addr);
241
242 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS);
243
244 /*
245 * Start reading bits from EEPROM.
246 */
247 for (i = 0x8000; i; i >>= 1) {
248 SIO_SET(WB_SIO_EE_CLK);
249 DELAY(100);
250 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT)
251 word |= i;
252 SIO_CLR(WB_SIO_EE_CLK);
253 DELAY(100);
254 }
255
256 /* Turn off EEPROM access mode. */
257 CSR_WRITE_4(sc, WB_SIO, 0);
258
259 *dest = word;
260
261 return;
262 }
263
264 /*
265 * Read a sequence of words from the EEPROM.
266 */
wb_read_eeprom(sc,dest,off,cnt,swap)267 void wb_read_eeprom(sc, dest, off, cnt, swap)
268 struct wb_softc *sc;
269 caddr_t dest;
270 int off;
271 int cnt;
272 int swap;
273 {
274 int i;
275 u_int16_t word = 0, *ptr;
276
277 for (i = 0; i < cnt; i++) {
278 wb_eeprom_getword(sc, off + i, &word);
279 ptr = (u_int16_t *)(dest + (i * 2));
280 if (swap)
281 *ptr = ntohs(word);
282 else
283 *ptr = word;
284 }
285
286 return;
287 }
288
289 /*
290 * Sync the PHYs by setting data bit and strobing the clock 32 times.
291 */
wb_mii_sync(sc)292 void wb_mii_sync(sc)
293 struct wb_softc *sc;
294 {
295 register int i;
296
297 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN);
298
299 for (i = 0; i < 32; i++) {
300 SIO_SET(WB_SIO_MII_CLK);
301 DELAY(1);
302 SIO_CLR(WB_SIO_MII_CLK);
303 DELAY(1);
304 }
305
306 return;
307 }
308
309 /*
310 * Clock a series of bits through the MII.
311 */
wb_mii_send(sc,bits,cnt)312 void wb_mii_send(sc, bits, cnt)
313 struct wb_softc *sc;
314 u_int32_t bits;
315 int cnt;
316 {
317 int i;
318
319 SIO_CLR(WB_SIO_MII_CLK);
320
321 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
322 if (bits & i) {
323 SIO_SET(WB_SIO_MII_DATAIN);
324 } else {
325 SIO_CLR(WB_SIO_MII_DATAIN);
326 }
327 DELAY(1);
328 SIO_CLR(WB_SIO_MII_CLK);
329 DELAY(1);
330 SIO_SET(WB_SIO_MII_CLK);
331 }
332 }
333
334 /*
335 * Read an PHY register through the MII.
336 */
wb_mii_readreg(sc,frame)337 int wb_mii_readreg(sc, frame)
338 struct wb_softc *sc;
339 struct wb_mii_frame *frame;
340
341 {
342 int i, ack, s;
343
344 s = splimp();
345
346 /*
347 * Set up frame for RX.
348 */
349 frame->mii_stdelim = WB_MII_STARTDELIM;
350 frame->mii_opcode = WB_MII_READOP;
351 frame->mii_turnaround = 0;
352 frame->mii_data = 0;
353
354 CSR_WRITE_4(sc, WB_SIO, 0);
355
356 /*
357 * Turn on data xmit.
358 */
359 SIO_SET(WB_SIO_MII_DIR);
360
361 wb_mii_sync(sc);
362
363 /*
364 * Send command/address info.
365 */
366 wb_mii_send(sc, frame->mii_stdelim, 2);
367 wb_mii_send(sc, frame->mii_opcode, 2);
368 wb_mii_send(sc, frame->mii_phyaddr, 5);
369 wb_mii_send(sc, frame->mii_regaddr, 5);
370
371 /* Idle bit */
372 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN));
373 DELAY(1);
374 SIO_SET(WB_SIO_MII_CLK);
375 DELAY(1);
376
377 /* Turn off xmit. */
378 SIO_CLR(WB_SIO_MII_DIR);
379 /* Check for ack */
380 SIO_CLR(WB_SIO_MII_CLK);
381 DELAY(1);
382 SIO_SET(WB_SIO_MII_CLK);
383 DELAY(1);
384 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT;
385 SIO_CLR(WB_SIO_MII_CLK);
386 DELAY(1);
387 SIO_SET(WB_SIO_MII_CLK);
388 DELAY(1);
389
390 /*
391 * Now try reading data bits. If the ack failed, we still
392 * need to clock through 16 cycles to keep the PHY(s) in sync.
393 */
394 if (ack) {
395 for(i = 0; i < 16; i++) {
396 SIO_CLR(WB_SIO_MII_CLK);
397 DELAY(1);
398 SIO_SET(WB_SIO_MII_CLK);
399 DELAY(1);
400 }
401 goto fail;
402 }
403
404 for (i = 0x8000; i; i >>= 1) {
405 SIO_CLR(WB_SIO_MII_CLK);
406 DELAY(1);
407 if (!ack) {
408 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT)
409 frame->mii_data |= i;
410 DELAY(1);
411 }
412 SIO_SET(WB_SIO_MII_CLK);
413 DELAY(1);
414 }
415
416 fail:
417
418 SIO_CLR(WB_SIO_MII_CLK);
419 DELAY(1);
420 SIO_SET(WB_SIO_MII_CLK);
421 DELAY(1);
422
423 splx(s);
424
425 if (ack)
426 return(1);
427 return(0);
428 }
429
430 /*
431 * Write to a PHY register through the MII.
432 */
wb_mii_writereg(sc,frame)433 int wb_mii_writereg(sc, frame)
434 struct wb_softc *sc;
435 struct wb_mii_frame *frame;
436
437 {
438 int s;
439
440 s = splimp();
441 /*
442 * Set up frame for TX.
443 */
444
445 frame->mii_stdelim = WB_MII_STARTDELIM;
446 frame->mii_opcode = WB_MII_WRITEOP;
447 frame->mii_turnaround = WB_MII_TURNAROUND;
448
449 /*
450 * Turn on data output.
451 */
452 SIO_SET(WB_SIO_MII_DIR);
453
454 wb_mii_sync(sc);
455
456 wb_mii_send(sc, frame->mii_stdelim, 2);
457 wb_mii_send(sc, frame->mii_opcode, 2);
458 wb_mii_send(sc, frame->mii_phyaddr, 5);
459 wb_mii_send(sc, frame->mii_regaddr, 5);
460 wb_mii_send(sc, frame->mii_turnaround, 2);
461 wb_mii_send(sc, frame->mii_data, 16);
462
463 /* Idle bit. */
464 SIO_SET(WB_SIO_MII_CLK);
465 DELAY(1);
466 SIO_CLR(WB_SIO_MII_CLK);
467 DELAY(1);
468
469 /*
470 * Turn off xmit.
471 */
472 SIO_CLR(WB_SIO_MII_DIR);
473
474 splx(s);
475
476 return(0);
477 }
478
479 int
wb_miibus_readreg(dev,phy,reg)480 wb_miibus_readreg(dev, phy, reg)
481 struct device *dev;
482 int phy, reg;
483 {
484 struct wb_softc *sc = (struct wb_softc *)dev;
485 struct wb_mii_frame frame;
486
487 bzero((char *)&frame, sizeof(frame));
488
489 frame.mii_phyaddr = phy;
490 frame.mii_regaddr = reg;
491 wb_mii_readreg(sc, &frame);
492
493 return(frame.mii_data);
494 }
495
496 void
wb_miibus_writereg(dev,phy,reg,data)497 wb_miibus_writereg(dev, phy, reg, data)
498 struct device *dev;
499 int phy, reg, data;
500 {
501 struct wb_softc *sc = (struct wb_softc *)dev;
502 struct wb_mii_frame frame;
503
504 bzero((char *)&frame, sizeof(frame));
505
506 frame.mii_phyaddr = phy;
507 frame.mii_regaddr = reg;
508 frame.mii_data = data;
509
510 wb_mii_writereg(sc, &frame);
511
512 return;
513 }
514
515 void
wb_miibus_statchg(dev)516 wb_miibus_statchg(dev)
517 struct device *dev;
518 {
519 struct wb_softc *sc = (struct wb_softc *)dev;
520
521 wb_setcfg(sc, sc->sc_mii.mii_media_active);
522 }
523
wb_calchash(addr)524 u_int8_t wb_calchash(addr)
525 caddr_t addr;
526 {
527 u_int32_t crc, carry;
528 int i, j;
529 u_int8_t c;
530
531 /* Compute CRC for the address value. */
532 crc = 0xFFFFFFFF; /* initial value */
533
534 for (i = 0; i < 6; i++) {
535 c = *(addr + i);
536 for (j = 0; j < 8; j++) {
537 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
538 crc <<= 1;
539 c >>= 1;
540 if (carry)
541 crc = (crc ^ 0x04c11db6) | carry;
542 }
543 }
544
545 /*
546 * return the filter bit position
547 * Note: I arrived at the following nonsense
548 * through experimentation. It's not the usual way to
549 * generate the bit position but it's the only thing
550 * I could come up with that works.
551 */
552 return(~(crc >> 26) & 0x0000003F);
553 }
554
555 /*
556 * Program the 64-bit multicast hash filter.
557 */
wb_setmulti(sc)558 void wb_setmulti(sc)
559 struct wb_softc *sc;
560 {
561 struct ifnet *ifp;
562 int h = 0;
563 u_int32_t hashes[2] = { 0, 0 };
564 struct arpcom *ac = &sc->arpcom;
565 struct ether_multi *enm;
566 struct ether_multistep step;
567 u_int32_t rxfilt;
568 int mcnt = 0;
569
570 ifp = &sc->arpcom.ac_if;
571
572 rxfilt = CSR_READ_4(sc, WB_NETCFG);
573
574 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
575 rxfilt |= WB_NETCFG_RX_MULTI;
576 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
577 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF);
578 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF);
579 return;
580 }
581
582 /* first, zot all the existing hash bits */
583 CSR_WRITE_4(sc, WB_MAR0, 0);
584 CSR_WRITE_4(sc, WB_MAR1, 0);
585
586 /* now program new ones */
587 ETHER_FIRST_MULTI(step, ac, enm);
588 while (enm != NULL) {
589 h = wb_calchash(enm->enm_addrlo);
590 if (h < 32)
591 hashes[0] |= (1 << h);
592 else
593 hashes[1] |= (1 << (h - 32));
594 mcnt++;
595 ETHER_NEXT_MULTI(step, enm);
596 }
597
598 if (mcnt)
599 rxfilt |= WB_NETCFG_RX_MULTI;
600 else
601 rxfilt &= ~WB_NETCFG_RX_MULTI;
602
603 CSR_WRITE_4(sc, WB_MAR0, hashes[0]);
604 CSR_WRITE_4(sc, WB_MAR1, hashes[1]);
605 CSR_WRITE_4(sc, WB_NETCFG, rxfilt);
606
607 return;
608 }
609
610 /*
611 * The Winbond manual states that in order to fiddle with the
612 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
613 * first have to put the transmit and/or receive logic in the idle state.
614 */
615 void
wb_setcfg(sc,media)616 wb_setcfg(sc, media)
617 struct wb_softc *sc;
618 u_int32_t media;
619 {
620 int i, restart = 0;
621
622 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) {
623 restart = 1;
624 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON));
625
626 for (i = 0; i < WB_TIMEOUT; i++) {
627 DELAY(10);
628 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) &&
629 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE))
630 break;
631 }
632
633 if (i == WB_TIMEOUT)
634 printf("%s: failed to force tx and "
635 "rx to idle state\n", sc->sc_dev.dv_xname);
636 }
637
638 if (IFM_SUBTYPE(media) == IFM_10_T)
639 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
640 else
641 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS);
642
643 if ((media & IFM_GMASK) == IFM_FDX)
644 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
645 else
646 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX);
647
648 if (restart)
649 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON);
650
651 return;
652 }
653
654 void
wb_reset(sc)655 wb_reset(sc)
656 struct wb_softc *sc;
657 {
658 register int i;
659 struct mii_data *mii = &sc->sc_mii;
660
661 CSR_WRITE_4(sc, WB_NETCFG, 0);
662 CSR_WRITE_4(sc, WB_BUSCTL, 0);
663 CSR_WRITE_4(sc, WB_TXADDR, 0);
664 CSR_WRITE_4(sc, WB_RXADDR, 0);
665
666 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
667 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET);
668
669 for (i = 0; i < WB_TIMEOUT; i++) {
670 DELAY(10);
671 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET))
672 break;
673 }
674 if (i == WB_TIMEOUT)
675 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
676
677 /* Wait a little while for the chip to get its brains in order. */
678 DELAY(1000);
679
680 if (mii->mii_instance) {
681 struct mii_softc *miisc;
682 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
683 miisc = LIST_NEXT(miisc, mii_list))
684 mii_phy_reset(miisc);
685 }
686 }
687
688 void
wb_fixmedia(sc)689 wb_fixmedia(sc)
690 struct wb_softc *sc;
691 {
692 struct mii_data *mii = &sc->sc_mii;
693 u_int32_t media;
694
695 if (LIST_FIRST(&mii->mii_phys) == NULL)
696 return;
697
698 mii_pollstat(mii);
699 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) {
700 media = mii->mii_media_active & ~IFM_10_T;
701 media |= IFM_100_TX;
702 } if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
703 media = mii->mii_media_active & ~IFM_100_TX;
704 media |= IFM_10_T;
705 } else
706 return;
707
708 ifmedia_set(&mii->mii_media, media);
709 }
710
711 const struct pci_matchid wb_devices[] = {
712 { PCI_VENDOR_WINBOND, PCI_PRODUCT_WINBOND_W89C840F },
713 { PCI_VENDOR_COMPEX, PCI_PRODUCT_COMPEX_RL100ATX },
714 };
715
716 /*
717 * Probe for a Winbond chip. Check the PCI vendor and device
718 * IDs against our list and return a device name if we find a match.
719 */
720 int
wb_probe(parent,match,aux)721 wb_probe(parent, match, aux)
722 struct device *parent;
723 void *match, *aux;
724 {
725 return (pci_matchbyid((struct pci_attach_args *)aux, wb_devices,
726 sizeof(wb_devices)/sizeof(wb_devices[0])));
727 }
728
729 /*
730 * Attach the interface. Allocate softc structures, do ifmedia
731 * setup and ethernet/BPF attach.
732 */
733 void
wb_attach(parent,self,aux)734 wb_attach(parent, self, aux)
735 struct device *parent, *self;
736 void *aux;
737 {
738 struct wb_softc *sc = (struct wb_softc *)self;
739 struct pci_attach_args *pa = aux;
740 pci_chipset_tag_t pc = pa->pa_pc;
741 pci_intr_handle_t ih;
742 const char *intrstr = NULL;
743 struct ifnet *ifp = &sc->arpcom.ac_if;
744 bus_addr_t iobase;
745 bus_size_t iosize;
746 int s, rseg;
747 u_int32_t command;
748 bus_dma_segment_t seg;
749 bus_dmamap_t dmamap;
750 caddr_t kva;
751
752 s = splimp();
753
754 /*
755 * Handle power management nonsense.
756 */
757
758 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_CAPID) & 0x000000FF;
759 if (command == 0x01) {
760
761 command = pci_conf_read(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL);
762 if (command & WB_PSTATE_MASK) {
763 u_int32_t io, mem, irq;
764
765 /* Save important PCI config data. */
766 io = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOIO);
767 mem = pci_conf_read(pc, pa->pa_tag, WB_PCI_LOMEM);
768 irq = pci_conf_read(pc, pa->pa_tag, WB_PCI_INTLINE);
769
770 /* Reset the power state. */
771 printf("%s: chip is in D%d power mode "
772 "-- setting to D0\n", sc->sc_dev.dv_xname,
773 command & WB_PSTATE_MASK);
774 command &= 0xFFFFFFFC;
775 pci_conf_write(pc, pa->pa_tag, WB_PCI_PWRMGMTCTRL,
776 command);
777
778 /* Restore PCI config data. */
779 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOIO, io);
780 pci_conf_write(pc, pa->pa_tag, WB_PCI_LOMEM, mem);
781 pci_conf_write(pc, pa->pa_tag, WB_PCI_INTLINE, irq);
782 }
783 }
784
785 /*
786 * Map control/status registers.
787 */
788 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
789 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
790 PCI_COMMAND_MASTER_ENABLE;
791 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
792 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
793
794 #ifdef WB_USEIOSPACE
795 if (!(command & PCI_COMMAND_IO_ENABLE)) {
796 printf(": failed to enable I/O ports!\n");
797 goto fail;
798 }
799 if (pci_io_find(pc, pa->pa_tag, WB_PCI_LOIO, &iobase, &iosize)) {
800 printf(": can't find i/o space\n");
801 goto fail;
802 }
803 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->wb_bhandle)) {
804 printf(": can't map i/o space\n");
805 goto fail;
806 }
807 sc->wb_btag = pa->pa_iot;
808 #else
809 if (!(command & PCI_COMMAND_MEM_ENABLE)) {
810 printf(": failed to enable memory mapping!\n");
811 goto fail;
812 }
813 if (pci_mem_find(pc, pa->pa_tag, WB_PCI_LOMEM, &iobase, &iosize, NULL)){
814 printf(": can't find mem space\n");
815 goto fail;
816 }
817 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->wb_bhandle)) {
818 printf(": can't map mem space\n");
819 goto fail;
820 }
821 sc->wb_btag = pa->pa_memt;
822 #endif
823
824 /* Allocate interrupt */
825 if (pci_intr_map(pa, &ih)) {
826 printf(": couldn't map interrupt\n");
827 goto fail;
828 }
829 intrstr = pci_intr_string(pc, ih);
830 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, wb_intr, sc,
831 self->dv_xname);
832 if (sc->sc_ih == NULL) {
833 printf(": couldn't establish interrupt");
834 if (intrstr != NULL)
835 printf(" at %s", intrstr);
836 printf("\n");
837 goto fail;
838 }
839 printf(": %s", intrstr);
840
841 sc->wb_cachesize = pci_conf_read(pc, pa->pa_tag, WB_PCI_CACHELEN)&0xff;
842
843 /* Reset the adapter. */
844 wb_reset(sc);
845
846 /*
847 * Get station address from the EEPROM.
848 */
849 wb_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 0, 3, 0);
850 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
851
852 if (bus_dmamem_alloc(pa->pa_dmat, sizeof(struct wb_list_data),
853 PAGE_SIZE, 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) {
854 printf("%s: can't alloc list data\n", sc->sc_dev.dv_xname);
855 goto fail;
856 }
857 if (bus_dmamem_map(pa->pa_dmat, &seg, rseg,
858 sizeof(struct wb_list_data), &kva, BUS_DMA_NOWAIT)) {
859 printf("%s: can't map list data, size %d\n",
860 sc->sc_dev.dv_xname, (int)sizeof(struct wb_list_data));
861 bus_dmamem_free(pa->pa_dmat, &seg, rseg);
862 goto fail;
863 }
864 if (bus_dmamap_create(pa->pa_dmat, sizeof(struct wb_list_data), 1,
865 sizeof(struct wb_list_data), 0, BUS_DMA_NOWAIT, &dmamap)) {
866 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname);
867 bus_dmamem_unmap(pa->pa_dmat, kva,
868 sizeof(struct wb_list_data));
869 bus_dmamem_free(pa->pa_dmat, &seg, rseg);
870 goto fail;
871 }
872 if (bus_dmamap_load(pa->pa_dmat, dmamap, kva,
873 sizeof(struct wb_list_data), NULL, BUS_DMA_NOWAIT)) {
874 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname);
875 bus_dmamap_destroy(pa->pa_dmat, dmamap);
876 bus_dmamem_unmap(pa->pa_dmat, kva,
877 sizeof(struct wb_list_data));
878 bus_dmamem_free(pa->pa_dmat, &seg, rseg);
879 goto fail;
880 }
881 sc->wb_ldata = (struct wb_list_data *)kva;
882 bzero(sc->wb_ldata, sizeof(struct wb_list_data));
883
884 ifp->if_softc = sc;
885 ifp->if_mtu = ETHERMTU;
886 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
887 ifp->if_ioctl = wb_ioctl;
888 ifp->if_output = ether_output;
889 ifp->if_start = wb_start;
890 ifp->if_watchdog = wb_watchdog;
891 ifp->if_baudrate = 10000000;
892 IFQ_SET_MAXLEN(&ifp->if_snd, WB_TX_LIST_CNT - 1);
893 IFQ_SET_READY(&ifp->if_snd);
894
895 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
896
897 /*
898 * Do ifmedia setup.
899 */
900 wb_stop(sc);
901
902 ifmedia_init(&sc->sc_mii.mii_media, 0, wb_ifmedia_upd, wb_ifmedia_sts);
903 sc->sc_mii.mii_ifp = ifp;
904 sc->sc_mii.mii_readreg = wb_miibus_readreg;
905 sc->sc_mii.mii_writereg = wb_miibus_writereg;
906 sc->sc_mii.mii_statchg = wb_miibus_statchg;
907 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
908 0);
909 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
910 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE,0,NULL);
911 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
912 } else
913 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
914
915 /*
916 * Call MI attach routines.
917 */
918 if_attach(ifp);
919 ether_ifattach(ifp);
920
921 shutdownhook_establish(wb_shutdown, sc);
922
923 fail:
924 splx(s);
925 return;
926 }
927
928 /*
929 * Initialize the transmit descriptors.
930 */
wb_list_tx_init(sc)931 int wb_list_tx_init(sc)
932 struct wb_softc *sc;
933 {
934 struct wb_chain_data *cd;
935 struct wb_list_data *ld;
936 int i;
937
938 cd = &sc->wb_cdata;
939 ld = sc->wb_ldata;
940
941 for (i = 0; i < WB_TX_LIST_CNT; i++) {
942 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i];
943 if (i == (WB_TX_LIST_CNT - 1)) {
944 cd->wb_tx_chain[i].wb_nextdesc =
945 &cd->wb_tx_chain[0];
946 } else {
947 cd->wb_tx_chain[i].wb_nextdesc =
948 &cd->wb_tx_chain[i + 1];
949 }
950 }
951
952 cd->wb_tx_free = &cd->wb_tx_chain[0];
953 cd->wb_tx_tail = cd->wb_tx_head = NULL;
954
955 return(0);
956 }
957
958
959 /*
960 * Initialize the RX descriptors and allocate mbufs for them. Note that
961 * we arrange the descriptors in a closed ring, so that the last descriptor
962 * points back to the first.
963 */
wb_list_rx_init(sc)964 int wb_list_rx_init(sc)
965 struct wb_softc *sc;
966 {
967 struct wb_chain_data *cd;
968 struct wb_list_data *ld;
969 int i;
970
971 cd = &sc->wb_cdata;
972 ld = sc->wb_ldata;
973
974 for (i = 0; i < WB_RX_LIST_CNT; i++) {
975 cd->wb_rx_chain[i].wb_ptr =
976 (struct wb_desc *)&ld->wb_rx_list[i];
977 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i];
978 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS)
979 return(ENOBUFS);
980 if (i == (WB_RX_LIST_CNT - 1)) {
981 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0];
982 ld->wb_rx_list[i].wb_next =
983 vtophys(&ld->wb_rx_list[0]);
984 } else {
985 cd->wb_rx_chain[i].wb_nextdesc =
986 &cd->wb_rx_chain[i + 1];
987 ld->wb_rx_list[i].wb_next =
988 vtophys(&ld->wb_rx_list[i + 1]);
989 }
990 }
991
992 cd->wb_rx_head = &cd->wb_rx_chain[0];
993
994 return(0);
995 }
996
997 void
wb_bfree(buf,size,arg)998 wb_bfree(buf, size, arg)
999 caddr_t buf;
1000 u_int size;
1001 void *arg;
1002 {
1003 }
1004
1005 /*
1006 * Initialize an RX descriptor and attach an MBUF cluster.
1007 */
1008 int
wb_newbuf(sc,c,m)1009 wb_newbuf(sc, c, m)
1010 struct wb_softc *sc;
1011 struct wb_chain_onefrag *c;
1012 struct mbuf *m;
1013 {
1014 struct mbuf *m_new = NULL;
1015
1016 if (m == NULL) {
1017 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1018 if (m_new == NULL)
1019 return(ENOBUFS);
1020 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf;
1021 m_new->m_flags |= M_EXT;
1022 m_new->m_ext.ext_size = m_new->m_pkthdr.len =
1023 m_new->m_len = WB_BUFBYTES;
1024 m_new->m_ext.ext_free = wb_bfree;
1025 m_new->m_ext.ext_arg = NULL;
1026 MCLINITREFERENCE(m_new);
1027 } else {
1028 m_new = m;
1029 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES;
1030 m_new->m_data = m_new->m_ext.ext_buf;
1031 }
1032
1033 m_adj(m_new, sizeof(u_int64_t));
1034
1035 c->wb_mbuf = m_new;
1036 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t));
1037 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536;
1038 c->wb_ptr->wb_status = WB_RXSTAT;
1039
1040 return(0);
1041 }
1042
1043 /*
1044 * A frame has been uploaded: pass the resulting mbuf chain up to
1045 * the higher level protocols.
1046 */
wb_rxeof(sc)1047 void wb_rxeof(sc)
1048 struct wb_softc *sc;
1049 {
1050 struct mbuf *m = NULL;
1051 struct ifnet *ifp;
1052 struct wb_chain_onefrag *cur_rx;
1053 int total_len = 0;
1054 u_int32_t rxstat;
1055
1056 ifp = &sc->arpcom.ac_if;
1057
1058 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) &
1059 WB_RXSTAT_OWN)) {
1060 struct mbuf *m0 = NULL;
1061
1062 cur_rx = sc->wb_cdata.wb_rx_head;
1063 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc;
1064
1065 m = cur_rx->wb_mbuf;
1066
1067 if ((rxstat & WB_RXSTAT_MIIERR) ||
1068 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) ||
1069 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) ||
1070 !(rxstat & WB_RXSTAT_LASTFRAG) ||
1071 !(rxstat & WB_RXSTAT_RXCMP)) {
1072 ifp->if_ierrors++;
1073 wb_newbuf(sc, cur_rx, m);
1074 printf("%s: receiver babbling: possible chip "
1075 "bug, forcing reset\n", sc->sc_dev.dv_xname);
1076 wb_fixmedia(sc);
1077 wb_reset(sc);
1078 wb_init(sc);
1079 return;
1080 }
1081
1082 if (rxstat & WB_RXSTAT_RXERR) {
1083 ifp->if_ierrors++;
1084 wb_newbuf(sc, cur_rx, m);
1085 break;
1086 }
1087
1088 /* No errors; receive the packet. */
1089 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status);
1090
1091 /*
1092 * XXX The Winbond chip includes the CRC with every
1093 * received frame, and there's no way to turn this
1094 * behavior off (at least, I can't find anything in
1095 * the manual that explains how to do it) so we have
1096 * to trim off the CRC manually.
1097 */
1098 total_len -= ETHER_CRC_LEN;
1099
1100 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN,
1101 total_len + ETHER_ALIGN, 0, ifp, NULL);
1102 wb_newbuf(sc, cur_rx, m);
1103 if (m0 == NULL) {
1104 ifp->if_ierrors++;
1105 break;
1106 }
1107 m_adj(m0, ETHER_ALIGN);
1108 m = m0;
1109
1110 ifp->if_ipackets++;
1111
1112 #if NBPFILTER > 0
1113 /*
1114 * Handle BPF listeners. Let the BPF user see the packet.
1115 */
1116 if (ifp->if_bpf)
1117 bpf_mtap(ifp->if_bpf, m);
1118 #endif
1119 /* pass it on. */
1120 ether_input_mbuf(ifp, m);
1121 }
1122
1123 return;
1124 }
1125
wb_rxeoc(sc)1126 void wb_rxeoc(sc)
1127 struct wb_softc *sc;
1128 {
1129 wb_rxeof(sc);
1130
1131 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1132 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1133 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1134 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND)
1135 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1136
1137 return;
1138 }
1139
1140 /*
1141 * A frame was downloaded to the chip. It's safe for us to clean up
1142 * the list buffers.
1143 */
wb_txeof(sc)1144 void wb_txeof(sc)
1145 struct wb_softc *sc;
1146 {
1147 struct wb_chain *cur_tx;
1148 struct ifnet *ifp;
1149
1150 ifp = &sc->arpcom.ac_if;
1151
1152 /* Clear the timeout timer. */
1153 ifp->if_timer = 0;
1154
1155 if (sc->wb_cdata.wb_tx_head == NULL)
1156 return;
1157
1158 /*
1159 * Go through our tx list and free mbufs for those
1160 * frames that have been transmitted.
1161 */
1162 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) {
1163 u_int32_t txstat;
1164
1165 cur_tx = sc->wb_cdata.wb_tx_head;
1166 txstat = WB_TXSTATUS(cur_tx);
1167
1168 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT)
1169 break;
1170
1171 if (txstat & WB_TXSTAT_TXERR) {
1172 ifp->if_oerrors++;
1173 if (txstat & WB_TXSTAT_ABORT)
1174 ifp->if_collisions++;
1175 if (txstat & WB_TXSTAT_LATECOLL)
1176 ifp->if_collisions++;
1177 }
1178
1179 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3;
1180
1181 ifp->if_opackets++;
1182 m_freem(cur_tx->wb_mbuf);
1183 cur_tx->wb_mbuf = NULL;
1184
1185 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) {
1186 sc->wb_cdata.wb_tx_head = NULL;
1187 sc->wb_cdata.wb_tx_tail = NULL;
1188 break;
1189 }
1190
1191 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc;
1192 }
1193
1194 return;
1195 }
1196
1197 /*
1198 * TX 'end of channel' interrupt handler.
1199 */
wb_txeoc(sc)1200 void wb_txeoc(sc)
1201 struct wb_softc *sc;
1202 {
1203 struct ifnet *ifp;
1204
1205 ifp = &sc->arpcom.ac_if;
1206
1207 ifp->if_timer = 0;
1208
1209 if (sc->wb_cdata.wb_tx_head == NULL) {
1210 ifp->if_flags &= ~IFF_OACTIVE;
1211 sc->wb_cdata.wb_tx_tail = NULL;
1212 } else {
1213 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) {
1214 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN;
1215 ifp->if_timer = 5;
1216 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1217 }
1218 }
1219
1220 return;
1221 }
1222
wb_intr(arg)1223 int wb_intr(arg)
1224 void *arg;
1225 {
1226 struct wb_softc *sc;
1227 struct ifnet *ifp;
1228 u_int32_t status;
1229 int r = 0;
1230
1231 sc = arg;
1232 ifp = &sc->arpcom.ac_if;
1233
1234 if (!(ifp->if_flags & IFF_UP))
1235 return (r);
1236
1237 /* Disable interrupts. */
1238 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1239
1240 for (;;) {
1241
1242 status = CSR_READ_4(sc, WB_ISR);
1243 if (status)
1244 CSR_WRITE_4(sc, WB_ISR, status);
1245
1246 if ((status & WB_INTRS) == 0)
1247 break;
1248
1249 r = 1;
1250
1251 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) {
1252 ifp->if_ierrors++;
1253 wb_reset(sc);
1254 if (status & WB_ISR_RX_ERR)
1255 wb_fixmedia(sc);
1256 wb_init(sc);
1257 continue;
1258 }
1259
1260 if (status & WB_ISR_RX_OK)
1261 wb_rxeof(sc);
1262
1263 if (status & WB_ISR_RX_IDLE)
1264 wb_rxeoc(sc);
1265
1266 if (status & WB_ISR_TX_OK)
1267 wb_txeof(sc);
1268
1269 if (status & WB_ISR_TX_NOBUF)
1270 wb_txeoc(sc);
1271
1272 if (status & WB_ISR_TX_IDLE) {
1273 wb_txeof(sc);
1274 if (sc->wb_cdata.wb_tx_head != NULL) {
1275 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1276 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1277 }
1278 }
1279
1280 if (status & WB_ISR_TX_UNDERRUN) {
1281 ifp->if_oerrors++;
1282 wb_txeof(sc);
1283 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1284 /* Jack up TX threshold */
1285 sc->wb_txthresh += WB_TXTHRESH_CHUNK;
1286 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1287 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1288 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1289 }
1290
1291 if (status & WB_ISR_BUS_ERR) {
1292 wb_reset(sc);
1293 wb_init(sc);
1294 }
1295
1296 }
1297
1298 /* Re-enable interrupts. */
1299 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1300
1301 if (!IFQ_IS_EMPTY(&ifp->if_snd)) {
1302 wb_start(ifp);
1303 }
1304
1305 return (r);
1306 }
1307
1308 void
wb_tick(xsc)1309 wb_tick(xsc)
1310 void *xsc;
1311 {
1312 struct wb_softc *sc = xsc;
1313 int s;
1314
1315 s = splimp();
1316 mii_tick(&sc->sc_mii);
1317 splx(s);
1318 timeout_add(&sc->wb_tick_tmo, hz);
1319 }
1320
1321 /*
1322 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1323 * pointers to the fragment pointers.
1324 */
wb_encap(sc,c,m_head)1325 int wb_encap(sc, c, m_head)
1326 struct wb_softc *sc;
1327 struct wb_chain *c;
1328 struct mbuf *m_head;
1329 {
1330 int frag = 0;
1331 struct wb_desc *f = NULL;
1332 int total_len;
1333 struct mbuf *m;
1334
1335 /*
1336 * Start packing the mbufs in this chain into
1337 * the fragment pointers. Stop when we run out
1338 * of fragments or hit the end of the mbuf chain.
1339 */
1340 m = m_head;
1341 total_len = 0;
1342
1343 for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
1344 if (m->m_len != 0) {
1345 if (frag == WB_MAXFRAGS)
1346 break;
1347 total_len += m->m_len;
1348 f = &c->wb_ptr->wb_frag[frag];
1349 f->wb_ctl = WB_TXCTL_TLINK | m->m_len;
1350 if (frag == 0) {
1351 f->wb_ctl |= WB_TXCTL_FIRSTFRAG;
1352 f->wb_status = 0;
1353 } else
1354 f->wb_status = WB_TXSTAT_OWN;
1355 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]);
1356 f->wb_data = vtophys(mtod(m, vaddr_t));
1357 frag++;
1358 }
1359 }
1360
1361 /*
1362 * Handle special case: we used up all 16 fragments,
1363 * but we have more mbufs left in the chain. Copy the
1364 * data into an mbuf cluster. Note that we don't
1365 * bother clearing the values in the other fragment
1366 * pointers/counters; it wouldn't gain us anything,
1367 * and would waste cycles.
1368 */
1369 if (m != NULL) {
1370 struct mbuf *m_new = NULL;
1371
1372 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1373 if (m_new == NULL)
1374 return(1);
1375 if (m_head->m_pkthdr.len > MHLEN) {
1376 MCLGET(m_new, M_DONTWAIT);
1377 if (!(m_new->m_flags & M_EXT)) {
1378 m_freem(m_new);
1379 return(1);
1380 }
1381 }
1382 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1383 mtod(m_new, caddr_t));
1384 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1385 m_freem(m_head);
1386 m_head = m_new;
1387 f = &c->wb_ptr->wb_frag[0];
1388 f->wb_status = 0;
1389 f->wb_data = vtophys(mtod(m_new, caddr_t));
1390 f->wb_ctl = total_len = m_new->m_len;
1391 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG;
1392 frag = 1;
1393 }
1394
1395 if (total_len < WB_MIN_FRAMELEN) {
1396 f = &c->wb_ptr->wb_frag[frag];
1397 f->wb_ctl = WB_MIN_FRAMELEN - total_len;
1398 f->wb_data = vtophys(&sc->wb_cdata.wb_pad);
1399 f->wb_ctl |= WB_TXCTL_TLINK;
1400 f->wb_status = WB_TXSTAT_OWN;
1401 frag++;
1402 }
1403
1404 c->wb_mbuf = m_head;
1405 c->wb_lastdesc = frag - 1;
1406 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG;
1407 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]);
1408
1409 return(0);
1410 }
1411
1412 /*
1413 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1414 * to the mbuf data regions directly in the transmit lists. We also save a
1415 * copy of the pointers since the transmit list fragment pointers are
1416 * physical addresses.
1417 */
1418
wb_start(ifp)1419 void wb_start(ifp)
1420 struct ifnet *ifp;
1421 {
1422 struct wb_softc *sc;
1423 struct mbuf *m_head = NULL;
1424 struct wb_chain *cur_tx = NULL, *start_tx;
1425
1426 sc = ifp->if_softc;
1427
1428 /*
1429 * Check for an available queue slot. If there are none,
1430 * punt.
1431 */
1432 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) {
1433 ifp->if_flags |= IFF_OACTIVE;
1434 return;
1435 }
1436
1437 start_tx = sc->wb_cdata.wb_tx_free;
1438
1439 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) {
1440 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1441 if (m_head == NULL)
1442 break;
1443
1444 /* Pick a descriptor off the free list. */
1445 cur_tx = sc->wb_cdata.wb_tx_free;
1446 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc;
1447
1448 /* Pack the data into the descriptor. */
1449 wb_encap(sc, cur_tx, m_head);
1450
1451 if (cur_tx != start_tx)
1452 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN;
1453
1454 #if NBPFILTER > 0
1455 /*
1456 * If there's a BPF listener, bounce a copy of this frame
1457 * to him.
1458 */
1459 if (ifp->if_bpf)
1460 bpf_mtap(ifp->if_bpf, cur_tx->wb_mbuf);
1461 #endif
1462 }
1463
1464 /*
1465 * If there are no packets queued, bail.
1466 */
1467 if (cur_tx == NULL)
1468 return;
1469
1470 /*
1471 * Place the request for the upload interrupt
1472 * in the last descriptor in the chain. This way, if
1473 * we're chaining several packets at once, we'll only
1474 * get an interupt once for the whole chain rather than
1475 * once for each packet.
1476 */
1477 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT;
1478 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT;
1479 sc->wb_cdata.wb_tx_tail = cur_tx;
1480
1481 if (sc->wb_cdata.wb_tx_head == NULL) {
1482 sc->wb_cdata.wb_tx_head = start_tx;
1483 WB_TXOWN(start_tx) = WB_TXSTAT_OWN;
1484 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF);
1485 } else {
1486 /*
1487 * We need to distinguish between the case where
1488 * the own bit is clear because the chip cleared it
1489 * and where the own bit is clear because we haven't
1490 * set it yet. The magic value WB_UNSET is just some
1491 * ramdomly chosen number which doesn't have the own
1492 * bit set. When we actually transmit the frame, the
1493 * status word will have _only_ the own bit set, so
1494 * the txeoc handler will be able to tell if it needs
1495 * to initiate another transmission to flush out pending
1496 * frames.
1497 */
1498 WB_TXOWN(start_tx) = WB_UNSENT;
1499 }
1500
1501 /*
1502 * Set a timeout in case the chip goes out to lunch.
1503 */
1504 ifp->if_timer = 5;
1505
1506 return;
1507 }
1508
wb_init(xsc)1509 void wb_init(xsc)
1510 void *xsc;
1511 {
1512 struct wb_softc *sc = xsc;
1513 struct ifnet *ifp = &sc->arpcom.ac_if;
1514 int s, i;
1515
1516 s = splimp();
1517
1518 /*
1519 * Cancel pending I/O and free all RX/TX buffers.
1520 */
1521 wb_stop(sc);
1522 wb_reset(sc);
1523
1524 sc->wb_txthresh = WB_TXTHRESH_INIT;
1525
1526 /*
1527 * Set cache alignment and burst length.
1528 */
1529 #ifdef foo
1530 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG);
1531 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH);
1532 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh));
1533 #endif
1534
1535 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION);
1536 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG);
1537 switch(sc->wb_cachesize) {
1538 case 32:
1539 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG);
1540 break;
1541 case 16:
1542 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG);
1543 break;
1544 case 8:
1545 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG);
1546 break;
1547 case 0:
1548 default:
1549 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE);
1550 break;
1551 }
1552
1553 /* This doesn't tend to work too well at 100Mbps. */
1554 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON);
1555
1556 /* Init our MAC address */
1557 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1558 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]);
1559 }
1560
1561 /* Init circular RX list. */
1562 if (wb_list_rx_init(sc) == ENOBUFS) {
1563 printf("%s: initialization failed: no "
1564 "memory for rx buffers\n", sc->sc_dev.dv_xname);
1565 wb_stop(sc);
1566 splx(s);
1567 return;
1568 }
1569
1570 /* Init TX descriptors. */
1571 wb_list_tx_init(sc);
1572
1573 /* If we want promiscuous mode, set the allframes bit. */
1574 if (ifp->if_flags & IFF_PROMISC) {
1575 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1576 } else {
1577 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS);
1578 }
1579
1580 /*
1581 * Set capture broadcast bit to capture broadcast frames.
1582 */
1583 if (ifp->if_flags & IFF_BROADCAST) {
1584 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1585 } else {
1586 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD);
1587 }
1588
1589 /*
1590 * Program the multicast filter, if necessary.
1591 */
1592 wb_setmulti(sc);
1593
1594 /*
1595 * Load the address of the RX list.
1596 */
1597 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1598 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0]));
1599
1600 /*
1601 * Enable interrupts.
1602 */
1603 CSR_WRITE_4(sc, WB_IMR, WB_INTRS);
1604 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF);
1605
1606 /* Enable receiver and transmitter. */
1607 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON);
1608 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF);
1609
1610 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1611 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0]));
1612 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON);
1613
1614 ifp->if_flags |= IFF_RUNNING;
1615 ifp->if_flags &= ~IFF_OACTIVE;
1616
1617 splx(s);
1618
1619 timeout_set(&sc->wb_tick_tmo, wb_tick, sc);
1620 timeout_add(&sc->wb_tick_tmo, hz);
1621
1622 return;
1623 }
1624
1625 /*
1626 * Set media options.
1627 */
1628 int
wb_ifmedia_upd(ifp)1629 wb_ifmedia_upd(ifp)
1630 struct ifnet *ifp;
1631 {
1632 struct wb_softc *sc = ifp->if_softc;
1633
1634 if (ifp->if_flags & IFF_UP)
1635 wb_init(sc);
1636
1637 return(0);
1638 }
1639
1640 /*
1641 * Report current media status.
1642 */
1643 void
wb_ifmedia_sts(ifp,ifmr)1644 wb_ifmedia_sts(ifp, ifmr)
1645 struct ifnet *ifp;
1646 struct ifmediareq *ifmr;
1647 {
1648 struct wb_softc *sc = ifp->if_softc;
1649 struct mii_data *mii = &sc->sc_mii;
1650
1651 mii_pollstat(mii);
1652 ifmr->ifm_active = mii->mii_media_active;
1653 ifmr->ifm_status = mii->mii_media_status;
1654 }
1655
wb_ioctl(ifp,command,data)1656 int wb_ioctl(ifp, command, data)
1657 struct ifnet *ifp;
1658 u_long command;
1659 caddr_t data;
1660 {
1661 struct wb_softc *sc = ifp->if_softc;
1662 struct ifreq *ifr = (struct ifreq *) data;
1663 struct ifaddr *ifa = (struct ifaddr *)data;
1664 int s, error = 0;
1665
1666 s = splimp();
1667
1668 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
1669 splx(s);
1670 return (error);
1671 }
1672
1673 switch(command) {
1674 case SIOCSIFADDR:
1675 ifp->if_flags |= IFF_UP;
1676 switch (ifa->ifa_addr->sa_family) {
1677 #ifdef INET
1678 case AF_INET:
1679 wb_init(sc);
1680 arp_ifinit(&sc->arpcom, ifa);
1681 break;
1682 #endif /* INET */
1683 default:
1684 wb_init(sc);
1685 }
1686 break;
1687 case SIOCSIFFLAGS:
1688 if (ifp->if_flags & IFF_UP) {
1689 wb_init(sc);
1690 } else {
1691 if (ifp->if_flags & IFF_RUNNING)
1692 wb_stop(sc);
1693 }
1694 error = 0;
1695 break;
1696 case SIOCADDMULTI:
1697 case SIOCDELMULTI:
1698 error = (command == SIOCADDMULTI) ?
1699 ether_addmulti(ifr, &sc->arpcom) :
1700 ether_delmulti(ifr, &sc->arpcom);
1701
1702 if (error == ENETRESET) {
1703 /*
1704 * Multicast list has changed; set the hardware
1705 * filter accordingly.
1706 */
1707 wb_setmulti(sc);
1708 error = 0;
1709 }
1710 break;
1711 case SIOCGIFMEDIA:
1712 case SIOCSIFMEDIA:
1713 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
1714 break;
1715 default:
1716 error = EINVAL;
1717 break;
1718 }
1719
1720 splx(s);
1721
1722 return(error);
1723 }
1724
wb_watchdog(ifp)1725 void wb_watchdog(ifp)
1726 struct ifnet *ifp;
1727 {
1728 struct wb_softc *sc;
1729
1730 sc = ifp->if_softc;
1731
1732 ifp->if_oerrors++;
1733 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
1734
1735 #ifdef foo
1736 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1737 printf("%s: no carrier - transceiver cable problem?\n",
1738 sc->sc_dev.dv_xname);
1739 #endif
1740 wb_stop(sc);
1741 wb_reset(sc);
1742 wb_init(sc);
1743
1744 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1745 wb_start(ifp);
1746
1747 return;
1748 }
1749
1750 /*
1751 * Stop the adapter and free any mbufs allocated to the
1752 * RX and TX lists.
1753 */
wb_stop(sc)1754 void wb_stop(sc)
1755 struct wb_softc *sc;
1756 {
1757 register int i;
1758 struct ifnet *ifp;
1759
1760 ifp = &sc->arpcom.ac_if;
1761 ifp->if_timer = 0;
1762
1763 timeout_del(&sc->wb_tick_tmo);
1764
1765 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON));
1766 CSR_WRITE_4(sc, WB_IMR, 0x00000000);
1767 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000);
1768 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000);
1769
1770 /*
1771 * Free data in the RX lists.
1772 */
1773 for (i = 0; i < WB_RX_LIST_CNT; i++) {
1774 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) {
1775 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf);
1776 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL;
1777 }
1778 }
1779 bzero((char *)&sc->wb_ldata->wb_rx_list,
1780 sizeof(sc->wb_ldata->wb_rx_list));
1781
1782 /*
1783 * Free the TX list buffers.
1784 */
1785 for (i = 0; i < WB_TX_LIST_CNT; i++) {
1786 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) {
1787 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf);
1788 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL;
1789 }
1790 }
1791
1792 bzero((char *)&sc->wb_ldata->wb_tx_list,
1793 sizeof(sc->wb_ldata->wb_tx_list));
1794
1795 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1796
1797 return;
1798 }
1799
1800 /*
1801 * Stop all chip I/O so that the kernel's probe routines don't
1802 * get confused by errant DMAs when rebooting.
1803 */
wb_shutdown(arg)1804 void wb_shutdown(arg)
1805 void *arg;
1806 {
1807 struct wb_softc *sc = (struct wb_softc *)arg;
1808
1809 wb_stop(sc);
1810
1811 return;
1812 }
1813
1814 struct cfattach wb_ca = {
1815 sizeof(struct wb_softc), wb_probe, wb_attach
1816 };
1817
1818 struct cfdriver wb_cd = {
1819 0, "wb", DV_IFNET
1820 };
1821