1 /* $OpenBSD: if_vr.c,v 1.46 2005/07/06 02:22:28 brad Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: src/sys/pci/if_vr.c,v 1.73 2003/08/22 07:13:22 imp Exp $
35 */
36
37 /*
38 * VIA Rhine fast ethernet PCI NIC driver
39 *
40 * Supports various network adapters based on the VIA Rhine
41 * and Rhine II PCI controllers, including the D-Link DFE530TX.
42 * Datasheets are available at http://www.via.com.tw.
43 *
44 * Written by Bill Paul <wpaul@ctr.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
47 */
48
49 /*
50 * The VIA Rhine controllers are similar in some respects to the
51 * the DEC tulip chips, except less complicated. The controller
52 * uses an MII bus and an external physical layer interface. The
53 * receiver has a one entry perfect filter and a 64-bit hash table
54 * multicast filter. Transmit and receive descriptors are similar
55 * to the tulip.
56 *
57 * The Rhine has a serious flaw in its transmit DMA mechanism:
58 * transmit buffers must be longword aligned. Unfortunately,
59 * FreeBSD doesn't guarantee that mbufs will be filled in starting
60 * at longword boundaries, so we have to do a buffer copy before
61 * transmission.
62 */
63
64 #include "bpfilter.h"
65
66 #include <sys/param.h>
67 #include <sys/systm.h>
68 #include <sys/sockio.h>
69 #include <sys/mbuf.h>
70 #include <sys/malloc.h>
71 #include <sys/kernel.h>
72 #include <sys/socket.h>
73
74 #include <net/if.h>
75 #include <sys/device.h>
76 #ifdef INET
77 #include <netinet/in.h>
78 #include <netinet/in_systm.h>
79 #include <netinet/in_var.h>
80 #include <netinet/ip.h>
81 #include <netinet/if_ether.h>
82 #endif /* INET */
83 #include <net/if_dl.h>
84 #include <net/if_media.h>
85
86 #if NBPFILTER > 0
87 #include <net/bpf.h>
88 #endif
89
90 #include <machine/bus.h>
91
92 #include <dev/mii/mii.h>
93 #include <dev/mii/miivar.h>
94
95 #include <dev/pci/pcireg.h>
96 #include <dev/pci/pcivar.h>
97 #include <dev/pci/pcidevs.h>
98
99 #define VR_USEIOSPACE
100 #undef VR_USESWSHIFT
101
102 #include <dev/pci/if_vrreg.h>
103
104 int vr_probe(struct device *, void *, void *);
105 void vr_attach(struct device *, struct device *, void *);
106
107 struct cfattach vr_ca = {
108 sizeof(struct vr_softc), vr_probe, vr_attach
109 };
110 struct cfdriver vr_cd = {
111 0, "vr", DV_IFNET
112 };
113
114 int vr_encap(struct vr_softc *, struct vr_chain *, struct mbuf *);
115 void vr_rxeof(struct vr_softc *);
116 void vr_rxeoc(struct vr_softc *);
117 void vr_txeof(struct vr_softc *);
118 void vr_tick(void *);
119 int vr_intr(void *);
120 void vr_start(struct ifnet *);
121 int vr_ioctl(struct ifnet *, u_long, caddr_t);
122 void vr_init(void *);
123 void vr_stop(struct vr_softc *);
124 void vr_watchdog(struct ifnet *);
125 void vr_shutdown(void *);
126 int vr_ifmedia_upd(struct ifnet *);
127 void vr_ifmedia_sts(struct ifnet *, struct ifmediareq *);
128
129 void vr_mii_sync(struct vr_softc *);
130 void vr_mii_send(struct vr_softc *, u_int32_t, int);
131 int vr_mii_readreg(struct vr_softc *, struct vr_mii_frame *);
132 int vr_mii_writereg(struct vr_softc *, struct vr_mii_frame *);
133 int vr_miibus_readreg(struct device *, int, int);
134 void vr_miibus_writereg(struct device *, int, int, int);
135 void vr_miibus_statchg(struct device *);
136
137 void vr_setcfg(struct vr_softc *, int);
138 void vr_setmulti(struct vr_softc *);
139 void vr_reset(struct vr_softc *);
140 int vr_list_rx_init(struct vr_softc *);
141 int vr_list_tx_init(struct vr_softc *);
142
143 #define VR_SETBIT(sc, reg, x) \
144 CSR_WRITE_1(sc, reg, \
145 CSR_READ_1(sc, reg) | (x))
146
147 #define VR_CLRBIT(sc, reg, x) \
148 CSR_WRITE_1(sc, reg, \
149 CSR_READ_1(sc, reg) & ~(x))
150
151 #define VR_SETBIT16(sc, reg, x) \
152 CSR_WRITE_2(sc, reg, \
153 CSR_READ_2(sc, reg) | (x))
154
155 #define VR_CLRBIT16(sc, reg, x) \
156 CSR_WRITE_2(sc, reg, \
157 CSR_READ_2(sc, reg) & ~(x))
158
159 #define VR_SETBIT32(sc, reg, x) \
160 CSR_WRITE_4(sc, reg, \
161 CSR_READ_4(sc, reg) | (x))
162
163 #define VR_CLRBIT32(sc, reg, x) \
164 CSR_WRITE_4(sc, reg, \
165 CSR_READ_4(sc, reg) & ~(x))
166
167 #define SIO_SET(x) \
168 CSR_WRITE_1(sc, VR_MIICMD, \
169 CSR_READ_1(sc, VR_MIICMD) | (x))
170
171 #define SIO_CLR(x) \
172 CSR_WRITE_1(sc, VR_MIICMD, \
173 CSR_READ_1(sc, VR_MIICMD) & ~(x))
174
175 #ifdef VR_USESWSHIFT
176 /*
177 * Sync the PHYs by setting data bit and strobing the clock 32 times.
178 */
179 void
vr_mii_sync(sc)180 vr_mii_sync(sc)
181 struct vr_softc *sc;
182 {
183 register int i;
184
185 SIO_SET(VR_MIICMD_DIR|VR_MIICMD_DATAIN);
186
187 for (i = 0; i < 32; i++) {
188 SIO_SET(VR_MIICMD_CLK);
189 DELAY(1);
190 SIO_CLR(VR_MIICMD_CLK);
191 DELAY(1);
192 }
193
194 return;
195 }
196
197 /*
198 * Clock a series of bits through the MII.
199 */
200 void
vr_mii_send(sc,bits,cnt)201 vr_mii_send(sc, bits, cnt)
202 struct vr_softc *sc;
203 u_int32_t bits;
204 int cnt;
205 {
206 int i;
207
208 SIO_CLR(VR_MIICMD_CLK);
209
210 for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
211 if (bits & i) {
212 SIO_SET(VR_MIICMD_DATAIN);
213 } else {
214 SIO_CLR(VR_MIICMD_DATAIN);
215 }
216 DELAY(1);
217 SIO_CLR(VR_MIICMD_CLK);
218 DELAY(1);
219 SIO_SET(VR_MIICMD_CLK);
220 }
221 }
222 #endif
223
224 /*
225 * Read an PHY register through the MII.
226 */
227 int
vr_mii_readreg(sc,frame)228 vr_mii_readreg(sc, frame)
229 struct vr_softc *sc;
230 struct vr_mii_frame *frame;
231
232 #ifdef VR_USESWSHIFT
233 {
234 int i, ack, s;
235
236 s = splimp();
237
238 /*
239 * Set up frame for RX.
240 */
241 frame->mii_stdelim = VR_MII_STARTDELIM;
242 frame->mii_opcode = VR_MII_READOP;
243 frame->mii_turnaround = 0;
244 frame->mii_data = 0;
245
246 CSR_WRITE_1(sc, VR_MIICMD, 0);
247 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
248
249 /*
250 * Turn on data xmit.
251 */
252 SIO_SET(VR_MIICMD_DIR);
253
254 vr_mii_sync(sc);
255
256 /*
257 * Send command/address info.
258 */
259 vr_mii_send(sc, frame->mii_stdelim, 2);
260 vr_mii_send(sc, frame->mii_opcode, 2);
261 vr_mii_send(sc, frame->mii_phyaddr, 5);
262 vr_mii_send(sc, frame->mii_regaddr, 5);
263
264 /* Idle bit */
265 SIO_CLR((VR_MIICMD_CLK|VR_MIICMD_DATAIN));
266 DELAY(1);
267 SIO_SET(VR_MIICMD_CLK);
268 DELAY(1);
269
270 /* Turn off xmit. */
271 SIO_CLR(VR_MIICMD_DIR);
272
273 /* Check for ack */
274 SIO_CLR(VR_MIICMD_CLK);
275 DELAY(1);
276 ack = CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT;
277 SIO_SET(VR_MIICMD_CLK);
278 DELAY(1);
279
280 /*
281 * Now try reading data bits. If the ack failed, we still
282 * need to clock through 16 cycles to keep the PHY(s) in sync.
283 */
284 if (ack) {
285 for(i = 0; i < 16; i++) {
286 SIO_CLR(VR_MIICMD_CLK);
287 DELAY(1);
288 SIO_SET(VR_MIICMD_CLK);
289 DELAY(1);
290 }
291 goto fail;
292 }
293
294 for (i = 0x8000; i; i >>= 1) {
295 SIO_CLR(VR_MIICMD_CLK);
296 DELAY(1);
297 if (!ack) {
298 if (CSR_READ_4(sc, VR_MIICMD) & VR_MIICMD_DATAOUT)
299 frame->mii_data |= i;
300 DELAY(1);
301 }
302 SIO_SET(VR_MIICMD_CLK);
303 DELAY(1);
304 }
305
306 fail:
307
308 SIO_CLR(VR_MIICMD_CLK);
309 DELAY(1);
310 SIO_SET(VR_MIICMD_CLK);
311 DELAY(1);
312
313 splx(s);
314
315 if (ack)
316 return(1);
317 return(0);
318 }
319 #else
320 {
321 int s, i;
322
323 s = splimp();
324
325 /* Set the PHY-address */
326 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
327 frame->mii_phyaddr);
328
329 /* Set the register-address */
330 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
331 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_READ_ENB);
332
333 for (i = 0; i < 10000; i++) {
334 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_READ_ENB) == 0)
335 break;
336 DELAY(1);
337 }
338
339 frame->mii_data = CSR_READ_2(sc, VR_MIIDATA);
340
341 (void)splx(s);
342
343 return(0);
344 }
345 #endif
346
347
348 /*
349 * Write to a PHY register through the MII.
350 */
351 int
vr_mii_writereg(sc,frame)352 vr_mii_writereg(sc, frame)
353 struct vr_softc *sc;
354 struct vr_mii_frame *frame;
355
356 #ifdef VR_USESWSHIFT
357 {
358 int s;
359
360 s = splimp();
361
362 CSR_WRITE_1(sc, VR_MIICMD, 0);
363 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_DIRECTPGM);
364
365 /*
366 * Set up frame for TX.
367 */
368
369 frame->mii_stdelim = VR_MII_STARTDELIM;
370 frame->mii_opcode = VR_MII_WRITEOP;
371 frame->mii_turnaround = VR_MII_TURNAROUND;
372
373 /*
374 * Turn on data output.
375 */
376 SIO_SET(VR_MIICMD_DIR);
377
378 vr_mii_sync(sc);
379
380 vr_mii_send(sc, frame->mii_stdelim, 2);
381 vr_mii_send(sc, frame->mii_opcode, 2);
382 vr_mii_send(sc, frame->mii_phyaddr, 5);
383 vr_mii_send(sc, frame->mii_regaddr, 5);
384 vr_mii_send(sc, frame->mii_turnaround, 2);
385 vr_mii_send(sc, frame->mii_data, 16);
386
387 /* Idle bit. */
388 SIO_SET(VR_MIICMD_CLK);
389 DELAY(1);
390 SIO_CLR(VR_MIICMD_CLK);
391 DELAY(1);
392
393 /*
394 * Turn off xmit.
395 */
396 SIO_CLR(VR_MIICMD_DIR);
397
398 splx(s);
399
400 return(0);
401 }
402 #else
403 {
404 int s, i;
405
406 s = splimp();
407
408 /* Set the PHY-address */
409 CSR_WRITE_1(sc, VR_PHYADDR, (CSR_READ_1(sc, VR_PHYADDR)& 0xe0)|
410 frame->mii_phyaddr);
411
412 /* Set the register-address and data to write */
413 CSR_WRITE_1(sc, VR_MIIADDR, frame->mii_regaddr);
414 CSR_WRITE_2(sc, VR_MIIDATA, frame->mii_data);
415
416 VR_SETBIT(sc, VR_MIICMD, VR_MIICMD_WRITE_ENB);
417
418 for (i = 0; i < 10000; i++) {
419 if ((CSR_READ_1(sc, VR_MIICMD) & VR_MIICMD_WRITE_ENB) == 0)
420 break;
421 DELAY(1);
422 }
423
424 (void)splx(s);
425
426 return(0);
427 }
428 #endif
429
430 int
vr_miibus_readreg(dev,phy,reg)431 vr_miibus_readreg(dev, phy, reg)
432 struct device *dev;
433 int phy, reg;
434 {
435 struct vr_softc *sc = (struct vr_softc *)dev;
436 struct vr_mii_frame frame;
437
438 switch (sc->vr_revid) {
439 case REV_ID_VT6102_APOLLO:
440 if (phy != 1)
441 return 0;
442 default:
443 break;
444 }
445
446 bzero((char *)&frame, sizeof(frame));
447
448 frame.mii_phyaddr = phy;
449 frame.mii_regaddr = reg;
450 vr_mii_readreg(sc, &frame);
451
452 return(frame.mii_data);
453 }
454
455 void
vr_miibus_writereg(dev,phy,reg,data)456 vr_miibus_writereg(dev, phy, reg, data)
457 struct device *dev;
458 int phy, reg, data;
459 {
460 struct vr_softc *sc = (struct vr_softc *)dev;
461 struct vr_mii_frame frame;
462
463 switch (sc->vr_revid) {
464 case REV_ID_VT6102_APOLLO:
465 if (phy != 1)
466 return;
467 default:
468 break;
469 }
470
471 bzero((char *)&frame, sizeof(frame));
472
473 frame.mii_phyaddr = phy;
474 frame.mii_regaddr = reg;
475 frame.mii_data = data;
476
477 vr_mii_writereg(sc, &frame);
478
479 return;
480 }
481
482 void
vr_miibus_statchg(dev)483 vr_miibus_statchg(dev)
484 struct device *dev;
485 {
486 struct vr_softc *sc = (struct vr_softc *)dev;
487
488 vr_setcfg(sc, sc->sc_mii.mii_media_active);
489 }
490
491 /*
492 * Program the 64-bit multicast hash filter.
493 */
494 void
vr_setmulti(sc)495 vr_setmulti(sc)
496 struct vr_softc *sc;
497 {
498 struct ifnet *ifp;
499 int h = 0;
500 u_int32_t hashes[2] = { 0, 0 };
501 struct arpcom *ac = &sc->arpcom;
502 struct ether_multi *enm;
503 struct ether_multistep step;
504 u_int8_t rxfilt;
505 int mcnt = 0;
506
507 ifp = &sc->arpcom.ac_if;
508
509 rxfilt = CSR_READ_1(sc, VR_RXCFG);
510
511 allmulti:
512 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
513 rxfilt |= VR_RXCFG_RX_MULTI;
514 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
515 CSR_WRITE_4(sc, VR_MAR0, 0xFFFFFFFF);
516 CSR_WRITE_4(sc, VR_MAR1, 0xFFFFFFFF);
517 return;
518 }
519
520 /* first, zot all the existing hash bits */
521 CSR_WRITE_4(sc, VR_MAR0, 0);
522 CSR_WRITE_4(sc, VR_MAR1, 0);
523
524 /* now program new ones */
525 ETHER_FIRST_MULTI(step, ac, enm);
526 while (enm != NULL) {
527 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
528 ifp->if_flags |= IFF_ALLMULTI;
529 goto allmulti;
530 }
531 h = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN) >> 26;
532 if (h < 32)
533 hashes[0] |= (1 << h);
534 else
535 hashes[1] |= (1 << (h - 32));
536 mcnt++;
537
538 ETHER_NEXT_MULTI(step, enm);
539 }
540
541 if (mcnt)
542 rxfilt |= VR_RXCFG_RX_MULTI;
543 else
544 rxfilt &= ~VR_RXCFG_RX_MULTI;
545
546 CSR_WRITE_4(sc, VR_MAR0, hashes[0]);
547 CSR_WRITE_4(sc, VR_MAR1, hashes[1]);
548 CSR_WRITE_1(sc, VR_RXCFG, rxfilt);
549
550 return;
551 }
552
553 /*
554 * In order to fiddle with the
555 * 'full-duplex' and '100Mbps' bits in the netconfig register, we
556 * first have to put the transmit and/or receive logic in the idle state.
557 */
558 void
vr_setcfg(sc,media)559 vr_setcfg(sc, media)
560 struct vr_softc *sc;
561 int media;
562 {
563 int restart = 0;
564
565 if (CSR_READ_2(sc, VR_COMMAND) & (VR_CMD_TX_ON|VR_CMD_RX_ON)) {
566 restart = 1;
567 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_TX_ON|VR_CMD_RX_ON));
568 }
569
570 if ((media & IFM_GMASK) == IFM_FDX)
571 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
572 else
573 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_FULLDUPLEX);
574
575 if (restart)
576 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_TX_ON|VR_CMD_RX_ON);
577
578 return;
579 }
580
581 void
vr_reset(sc)582 vr_reset(sc)
583 struct vr_softc *sc;
584 {
585 register int i;
586
587 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RESET);
588
589 for (i = 0; i < VR_TIMEOUT; i++) {
590 DELAY(10);
591 if (!(CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RESET))
592 break;
593 }
594 if (i == VR_TIMEOUT) {
595 if (sc->vr_revid < REV_ID_VT3065_A)
596 printf("%s: reset never completed!\n",
597 sc->sc_dev.dv_xname);
598 else {
599 /* Use newer force reset command */
600 printf("%s: Using force reset command.\n",
601 sc->sc_dev.dv_xname);
602 VR_SETBIT(sc, VR_MISC_CR1, VR_MISCCR1_FORSRST);
603 }
604 }
605
606 /* Wait a little while for the chip to get its brains in order. */
607 DELAY(1000);
608 }
609
610 const struct pci_matchid vr_devices[] = {
611 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINE },
612 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINEII },
613 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_RHINEII_2 },
614 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105 },
615 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT6105M },
616 { PCI_VENDOR_DELTA, PCI_PRODUCT_DELTA_RHINEII },
617 { PCI_VENDOR_ADDTRON, PCI_PRODUCT_ADDTRON_RHINEII },
618 };
619
620 /*
621 * Probe for a VIA Rhine chip.
622 */
623 int
vr_probe(parent,match,aux)624 vr_probe(parent, match, aux)
625 struct device *parent;
626 void *match, *aux;
627 {
628 return (pci_matchbyid((struct pci_attach_args *)aux, vr_devices,
629 sizeof(vr_devices)/sizeof(vr_devices[0])));
630 }
631
632 /*
633 * Attach the interface. Allocate softc structures, do ifmedia
634 * setup and ethernet/BPF attach.
635 */
636 void
vr_attach(parent,self,aux)637 vr_attach(parent, self, aux)
638 struct device *parent, *self;
639 void *aux;
640 {
641 int s, i;
642 u_int32_t command;
643 struct vr_softc *sc = (struct vr_softc *)self;
644 struct pci_attach_args *pa = aux;
645 pci_chipset_tag_t pc = pa->pa_pc;
646 pci_intr_handle_t ih;
647 const char *intrstr = NULL;
648 struct ifnet *ifp = &sc->arpcom.ac_if;
649 bus_addr_t iobase;
650 bus_size_t iosize;
651 int rseg;
652 caddr_t kva;
653
654 s = splimp();
655
656 /*
657 * Handle power management nonsense.
658 */
659 command = pci_conf_read(pa->pa_pc, pa->pa_tag,
660 VR_PCI_CAPID) & 0x000000ff;
661 if (command == 0x01) {
662 command = pci_conf_read(pa->pa_pc, pa->pa_tag,
663 VR_PCI_PWRMGMTCTRL);
664 if (command & VR_PSTATE_MASK) {
665 u_int32_t iobase, membase, irq;
666
667 /* Save important PCI config data. */
668 iobase = pci_conf_read(pa->pa_pc, pa->pa_tag,
669 VR_PCI_LOIO);
670 membase = pci_conf_read(pa->pa_pc, pa->pa_tag,
671 VR_PCI_LOMEM);
672 irq = pci_conf_read(pa->pa_pc, pa->pa_tag,
673 VR_PCI_INTLINE);
674
675 /* Reset the power state. */
676 command &= 0xFFFFFFFC;
677 pci_conf_write(pa->pa_pc, pa->pa_tag,
678 VR_PCI_PWRMGMTCTRL, command);
679
680 /* Restore PCI config data. */
681 pci_conf_write(pa->pa_pc, pa->pa_tag,
682 VR_PCI_LOIO, iobase);
683 pci_conf_write(pa->pa_pc, pa->pa_tag,
684 VR_PCI_LOMEM, membase);
685 pci_conf_write(pa->pa_pc, pa->pa_tag,
686 VR_PCI_INTLINE, irq);
687 }
688 }
689
690 /*
691 * Map control/status registers.
692 */
693 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
694 sc->vr_revid = PCI_REVISION(pa->pa_class);
695
696 #ifdef VR_USEIOSPACE
697 if (!(command & PCI_COMMAND_IO_ENABLE)) {
698 printf(": failed to enable I/O ports\n");
699 goto fail;
700 }
701 if (pci_io_find(pc, pa->pa_tag, VR_PCI_LOIO, &iobase, &iosize)) {
702 printf(": failed to find i/o space\n");
703 goto fail;
704 }
705 if (bus_space_map(pa->pa_iot, iobase, iosize, 0, &sc->vr_bhandle)) {
706 printf(": failed map i/o space\n");
707 goto fail;
708 }
709 sc->vr_btag = pa->pa_iot;
710 #else
711 if (!(command & PCI_COMMAND_MEM_ENABLE)) {
712 printf(": failed to enable memory mapping\n");
713 goto fail;
714 }
715 if (pci_mem_find(pc, pa->pa_tag, VR_PCI_LOMEM, &iobase, &iosize)) {
716 printf(": failed to find memory space\n");
717 goto fail;
718 }
719 if (bus_space_map(pa->pa_memt, iobase, iosize, 0, &sc->vr_bhandle)) {
720 printf(": failed map memory space\n");
721 goto fail;
722 }
723 sc->vr_btag = pa->pa_memt;
724 #endif
725
726 /* Allocate interrupt */
727 if (pci_intr_map(pa, &ih)) {
728 printf(": couldn't map interrupt\n");
729 goto fail;
730 }
731 intrstr = pci_intr_string(pc, ih);
732 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, vr_intr, sc,
733 self->dv_xname);
734 if (sc->sc_ih == NULL) {
735 printf(": could not establish interrupt");
736 if (intrstr != NULL)
737 printf(" at %s", intrstr);
738 printf("\n");
739 goto fail;
740 }
741 printf(": %s", intrstr);
742
743 /*
744 * Windows may put the chip in suspend mode when it
745 * shuts down. Be sure to kick it in the head to wake it
746 * up again.
747 */
748 VR_CLRBIT(sc, VR_STICKHW, (VR_STICKHW_DS0|VR_STICKHW_DS1));
749
750 /* Reset the adapter. */
751 vr_reset(sc);
752
753 /*
754 * Turn on bit2 (MIION) in PCI configuration register 0x53 during
755 * initialization and disable AUTOPOLL.
756 */
757 pci_conf_write(pa->pa_pc, pa->pa_tag, VR_PCI_MODE,
758 pci_conf_read(pa->pa_pc, pa->pa_tag, VR_PCI_MODE) |
759 (VR_MODE3_MIION << 24));
760 VR_CLRBIT(sc, VR_MIICMD, VR_MIICMD_AUTOPOLL);
761
762 /*
763 * Get station address. The way the Rhine chips work,
764 * you're not allowed to directly access the EEPROM once
765 * they've been programmed a special way. Consequently,
766 * we need to read the node address from the PAR0 and PAR1
767 * registers.
768 */
769 VR_SETBIT(sc, VR_EECSR, VR_EECSR_LOAD);
770 DELAY(1000);
771 for (i = 0; i < ETHER_ADDR_LEN; i++)
772 sc->arpcom.ac_enaddr[i] = CSR_READ_1(sc, VR_PAR0 + i);
773
774 /*
775 * A Rhine chip was detected. Inform the world.
776 */
777 printf(" address %s\n", ether_sprintf(sc->arpcom.ac_enaddr));
778
779 sc->sc_dmat = pa->pa_dmat;
780 if (bus_dmamem_alloc(sc->sc_dmat, sizeof(struct vr_list_data),
781 PAGE_SIZE, 0, &sc->sc_listseg, 1, &rseg, BUS_DMA_NOWAIT)) {
782 printf("%s: can't alloc list\n", sc->sc_dev.dv_xname);
783 goto fail;
784 }
785 if (bus_dmamem_map(sc->sc_dmat, &sc->sc_listseg, rseg,
786 sizeof(struct vr_list_data), &kva, BUS_DMA_NOWAIT)) {
787 printf("%s: can't map dma buffers (%d bytes)\n",
788 sc->sc_dev.dv_xname, (int)sizeof(struct vr_list_data));
789 bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);
790 goto fail;
791 }
792 if (bus_dmamap_create(sc->sc_dmat, sizeof(struct vr_list_data), 1,
793 sizeof(struct vr_list_data), 0, BUS_DMA_NOWAIT, &sc->sc_listmap)) {
794 printf("%s: can't create dma map\n", sc->sc_dev.dv_xname);
795 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data));
796 bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);
797 goto fail;
798 }
799 if (bus_dmamap_load(sc->sc_dmat, sc->sc_listmap, kva,
800 sizeof(struct vr_list_data), NULL, BUS_DMA_NOWAIT)) {
801 printf("%s: can't load dma map\n", sc->sc_dev.dv_xname);
802 bus_dmamap_destroy(sc->sc_dmat, sc->sc_listmap);
803 bus_dmamem_unmap(sc->sc_dmat, kva, sizeof(struct vr_list_data));
804 bus_dmamem_free(sc->sc_dmat, &sc->sc_listseg, rseg);
805 goto fail;
806 }
807 sc->vr_ldata = (struct vr_list_data *)kva;
808 bzero(sc->vr_ldata, sizeof(struct vr_list_data));
809
810 ifp = &sc->arpcom.ac_if;
811 ifp->if_softc = sc;
812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
813 ifp->if_ioctl = vr_ioctl;
814 ifp->if_start = vr_start;
815 ifp->if_watchdog = vr_watchdog;
816 ifp->if_baudrate = 10000000;
817 IFQ_SET_READY(&ifp->if_snd);
818 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ);
819
820 /*
821 * Do MII setup.
822 */
823 sc->sc_mii.mii_ifp = ifp;
824 sc->sc_mii.mii_readreg = vr_miibus_readreg;
825 sc->sc_mii.mii_writereg = vr_miibus_writereg;
826 sc->sc_mii.mii_statchg = vr_miibus_statchg;
827 ifmedia_init(&sc->sc_mii.mii_media, 0, vr_ifmedia_upd, vr_ifmedia_sts);
828 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, MII_OFFSET_ANY,
829 0);
830 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
831 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
832 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
833 } else
834 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
835 timeout_set(&sc->sc_to, vr_tick, sc);
836
837 /*
838 * Call MI attach routines.
839 */
840 if_attach(ifp);
841 ether_ifattach(ifp);
842
843 shutdownhook_establish(vr_shutdown, sc);
844
845 fail:
846 splx(s);
847 return;
848 }
849
850 /*
851 * Initialize the transmit descriptors.
852 */
853 int
vr_list_tx_init(sc)854 vr_list_tx_init(sc)
855 struct vr_softc *sc;
856 {
857 struct vr_chain_data *cd;
858 struct vr_list_data *ld;
859 int i;
860
861 cd = &sc->vr_cdata;
862 ld = sc->vr_ldata;
863 for (i = 0; i < VR_TX_LIST_CNT; i++) {
864 cd->vr_tx_chain[i].vr_ptr = &ld->vr_tx_list[i];
865 cd->vr_tx_chain[i].vr_paddr =
866 sc->sc_listmap->dm_segs[0].ds_addr +
867 offsetof(struct vr_list_data, vr_tx_list[i]);
868
869 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
870 MCLBYTES, 0, BUS_DMA_NOWAIT, &cd->vr_tx_chain[i].vr_map))
871 return (ENOBUFS);
872
873 if (i == (VR_TX_LIST_CNT - 1))
874 cd->vr_tx_chain[i].vr_nextdesc =
875 &cd->vr_tx_chain[0];
876 else
877 cd->vr_tx_chain[i].vr_nextdesc =
878 &cd->vr_tx_chain[i + 1];
879 }
880
881 cd->vr_tx_cons = cd->vr_tx_prod = &cd->vr_tx_chain[0];
882
883 return (0);
884 }
885
886
887 /*
888 * Initialize the RX descriptors and allocate mbufs for them. Note that
889 * we arrange the descriptors in a closed ring, so that the last descriptor
890 * points back to the first.
891 */
892 int
vr_list_rx_init(sc)893 vr_list_rx_init(sc)
894 struct vr_softc *sc;
895 {
896 struct vr_chain_data *cd;
897 struct vr_list_data *ld;
898 int i;
899 struct vr_desc *d;
900
901 cd = &sc->vr_cdata;
902 ld = sc->vr_ldata;
903
904 for (i = 0; i < VR_RX_LIST_CNT; i++) {
905 d = (struct vr_desc *)&ld->vr_rx_list[i];
906 cd->vr_rx_chain[i].vr_ptr = d;
907 cd->vr_rx_chain[i].vr_paddr =
908 sc->sc_listmap->dm_segs[0].ds_addr +
909 offsetof(struct vr_list_data, vr_rx_list[i]);
910 cd->vr_rx_chain[i].vr_buf =
911 (u_int8_t *)malloc(MCLBYTES, M_DEVBUF, M_NOWAIT);
912 if (cd->vr_rx_chain[i].vr_buf == NULL)
913 return (ENOBUFS);
914
915 if (bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
916 0, BUS_DMA_NOWAIT | BUS_DMA_READ,
917 &cd->vr_rx_chain[i].vr_map))
918 return (ENOBUFS);
919
920 if (bus_dmamap_load(sc->sc_dmat, cd->vr_rx_chain[i].vr_map,
921 cd->vr_rx_chain[i].vr_buf, MCLBYTES, NULL, BUS_DMA_NOWAIT))
922 return (ENOBUFS);
923 bus_dmamap_sync(sc->sc_dmat, cd->vr_rx_chain[i].vr_map,
924 0, cd->vr_rx_chain[i].vr_map->dm_mapsize,
925 BUS_DMASYNC_PREREAD);
926
927 d->vr_data =
928 htole32(cd->vr_rx_chain[i].vr_map->dm_segs[0].ds_addr +
929 sizeof(u_int64_t));
930 d->vr_ctl = htole32(VR_RXCTL | VR_RXLEN);
931
932 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
933 sc->sc_listmap->dm_mapsize, BUS_DMASYNC_PREWRITE);
934
935 d->vr_status = htole32(VR_RXSTAT);
936
937 if (i == (VR_RX_LIST_CNT - 1)) {
938 cd->vr_rx_chain[i].vr_nextdesc =
939 &cd->vr_rx_chain[0];
940 ld->vr_rx_list[i].vr_next =
941 htole32(sc->sc_listmap->dm_segs[0].ds_addr +
942 offsetof(struct vr_list_data, vr_rx_list[0]));
943 } else {
944 cd->vr_rx_chain[i].vr_nextdesc =
945 &cd->vr_rx_chain[i + 1];
946 ld->vr_rx_list[i].vr_next =
947 htole32(sc->sc_listmap->dm_segs[0].ds_addr +
948 offsetof(struct vr_list_data, vr_rx_list[i + 1]));
949 }
950 }
951
952 cd->vr_rx_head = &cd->vr_rx_chain[0];
953
954 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
955 sc->sc_listmap->dm_mapsize,
956 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
957
958 return(0);
959 }
960
961 /*
962 * A frame has been uploaded: pass the resulting mbuf chain up to
963 * the higher level protocols.
964 */
965 void
vr_rxeof(sc)966 vr_rxeof(sc)
967 struct vr_softc *sc;
968 {
969 struct mbuf *m0;
970 struct ifnet *ifp;
971 struct vr_chain_onefrag *cur_rx;
972 int total_len = 0;
973 u_int32_t rxstat;
974
975 ifp = &sc->arpcom.ac_if;
976
977 for (;;) {
978
979 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
980 0, sc->sc_listmap->dm_mapsize,
981 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
982 rxstat = letoh32(sc->vr_cdata.vr_rx_head->vr_ptr->vr_status);
983 if (rxstat & VR_RXSTAT_OWN)
984 break;
985
986 m0 = NULL;
987 cur_rx = sc->vr_cdata.vr_rx_head;
988 sc->vr_cdata.vr_rx_head = cur_rx->vr_nextdesc;
989
990 /*
991 * If an error occurs, update stats, clear the
992 * status word and leave the mbuf cluster in place:
993 * it should simply get re-used next time this descriptor
994 * comes up in the ring.
995 */
996 if (rxstat & VR_RXSTAT_RXERR) {
997 ifp->if_ierrors++;
998 printf("%s: rx error (%02x):",
999 sc->sc_dev.dv_xname, rxstat & 0x000000ff);
1000 if (rxstat & VR_RXSTAT_CRCERR)
1001 printf(" crc error");
1002 if (rxstat & VR_RXSTAT_FRAMEALIGNERR)
1003 printf(" frame alignment error");
1004 if (rxstat & VR_RXSTAT_FIFOOFLOW)
1005 printf(" FIFO overflow");
1006 if (rxstat & VR_RXSTAT_GIANT)
1007 printf(" received giant packet");
1008 if (rxstat & VR_RXSTAT_RUNT)
1009 printf(" received runt packet");
1010 if (rxstat & VR_RXSTAT_BUSERR)
1011 printf(" system bus error");
1012 if (rxstat & VR_RXSTAT_BUFFERR)
1013 printf(" rx buffer error");
1014 printf("\n");
1015
1016 /* Reinitialize descriptor */
1017 cur_rx->vr_ptr->vr_status = htole32(VR_RXSTAT);
1018 cur_rx->vr_ptr->vr_data =
1019 htole32(cur_rx->vr_map->dm_segs[0].ds_addr +
1020 sizeof(u_int64_t));
1021 cur_rx->vr_ptr->vr_ctl = htole32(VR_RXCTL | VR_RXLEN);
1022 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1023 0, sc->sc_listmap->dm_mapsize,
1024 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1025 continue;
1026 }
1027
1028 /* No errors; receive the packet. */
1029 total_len = VR_RXBYTES(letoh32(cur_rx->vr_ptr->vr_status));
1030
1031 /*
1032 * XXX The VIA Rhine chip includes the CRC with every
1033 * received frame, and there's no way to turn this
1034 * behavior off (at least, I can't find anything in
1035 * the manual that explains how to do it) so we have
1036 * to trim off the CRC manually.
1037 */
1038 total_len -= ETHER_CRC_LEN;
1039
1040 bus_dmamap_sync(sc->sc_dmat, cur_rx->vr_map, 0,
1041 cur_rx->vr_map->dm_mapsize,
1042 BUS_DMASYNC_POSTREAD);
1043 m0 = m_devget(cur_rx->vr_buf + sizeof(u_int64_t) - ETHER_ALIGN,
1044 total_len + ETHER_ALIGN, 0, ifp, NULL);
1045 bus_dmamap_sync(sc->sc_dmat, cur_rx->vr_map, 0,
1046 cur_rx->vr_map->dm_mapsize,
1047 BUS_DMASYNC_PREREAD);
1048
1049 /* Reinitialize descriptor */
1050 cur_rx->vr_ptr->vr_status = htole32(VR_RXSTAT);
1051 cur_rx->vr_ptr->vr_data =
1052 htole32(cur_rx->vr_map->dm_segs[0].ds_addr +
1053 sizeof(u_int64_t));
1054 cur_rx->vr_ptr->vr_ctl = htole32(VR_RXCTL | VR_RXLEN);
1055 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
1056 sc->sc_listmap->dm_mapsize,
1057 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1058
1059 if (m0 == NULL) {
1060 ifp->if_ierrors++;
1061 continue;
1062 }
1063 m_adj(m0, ETHER_ALIGN);
1064
1065 ifp->if_ipackets++;
1066
1067 #if NBPFILTER > 0
1068 /*
1069 * Handle BPF listeners. Let the BPF user see the packet.
1070 */
1071 if (ifp->if_bpf)
1072 bpf_mtap(ifp->if_bpf, m0);
1073 #endif
1074 /* pass it on. */
1075 ether_input_mbuf(ifp, m0);
1076 }
1077
1078 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap,
1079 0, sc->sc_listmap->dm_mapsize,
1080 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1081
1082 return;
1083 }
1084
1085 void
vr_rxeoc(sc)1086 vr_rxeoc(sc)
1087 struct vr_softc *sc;
1088 {
1089 struct ifnet *ifp;
1090 int i;
1091
1092 ifp = &sc->arpcom.ac_if;
1093
1094 ifp->if_ierrors++;
1095
1096 VR_CLRBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1097 DELAY(10000);
1098
1099 for (i = 0x400;
1100 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_RX_ON);
1101 i--)
1102 ; /* Wait for receiver to stop */
1103
1104 if (!i) {
1105 printf("%s: rx shutdown error!\n", sc->sc_dev.dv_xname);
1106 sc->vr_flags |= VR_F_RESTART;
1107 return;
1108 }
1109
1110 vr_rxeof(sc);
1111
1112 CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr);
1113 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_ON);
1114 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_RX_GO);
1115
1116 return;
1117 }
1118
1119 /*
1120 * A frame was downloaded to the chip. It's safe for us to clean up
1121 * the list buffers.
1122 */
1123
1124 void
vr_txeof(sc)1125 vr_txeof(sc)
1126 struct vr_softc *sc;
1127 {
1128 struct vr_chain *cur_tx;
1129 struct ifnet *ifp;
1130
1131 ifp = &sc->arpcom.ac_if;
1132
1133 /*
1134 * Go through our tx list and free mbufs for those
1135 * frames that have been transmitted.
1136 */
1137 cur_tx = sc->vr_cdata.vr_tx_cons;
1138 while(cur_tx->vr_mbuf != NULL) {
1139 u_int32_t txstat;
1140 int i;
1141
1142 txstat = letoh32(cur_tx->vr_ptr->vr_status);
1143
1144 if ((txstat & VR_TXSTAT_ABRT) ||
1145 (txstat & VR_TXSTAT_UDF)) {
1146 for (i = 0x400;
1147 i && (CSR_READ_2(sc, VR_COMMAND) & VR_CMD_TX_ON);
1148 i--)
1149 ; /* Wait for chip to shutdown */
1150 if (!i) {
1151 printf("%s: tx shutdown timeout\n",
1152 sc->sc_dev.dv_xname);
1153 sc->vr_flags |= VR_F_RESTART;
1154 break;
1155 }
1156 VR_TXOWN(cur_tx) = htole32(VR_TXSTAT_OWN);
1157 CSR_WRITE_4(sc, VR_TXADDR, cur_tx->vr_paddr);
1158 break;
1159 }
1160
1161 if (txstat & VR_TXSTAT_OWN)
1162 break;
1163
1164 if (txstat & VR_TXSTAT_ERRSUM) {
1165 ifp->if_oerrors++;
1166 if (txstat & VR_TXSTAT_DEFER)
1167 ifp->if_collisions++;
1168 if (txstat & VR_TXSTAT_LATECOLL)
1169 ifp->if_collisions++;
1170 }
1171
1172 ifp->if_collisions +=(txstat & VR_TXSTAT_COLLCNT) >> 3;
1173
1174 ifp->if_opackets++;
1175 if (cur_tx->vr_map != NULL && cur_tx->vr_map->dm_segs > 0)
1176 bus_dmamap_unload(sc->sc_dmat, cur_tx->vr_map);
1177
1178 m_freem(cur_tx->vr_mbuf);
1179 cur_tx->vr_mbuf = NULL;
1180 ifp->if_flags &= ~IFF_OACTIVE;
1181
1182 cur_tx = cur_tx->vr_nextdesc;
1183 }
1184
1185 sc->vr_cdata.vr_tx_cons = cur_tx;
1186 if (cur_tx->vr_mbuf == NULL)
1187 ifp->if_timer = 0;
1188 }
1189
1190 void
vr_tick(xsc)1191 vr_tick(xsc)
1192 void *xsc;
1193 {
1194 struct vr_softc *sc = xsc;
1195 int s;
1196
1197 s = splimp();
1198 if (sc->vr_flags & VR_F_RESTART) {
1199 printf("%s: restarting\n", sc->sc_dev.dv_xname);
1200 vr_stop(sc);
1201 vr_reset(sc);
1202 vr_init(sc);
1203 sc->vr_flags &= ~VR_F_RESTART;
1204 }
1205
1206 mii_tick(&sc->sc_mii);
1207 timeout_add(&sc->sc_to, hz);
1208 splx(s);
1209 }
1210
1211 int
vr_intr(arg)1212 vr_intr(arg)
1213 void *arg;
1214 {
1215 struct vr_softc *sc;
1216 struct ifnet *ifp;
1217 u_int16_t status;
1218 int claimed = 0;
1219
1220 sc = arg;
1221 ifp = &sc->arpcom.ac_if;
1222
1223 /* Supress unwanted interrupts. */
1224 if (!(ifp->if_flags & IFF_UP)) {
1225 vr_stop(sc);
1226 return 0;
1227 }
1228
1229 /* Disable interrupts. */
1230 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1231
1232 for (;;) {
1233
1234 status = CSR_READ_2(sc, VR_ISR);
1235 if (status)
1236 CSR_WRITE_2(sc, VR_ISR, status);
1237
1238 if ((status & VR_INTRS) == 0)
1239 break;
1240
1241 claimed = 1;
1242
1243 if (status & VR_ISR_RX_OK)
1244 vr_rxeof(sc);
1245
1246 if (status & VR_ISR_RX_DROPPED) {
1247 printf("%s: rx packet lost\n", sc->sc_dev.dv_xname);
1248 ifp->if_ierrors++;
1249 }
1250
1251 if ((status & VR_ISR_RX_ERR) || (status & VR_ISR_RX_NOBUF) ||
1252 (status & VR_ISR_RX_NOBUF) || (status & VR_ISR_RX_OFLOW)) {
1253 printf("%s: receive error (%04x)",
1254 sc->sc_dev.dv_xname, status);
1255 if (status & VR_ISR_RX_NOBUF)
1256 printf(" no buffers");
1257 if (status & VR_ISR_RX_OFLOW)
1258 printf(" overflow");
1259 if (status & VR_ISR_RX_DROPPED)
1260 printf(" packet lost");
1261 printf("\n");
1262 vr_rxeoc(sc);
1263 }
1264
1265 if ((status & VR_ISR_BUSERR) || (status & VR_ISR_TX_UNDERRUN)) {
1266 vr_reset(sc);
1267 vr_init(sc);
1268 break;
1269 }
1270
1271 if ((status & VR_ISR_TX_OK) || (status & VR_ISR_TX_ABRT) ||
1272 (status & VR_ISR_TX_ABRT2) || (status & VR_ISR_UDFI)) {
1273 vr_txeof(sc);
1274 if ((status & VR_ISR_UDFI) ||
1275 (status & VR_ISR_TX_ABRT2) ||
1276 (status & VR_ISR_TX_ABRT)) {
1277 ifp->if_oerrors++;
1278 if (sc->vr_cdata.vr_tx_cons->vr_mbuf != NULL) {
1279 VR_SETBIT16(sc, VR_COMMAND,
1280 VR_CMD_TX_ON);
1281 VR_SETBIT16(sc, VR_COMMAND,
1282 VR_CMD_TX_GO);
1283 }
1284 }
1285 }
1286 }
1287
1288 /* Re-enable interrupts. */
1289 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1290
1291 if (!IFQ_IS_EMPTY(&ifp->if_snd)) {
1292 vr_start(ifp);
1293 }
1294
1295 return (claimed);
1296 }
1297
1298 /*
1299 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1300 * pointers to the fragment pointers.
1301 */
1302 int
vr_encap(sc,c,m_head)1303 vr_encap(sc, c, m_head)
1304 struct vr_softc *sc;
1305 struct vr_chain *c;
1306 struct mbuf *m_head;
1307 {
1308 struct vr_desc *f = NULL;
1309 struct mbuf *m = m_head;
1310 struct mbuf *m_new = NULL;
1311
1312 m = m_head;
1313
1314 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1315 if (m_new == NULL)
1316 return (1);
1317 if (m_head->m_pkthdr.len > MHLEN) {
1318 MCLGET(m_new, M_DONTWAIT);
1319 if (!(m_new->m_flags & M_EXT)) {
1320 m_freem(m_new);
1321 return (1);
1322 }
1323 }
1324 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1325 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1326
1327 /*
1328 * The Rhine chip doesn't auto-pad, so we have to make
1329 * sure to pad short frames out to the minimum frame length
1330 * ourselves.
1331 */
1332 if (m_new->m_len < VR_MIN_FRAMELEN) {
1333 /* data field should be padded with octets of zero */
1334 bzero(&m_new->m_data[m_new->m_len],
1335 VR_MIN_FRAMELEN-m_new->m_len);
1336 m_new->m_pkthdr.len += VR_MIN_FRAMELEN - m_new->m_len;
1337 m_new->m_len = m_new->m_pkthdr.len;
1338 }
1339
1340 if (bus_dmamap_load_mbuf(sc->sc_dmat, c->vr_map, m_new,
1341 BUS_DMA_NOWAIT | BUS_DMA_WRITE)) {
1342 m_freem(m_new);
1343 return (1);
1344 }
1345 bus_dmamap_sync(sc->sc_dmat, c->vr_map, 0, c->vr_map->dm_mapsize,
1346 BUS_DMASYNC_PREWRITE);
1347
1348 m_freem(m_head);
1349
1350 f = c->vr_ptr;
1351 f->vr_data = htole32(c->vr_map->dm_segs[0].ds_addr);
1352 f->vr_ctl = htole32(c->vr_map->dm_mapsize);
1353 f->vr_ctl |= htole32(VR_TXCTL_TLINK|VR_TXCTL_FIRSTFRAG);
1354 f->vr_status = htole32(0);
1355
1356 c->vr_mbuf = m_new;
1357 c->vr_ptr->vr_ctl |= htole32(VR_TXCTL_LASTFRAG|VR_TXCTL_FINT);
1358 c->vr_ptr->vr_next = htole32(c->vr_nextdesc->vr_paddr);
1359
1360 return (0);
1361 }
1362
1363 /*
1364 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1365 * to the mbuf data regions directly in the transmit lists. We also save a
1366 * copy of the pointers since the transmit list fragment pointers are
1367 * physical addresses.
1368 */
1369
1370 void
vr_start(ifp)1371 vr_start(ifp)
1372 struct ifnet *ifp;
1373 {
1374 struct vr_softc *sc;
1375 struct mbuf *m_head;
1376 struct vr_chain *cur_tx;
1377
1378 sc = ifp->if_softc;
1379
1380 cur_tx = sc->vr_cdata.vr_tx_prod;
1381 while (cur_tx->vr_mbuf == NULL) {
1382 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1383 if (m_head == NULL)
1384 break;
1385
1386 /* Pack the data into the descriptor. */
1387 if (vr_encap(sc, cur_tx, m_head)) {
1388 /* Rollback, send what we were able to encap. */
1389 if (ALTQ_IS_ENABLED(&ifp->if_snd)) {
1390 m_freem(m_head);
1391 } else {
1392 IF_PREPEND(&ifp->if_snd, m_head);
1393 }
1394 break;
1395 }
1396
1397 VR_TXOWN(cur_tx) = htole32(VR_TXSTAT_OWN);
1398
1399 #if NBPFILTER > 0
1400 /*
1401 * If there's a BPF listener, bounce a copy of this frame
1402 * to him.
1403 */
1404 if (ifp->if_bpf)
1405 bpf_mtap(ifp->if_bpf, cur_tx->vr_mbuf);
1406 #endif
1407 cur_tx = cur_tx->vr_nextdesc;
1408 }
1409 if (cur_tx != sc->vr_cdata.vr_tx_prod || cur_tx->vr_mbuf != NULL) {
1410 sc->vr_cdata.vr_tx_prod = cur_tx;
1411
1412 bus_dmamap_sync(sc->sc_dmat, sc->sc_listmap, 0,
1413 sc->sc_listmap->dm_mapsize,
1414 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1415
1416 /* Tell the chip to start transmitting. */
1417 VR_SETBIT16(sc, VR_COMMAND, /*VR_CMD_TX_ON|*/VR_CMD_TX_GO);
1418
1419 /* Set a timeout in case the chip goes out to lunch. */
1420 ifp->if_timer = 5;
1421
1422 if (cur_tx->vr_mbuf != NULL)
1423 ifp->if_flags |= IFF_OACTIVE;
1424 }
1425 }
1426
1427 void
vr_init(xsc)1428 vr_init(xsc)
1429 void *xsc;
1430 {
1431 struct vr_softc *sc = xsc;
1432 struct ifnet *ifp = &sc->arpcom.ac_if;
1433 struct mii_data *mii = &sc->sc_mii;
1434 int s, i;
1435
1436 s = splimp();
1437
1438 /*
1439 * Cancel pending I/O and free all RX/TX buffers.
1440 */
1441 vr_stop(sc);
1442 vr_reset(sc);
1443
1444 /*
1445 * Set our station address.
1446 */
1447 for (i = 0; i < ETHER_ADDR_LEN; i++)
1448 CSR_WRITE_1(sc, VR_PAR0 + i, sc->arpcom.ac_enaddr[i]);
1449
1450 /* Set DMA size */
1451 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_DMA_LENGTH);
1452 VR_SETBIT(sc, VR_BCR0, VR_BCR0_DMA_STORENFWD);
1453
1454 /*
1455 * BCR0 and BCR1 can override the RXCFG and TXCFG registers,
1456 * so we must set both.
1457 */
1458 VR_CLRBIT(sc, VR_BCR0, VR_BCR0_RX_THRESH);
1459 VR_SETBIT(sc, VR_BCR0, VR_BCR0_RXTHRESH128BYTES);
1460
1461 VR_CLRBIT(sc, VR_BCR1, VR_BCR1_TX_THRESH);
1462 VR_SETBIT(sc, VR_BCR1, VR_BCR1_TXTHRESHSTORENFWD);
1463
1464 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_THRESH);
1465 VR_SETBIT(sc, VR_RXCFG, VR_RXTHRESH_128BYTES);
1466
1467 VR_CLRBIT(sc, VR_TXCFG, VR_TXCFG_TX_THRESH);
1468 VR_SETBIT(sc, VR_TXCFG, VR_TXTHRESH_STORENFWD);
1469
1470 /* Init circular RX list. */
1471 if (vr_list_rx_init(sc) == ENOBUFS) {
1472 printf("%s: initialization failed: no memory for rx buffers\n",
1473 sc->sc_dev.dv_xname);
1474 vr_stop(sc);
1475 splx(s);
1476 return;
1477 }
1478
1479 /*
1480 * Init tx descriptors.
1481 */
1482 if (vr_list_tx_init(sc) == ENOBUFS) {
1483 printf("%s: initialization failed: no memory for tx buffers\n",
1484 sc->sc_dev.dv_xname);
1485 vr_stop(sc);
1486 splx(s);
1487 return;
1488 }
1489
1490 /* If we want promiscuous mode, set the allframes bit. */
1491 if (ifp->if_flags & IFF_PROMISC)
1492 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1493 else
1494 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_PROMISC);
1495
1496 /* Set capture broadcast bit to capture broadcast frames. */
1497 if (ifp->if_flags & IFF_BROADCAST)
1498 VR_SETBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1499 else
1500 VR_CLRBIT(sc, VR_RXCFG, VR_RXCFG_RX_BROAD);
1501
1502 /*
1503 * Program the multicast filter, if necessary.
1504 */
1505 vr_setmulti(sc);
1506
1507 /*
1508 * Load the address of the RX list.
1509 */
1510 CSR_WRITE_4(sc, VR_RXADDR, sc->vr_cdata.vr_rx_head->vr_paddr);
1511
1512 /* Enable receiver and transmitter. */
1513 CSR_WRITE_2(sc, VR_COMMAND, VR_CMD_TX_NOPOLL|VR_CMD_START|
1514 VR_CMD_TX_ON|VR_CMD_RX_ON|
1515 VR_CMD_RX_GO);
1516
1517 CSR_WRITE_4(sc, VR_TXADDR, sc->sc_listmap->dm_segs[0].ds_addr +
1518 offsetof(struct vr_list_data, vr_tx_list[0]));
1519
1520 /*
1521 * Enable interrupts.
1522 */
1523 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
1524 CSR_WRITE_2(sc, VR_IMR, VR_INTRS);
1525
1526 /* Restore state of BMCR */
1527 mii_mediachg(mii);
1528
1529 ifp->if_flags |= IFF_RUNNING;
1530 ifp->if_flags &= ~IFF_OACTIVE;
1531
1532 if (!timeout_pending(&sc->sc_to))
1533 timeout_add(&sc->sc_to, hz);
1534
1535 splx(s);
1536 }
1537
1538 /*
1539 * Set media options.
1540 */
1541 int
vr_ifmedia_upd(ifp)1542 vr_ifmedia_upd(ifp)
1543 struct ifnet *ifp;
1544 {
1545 struct vr_softc *sc = ifp->if_softc;
1546
1547 if (ifp->if_flags & IFF_UP)
1548 vr_init(sc);
1549
1550 return(0);
1551 }
1552
1553 /*
1554 * Report current media status.
1555 */
1556 void
vr_ifmedia_sts(ifp,ifmr)1557 vr_ifmedia_sts(ifp, ifmr)
1558 struct ifnet *ifp;
1559 struct ifmediareq *ifmr;
1560 {
1561 struct vr_softc *sc = ifp->if_softc;
1562 struct mii_data *mii = &sc->sc_mii;
1563
1564 mii_pollstat(mii);
1565 ifmr->ifm_active = mii->mii_media_active;
1566 ifmr->ifm_status = mii->mii_media_status;
1567 }
1568
1569 int
vr_ioctl(ifp,command,data)1570 vr_ioctl(ifp, command, data)
1571 struct ifnet *ifp;
1572 u_long command;
1573 caddr_t data;
1574 {
1575 struct vr_softc *sc = ifp->if_softc;
1576 struct ifreq *ifr = (struct ifreq *) data;
1577 int s, error = 0;
1578 struct ifaddr *ifa = (struct ifaddr *)data;
1579
1580 s = splimp();
1581
1582 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) {
1583 splx(s);
1584 return error;
1585 }
1586
1587 switch(command) {
1588 case SIOCSIFADDR:
1589 ifp->if_flags |= IFF_UP;
1590 switch (ifa->ifa_addr->sa_family) {
1591 #ifdef INET
1592 case AF_INET:
1593 vr_init(sc);
1594 arp_ifinit(&sc->arpcom, ifa);
1595 break;
1596 #endif /* INET */
1597 default:
1598 vr_init(sc);
1599 break;
1600 }
1601 break;
1602 case SIOCSIFFLAGS:
1603 if (ifp->if_flags & IFF_UP) {
1604 vr_init(sc);
1605 } else {
1606 if (ifp->if_flags & IFF_RUNNING)
1607 vr_stop(sc);
1608 }
1609 error = 0;
1610 break;
1611 case SIOCADDMULTI:
1612 case SIOCDELMULTI:
1613 error = (command == SIOCADDMULTI) ?
1614 ether_addmulti(ifr, &sc->arpcom) :
1615 ether_delmulti(ifr, &sc->arpcom);
1616
1617 if (error == ENETRESET) {
1618 /*
1619 * Multicast list has changed; set the hardware
1620 * filter accordingly.
1621 */
1622 if (ifp->if_flags & IFF_RUNNING)
1623 vr_setmulti(sc);
1624 error = 0;
1625 }
1626 break;
1627 case SIOCGIFMEDIA:
1628 case SIOCSIFMEDIA:
1629 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
1630 break;
1631 default:
1632 error = EINVAL;
1633 break;
1634 }
1635
1636 splx(s);
1637
1638 return(error);
1639 }
1640
1641 void
vr_watchdog(ifp)1642 vr_watchdog(ifp)
1643 struct ifnet *ifp;
1644 {
1645 struct vr_softc *sc;
1646
1647 sc = ifp->if_softc;
1648
1649 ifp->if_oerrors++;
1650 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
1651
1652 vr_stop(sc);
1653 vr_reset(sc);
1654 vr_init(sc);
1655
1656 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1657 vr_start(ifp);
1658
1659 return;
1660 }
1661
1662 /*
1663 * Stop the adapter and free any mbufs allocated to the
1664 * RX and TX lists.
1665 */
1666 void
vr_stop(sc)1667 vr_stop(sc)
1668 struct vr_softc *sc;
1669 {
1670 int i;
1671 struct ifnet *ifp;
1672 bus_dmamap_t map;
1673
1674 ifp = &sc->arpcom.ac_if;
1675 ifp->if_timer = 0;
1676
1677 if (timeout_pending(&sc->sc_to))
1678 timeout_del(&sc->sc_to);
1679
1680 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1681
1682 VR_SETBIT16(sc, VR_COMMAND, VR_CMD_STOP);
1683 VR_CLRBIT16(sc, VR_COMMAND, (VR_CMD_RX_ON|VR_CMD_TX_ON));
1684 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1685 CSR_WRITE_4(sc, VR_TXADDR, 0x00000000);
1686 CSR_WRITE_4(sc, VR_RXADDR, 0x00000000);
1687
1688 /*
1689 * Free data in the RX lists.
1690 */
1691 for (i = 0; i < VR_RX_LIST_CNT; i++) {
1692
1693 if (sc->vr_cdata.vr_rx_chain[i].vr_buf != NULL) {
1694 free(sc->vr_cdata.vr_rx_chain[i].vr_buf, M_DEVBUF);
1695 sc->vr_cdata.vr_rx_chain[i].vr_buf = NULL;
1696 }
1697
1698 map = sc->vr_cdata.vr_rx_chain[i].vr_map;
1699 if (map != NULL) {
1700 if (map->dm_segs > 0)
1701 bus_dmamap_unload(sc->sc_dmat, map);
1702 bus_dmamap_destroy(sc->sc_dmat, map);
1703 sc->vr_cdata.vr_rx_chain[i].vr_map = NULL;
1704 }
1705 }
1706 bzero((char *)&sc->vr_ldata->vr_rx_list,
1707 sizeof(sc->vr_ldata->vr_rx_list));
1708
1709 /*
1710 * Free the TX list buffers.
1711 */
1712 for (i = 0; i < VR_TX_LIST_CNT; i++) {
1713 bus_dmamap_t map;
1714
1715 if (sc->vr_cdata.vr_tx_chain[i].vr_mbuf != NULL) {
1716 m_freem(sc->vr_cdata.vr_tx_chain[i].vr_mbuf);
1717 sc->vr_cdata.vr_tx_chain[i].vr_mbuf = NULL;
1718 }
1719 map = sc->vr_cdata.vr_tx_chain[i].vr_map;
1720 if (map != NULL) {
1721 if (map->dm_nsegs > 0)
1722 bus_dmamap_unload(sc->sc_dmat, map);
1723 bus_dmamap_destroy(sc->sc_dmat, map);
1724 sc->vr_cdata.vr_tx_chain[i].vr_map = NULL;
1725 }
1726 }
1727
1728 bzero((char *)&sc->vr_ldata->vr_tx_list,
1729 sizeof(sc->vr_ldata->vr_tx_list));
1730
1731 return;
1732 }
1733
1734 /*
1735 * Stop all chip I/O so that the kernel's probe routines don't
1736 * get confused by errant DMAs when rebooting.
1737 */
1738 void
vr_shutdown(arg)1739 vr_shutdown(arg)
1740 void *arg;
1741 {
1742 struct vr_softc *sc = (struct vr_softc *)arg;
1743
1744 vr_stop(sc);
1745 }
1746