1 /* $OpenBSD: if_tx.c,v 1.27 2003/08/19 14:01:35 mpech Exp $ */
2 /* $FreeBSD: src/sys/pci/if_tx.c,v 1.45 2001/02/07 20:11:02 semenu Exp $ */
3
4 /*-
5 * Copyright (c) 1997 Semen Ustimenko (semen@iclub.nsu.ru)
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 /*
31 * EtherPower II 10/100 Fast Ethernet (tx0)
32 * (aka SMC9432TX based on SMC83c170 EPIC chip)
33 *
34 * Thanks are going to Steve Bauer and Jason Wright.
35 *
36 * todo:
37 * Implement FULL IFF_MULTICAST support.
38 *
39 */
40
41 /* We should define compile time options before if_txvar.h included */
42 #define EARLY_RX 1
43 /*#define EPIC_DEBUG 1*/
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/sockio.h>
48 #include <sys/mbuf.h>
49 #include <sys/malloc.h>
50 #include <sys/kernel.h>
51 #include <sys/socket.h>
52 #include <sys/queue.h>
53
54 #if defined(__FreeBSD__)
55 #define NBPFILTER 1
56
57 #include <net/if.h>
58 #include <net/if_arp.h>
59 #include <net/ethernet.h>
60 #include <net/if_media.h>
61
62 #include <net/bpf.h>
63
64 #include <vm/vm.h> /* for vtophys */
65 #include <vm/pmap.h> /* for vtophys */
66 #include <machine/clock.h> /* for DELAY */
67 #include <machine/bus_memio.h>
68 #include <machine/bus_pio.h>
69 #include <machine/bus.h>
70 #include <machine/resource.h>
71 #include <sys/bus.h>
72 #include <sys/rman.h>
73
74 #include <pci/pcireg.h>
75 #include <pci/pcivar.h>
76
77 #include <dev/mii/mii.h>
78 #include <dev/mii/miivar.h>
79 #include <dev/mii/miidevs.h>
80
81 #include <dev/mii/lxtphyreg.h>
82
83 #include "miibus_if.h"
84
85 #include <pci/if_txvar.h>
86 #else /* __OpenBSD__ */
87 #include "bpfilter.h"
88
89 #include <sys/device.h>
90
91 #include <net/if.h>
92 #include <net/if_dl.h>
93 #include <net/if_types.h>
94 #include <net/if_media.h>
95
96 #ifdef INET
97 #include <netinet/in.h>
98 #include <netinet/in_systm.h>
99 #include <netinet/in_var.h>
100 #include <netinet/ip.h>
101 #include <netinet/if_ether.h>
102 #endif
103
104 #ifdef IPX
105 #include <netipx/ipx.h>
106 #include <netipx/ipx_if.h>
107 #endif
108
109 #ifdef NS
110 #include <netns/ns.h>
111 #include <netns/ns_if.h>
112 #endif
113
114 #if NBPFILTER > 0
115 #include <net/bpf.h>
116 #endif
117
118 #include <uvm/uvm_extern.h>
119
120 #include <dev/mii/mii.h>
121 #include <dev/mii/miivar.h>
122 #include <dev/mii/miidevs.h>
123 #include <dev/mii/lxtphyreg.h>
124
125 #include <dev/pci/pcivar.h>
126 #include <dev/pci/pcireg.h>
127 #include <dev/pci/pcidevs.h>
128
129 #include <dev/pci/if_txvar.h>
130 #endif
131
132 #if defined(__FreeBSD__)
133 MODULE_DEPEND(tx, miibus, 1, 1, 1);
134 #endif
135
136 #if defined(__FreeBSD__)
137 #define EPIC_INTR_RET_TYPE void
138 #define EPIC_MIIBUS_WRITEREG_RET_TYPE int
139 #define EPIC_STATIC static
140 #else /* __OpenBSD__ */
141 #define EPIC_INTR_RET_TYPE int
142 #define EPIC_MIIBUS_WRITEREG_RET_TYPE void
143 #define EPIC_STATIC
144 #endif
145
146 EPIC_STATIC int epic_ifioctl(register struct ifnet *, u_long, caddr_t);
147 EPIC_STATIC EPIC_INTR_RET_TYPE epic_intr(void *);
148 EPIC_STATIC int epic_common_attach(epic_softc_t *);
149 EPIC_STATIC void epic_ifstart(struct ifnet *);
150 EPIC_STATIC void epic_ifwatchdog(struct ifnet *);
151 EPIC_STATIC int epic_init(epic_softc_t *);
152 EPIC_STATIC void epic_stop(epic_softc_t *);
153 EPIC_STATIC void epic_rx_done(epic_softc_t *);
154 EPIC_STATIC void epic_tx_done(epic_softc_t *);
155 EPIC_STATIC int epic_init_rings(epic_softc_t *);
156 EPIC_STATIC void epic_free_rings(epic_softc_t *);
157 EPIC_STATIC void epic_stop_activity(epic_softc_t *);
158 EPIC_STATIC void epic_start_activity(epic_softc_t *);
159 EPIC_STATIC void epic_set_rx_mode(epic_softc_t *);
160 EPIC_STATIC void epic_set_tx_mode(epic_softc_t *);
161 EPIC_STATIC void epic_set_mc_table(epic_softc_t *);
162 EPIC_STATIC int epic_read_eeprom(epic_softc_t *,u_int16_t);
163 EPIC_STATIC void epic_output_eepromw(epic_softc_t *, u_int16_t);
164 EPIC_STATIC u_int16_t epic_input_eepromw(epic_softc_t *);
165 EPIC_STATIC u_int8_t epic_eeprom_clock(epic_softc_t *,u_int8_t);
166 EPIC_STATIC void epic_write_eepromreg(epic_softc_t *,u_int8_t);
167 EPIC_STATIC u_int8_t epic_read_eepromreg(epic_softc_t *);
168
169 EPIC_STATIC int epic_read_phy_reg(epic_softc_t *, int, int);
170 EPIC_STATIC void epic_write_phy_reg(epic_softc_t *, int, int, int);
171
172 EPIC_STATIC int epic_miibus_readreg(struct device*, int, int);
173 EPIC_STATIC EPIC_MIIBUS_WRITEREG_RET_TYPE epic_miibus_writereg(struct device*, int, int, int);
174 EPIC_STATIC void epic_miibus_statchg(struct device *);
175 EPIC_STATIC void epic_miibus_mediainit(struct device *);
176
177
178 EPIC_STATIC int epic_ifmedia_upd(struct ifnet *);
179 EPIC_STATIC void epic_ifmedia_sts(struct ifnet *, struct ifmediareq *);
180 EPIC_STATIC void epic_tick(void *);
181
182 /* -------------------------------------------------------------------------
183 OS-specific part
184 ------------------------------------------------------------------------- */
185
186 #if defined(__OpenBSD__)
187 /* -----------------------------OpenBSD------------------------------------- */
188
189 int epic_openbsd_probe(struct device *,void *,void *);
190 void epic_openbsd_attach(struct device *, struct device *, void *);
191 void epic_openbsd_shutdown(void *);
192
193 struct cfattach tx_ca = {
194 sizeof(epic_softc_t), epic_openbsd_probe, epic_openbsd_attach
195 };
196 struct cfdriver tx_cd = {
197 NULL,"tx",DV_IFNET
198 };
199
200 /* Synopsis: Check if device id corresponds with SMC83C170 id. */
201 int
epic_openbsd_probe(struct device * parent,void * match,void * aux)202 epic_openbsd_probe(
203 struct device *parent,
204 void *match,
205 void *aux )
206 {
207 struct pci_attach_args *pa = aux;
208
209 if (PCI_VENDOR(pa->pa_id) == SMC_VENDORID &&
210 PCI_PRODUCT(pa->pa_id) == SMC_DEVICEID_83C170)
211 return (1);
212 return (0);
213 }
214
215 void
epic_openbsd_attach(struct device * parent,struct device * self,void * aux)216 epic_openbsd_attach(
217 struct device *parent,
218 struct device *self,
219 void *aux )
220 {
221 epic_softc_t *sc = (epic_softc_t*)self;
222 struct pci_attach_args *pa = aux;
223 pci_chipset_tag_t pc = pa->pa_pc;
224 pci_intr_handle_t ih;
225 const char *intrstr = NULL;
226 struct ifnet *ifp;
227 bus_size_t iosize;
228 u_int32_t command;
229
230 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
231 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE |
232 PCI_COMMAND_MASTER_ENABLE;
233 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command);
234 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
235
236 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) == 0) {
237 printf(": neither i/o nor mem enabled\n");
238 return;
239 }
240
241 if (command & PCI_COMMAND_MEM_ENABLE) {
242 if (pci_mapreg_map(pa, PCI_BASEMEM, PCI_MAPREG_TYPE_MEM, 0,
243 &sc->sc_st, &sc->sc_sh, NULL, &iosize, 0)) {
244 printf(": can't map mem space\n");
245 return;
246 }
247 } else {
248 if (pci_mapreg_map(pa, PCI_BASEIO, PCI_MAPREG_TYPE_IO, 0,
249 &sc->sc_st, &sc->sc_sh, NULL, &iosize, 0)) {
250 printf(": can't map i/o space\n");
251 return;
252 }
253 }
254
255 ifp = &sc->sc_if;
256 bcopy(sc->dev.dv_xname, ifp->if_xname,IFNAMSIZ);
257 ifp->if_softc = sc;
258 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
259 ifp->if_ioctl = epic_ifioctl;
260 ifp->if_start = epic_ifstart;
261 ifp->if_watchdog = epic_ifwatchdog;
262 IFQ_SET_READY(&ifp->if_snd);
263
264 /* Fetch card id */
265 sc->cardvend = pci_conf_read(pc, pa->pa_tag, PCI_SUBVEND_0);
266 sc->cardid = pci_conf_read(pc, pa->pa_tag, PCI_SUBDEV_0);
267
268 /* Do common attach procedure */
269 if( epic_common_attach(sc) ) return;
270
271 /* Map interrupt */
272 if( pci_intr_map(pa, &ih)) {
273 printf(": can't map interrupt\n");
274 return;
275 }
276 intrstr = pci_intr_string(pc, ih);
277 sc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc,
278 self->dv_xname);
279
280 if( NULL == sc->sc_ih ) {
281 printf(": can't establish interrupt");
282 if( intrstr )printf(" at %s",intrstr);
283 printf("\n");
284 return;
285 }
286
287 /* Display some info */
288 printf(": %s address %s\n", intrstr, ether_sprintf(sc->sc_macaddr));
289
290 /* Init ifmedia interface */
291 ifmedia_init(&sc->miibus.mii_media, 0,
292 epic_ifmedia_upd, epic_ifmedia_sts);
293 sc->miibus.mii_ifp = ifp;
294 sc->miibus.mii_readreg = epic_miibus_readreg;
295 sc->miibus.mii_writereg = epic_miibus_writereg;
296 sc->miibus.mii_statchg = epic_miibus_statchg;
297 mii_phy_probe(self, &sc->miibus, 0xffffffff);
298 if (LIST_FIRST(&sc->miibus.mii_phys) == NULL) {
299 ifmedia_add(&sc->miibus.mii_media, IFM_ETHER|IFM_NONE,0,NULL);
300 ifmedia_set(&sc->miibus.mii_media, IFM_ETHER|IFM_NONE);
301 } else
302 ifmedia_set(&sc->miibus.mii_media, IFM_ETHER|IFM_AUTO);
303
304 timeout_set(&sc->sc_tmo, epic_tick, sc);
305
306 /* Attach os interface and bpf */
307 if_attach(ifp);
308 ether_ifattach(ifp);
309
310 /* Set shutdown routine to stop DMA process */
311 shutdownhook_establish(epic_openbsd_shutdown, sc);
312 }
313
314 /* Simple call epic_stop() */
315 void
epic_openbsd_shutdown(void * sc)316 epic_openbsd_shutdown(
317 void *sc)
318 {
319 epic_stop(sc);
320 }
321
322 #else /* __FreeBSD__ */
323 /* -----------------------------FreeBSD------------------------------------- */
324
325 static int epic_freebsd_probe(device_t);
326 static int epic_freebsd_attach(device_t);
327 static void epic_freebsd_shutdown(device_t);
328 static int epic_freebsd_detach(device_t);
329 static struct epic_type *epic_devtype(device_t);
330
331 static device_method_t epic_methods[] = {
332 /* Device interface */
333 DEVMETHOD(device_probe, epic_freebsd_probe),
334 DEVMETHOD(device_attach, epic_freebsd_attach),
335 DEVMETHOD(device_detach, epic_freebsd_detach),
336 DEVMETHOD(device_shutdown, epic_freebsd_shutdown),
337
338 /* bus interface */
339 DEVMETHOD(bus_print_child, bus_generic_print_child),
340 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
341
342 /* MII interface */
343 DEVMETHOD(miibus_readreg, epic_miibus_readreg),
344 DEVMETHOD(miibus_writereg, epic_miibus_writereg),
345 DEVMETHOD(miibus_statchg, epic_miibus_statchg),
346 DEVMETHOD(miibus_mediainit, epic_miibus_mediainit),
347
348 { 0, 0 }
349 };
350
351 static driver_t epic_driver = {
352 "tx",
353 epic_methods,
354 sizeof(epic_softc_t)
355 };
356
357 static devclass_t epic_devclass;
358
359 DRIVER_MODULE(if_tx, pci, epic_driver, epic_devclass, 0, 0);
360 DRIVER_MODULE(miibus, tx, miibus_driver, miibus_devclass, 0, 0);
361
362 static struct epic_type epic_devs[] = {
363 { SMC_VENDORID, SMC_DEVICEID_83C170,
364 "SMC EtherPower II 10/100" },
365 { 0, 0, NULL }
366 };
367
368 static int
epic_freebsd_probe(dev)369 epic_freebsd_probe(dev)
370 device_t dev;
371 {
372 struct epic_type *t;
373
374 t = epic_devtype(dev);
375
376 if (t != NULL) {
377 device_set_desc(dev, t->name);
378 return(0);
379 }
380
381 return(ENXIO);
382 }
383
384 static struct epic_type *
epic_devtype(dev)385 epic_devtype(dev)
386 device_t dev;
387 {
388 struct epic_type *t;
389
390 t = epic_devs;
391
392 while(t->name != NULL) {
393 if ((pci_get_vendor(dev) == t->ven_id) &&
394 (pci_get_device(dev) == t->dev_id)) {
395 return(t);
396 }
397 t++;
398 }
399 return (NULL);
400 }
401
402 #if defined(EPIC_USEIOSPACE)
403 #define EPIC_RES SYS_RES_IOPORT
404 #define EPIC_RID PCIR_BASEIO
405 #else
406 #define EPIC_RES SYS_RES_MEMORY
407 #define EPIC_RID PCIR_BASEMEM
408 #endif
409
410 /*
411 * Do FreeBSD-specific attach routine, like map registers, alloc softc
412 * structure and etc.
413 */
414 static int
epic_freebsd_attach(dev)415 epic_freebsd_attach(dev)
416 device_t dev;
417 {
418 struct ifnet *ifp;
419 epic_softc_t *sc;
420 u_int32_t command;
421 int unit, error;
422 int i, s, rid, tmp;
423
424 s = splimp ();
425
426 sc = device_get_softc(dev);
427 unit = device_get_unit(dev);
428
429 /* Preinitialize softc structure */
430 bzero(sc, sizeof(epic_softc_t));
431 sc->unit = unit;
432 sc->dev = dev;
433
434 /* Fill ifnet structure */
435 ifp = &sc->sc_if;
436 ifp->if_unit = unit;
437 ifp->if_name = "tx";
438 ifp->if_softc = sc;
439 ifp->if_flags = IFF_BROADCAST|IFF_SIMPLEX|IFF_MULTICAST;
440 ifp->if_ioctl = epic_ifioctl;
441 ifp->if_output = ether_output;
442 ifp->if_start = epic_ifstart;
443 ifp->if_watchdog = epic_ifwatchdog;
444 ifp->if_init = (if_init_f_t*)epic_init;
445 ifp->if_timer = 0;
446 ifp->if_baudrate = 10000000;
447 IFQ_SET_MAXLEN(&ifp->if_snd, TX_RING_SIZE - 1);
448 IFQ_SET_READY(&ifp->if_snd);
449
450 /* Enable ports, memory and busmastering */
451 command = pci_read_config(dev, PCIR_COMMAND, 4);
452 command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN;
453 pci_write_config(dev, PCIR_COMMAND, command, 4);
454 command = pci_read_config(dev, PCIR_COMMAND, 4);
455
456 #if defined(EPIC_USEIOSPACE)
457 if (!(command & PCIM_CMD_PORTEN)) {
458 device_printf(dev, "failed to enable I/O mapping!\n");
459 error = ENXIO;
460 goto fail;
461 }
462 #else
463 if (!(command & PCIM_CMD_MEMEN)) {
464 device_printf(dev, "failed to enable memory mapping!\n");
465 error = ENXIO;
466 goto fail;
467 }
468 #endif
469
470 rid = EPIC_RID;
471 sc->res = bus_alloc_resource(dev, EPIC_RES, &rid, 0, ~0, 1,
472 RF_ACTIVE);
473
474 if (sc->res == NULL) {
475 device_printf(dev, "couldn't map ports/memory\n");
476 error = ENXIO;
477 goto fail;
478 }
479
480 sc->sc_st = rman_get_bustag(sc->res);
481 sc->sc_sh = rman_get_bushandle(sc->res);
482
483 /* Allocate interrupt */
484 rid = 0;
485 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
486 RF_SHAREABLE | RF_ACTIVE);
487
488 if (sc->irq == NULL) {
489 device_printf(dev, "couldn't map interrupt\n");
490 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
491 error = ENXIO;
492 goto fail;
493 }
494
495 error = bus_setup_intr(dev, sc->irq, INTR_TYPE_NET,
496 epic_intr, sc, &sc->sc_ih);
497
498 if (error) {
499 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
500 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
501 device_printf(dev, "couldn't set up irq\n");
502 goto fail;
503 }
504
505 /* Bring the chip out of low-power mode and reset it. */
506 CSR_WRITE_4( sc, GENCTL, GENCTL_SOFT_RESET );
507 DELAY(500);
508
509 /* Workaround for Application Note 7-15 */
510 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
511
512 /*
513 * Do ifmedia setup.
514 */
515 if (mii_phy_probe(dev, &sc->miibus,
516 epic_ifmedia_upd, epic_ifmedia_sts)) {
517 device_printf(dev, "MII without any PHY!?\n");
518 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
519 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
520 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
521 error = ENXIO;
522 goto fail;
523 }
524
525 /* Do OS independent part, including chip wakeup and reset */
526 if (epic_common_attach(sc)) {
527 device_printf(dev, "memory distribution error\n");
528 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
529 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
530 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
531 error = ENXIO;
532 goto fail;
533 }
534
535 /* Fetch card id */
536 sc->cardvend = pci_read_config(sc->dev, PCIR_SUBVEND_0, 2);
537 sc->cardid = pci_read_config(sc->dev, PCIR_SUBDEV_0, 2);
538 printf("vend/id(%x/%x) ", sc->cardvend, sc->cardid);
539
540 /* Display ethernet address ,... */
541 device_printf(dev, "address %6D,", sc->sc_macaddr, ":");
542
543 /* board type and ... */
544 printf(" type ");
545 for(i=0x2c;i<0x32;i++) {
546 tmp = epic_read_eeprom( sc, i );
547 if( ' ' == (u_int8_t)tmp ) break;
548 printf("%c",(u_int8_t)tmp);
549 tmp >>= 8;
550 if( ' ' == (u_int8_t)tmp ) break;
551 printf("%c",(u_int8_t)tmp);
552 }
553 printf("\n");
554
555 /* Attach to OS's managers */
556 ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
557 callout_handle_init(&sc->stat_ch);
558
559 fail:
560 splx(s);
561
562 return(error);
563 }
564
565 /*
566 * Detach driver and free resources
567 */
568 static int
epic_freebsd_detach(dev)569 epic_freebsd_detach(dev)
570 device_t dev;
571 {
572 struct ifnet *ifp;
573 epic_softc_t *sc;
574 int s;
575
576 s = splimp();
577
578 sc = device_get_softc(dev);
579 ifp = &sc->arpcom.ac_if;
580
581 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
582
583 epic_stop(sc);
584
585 bus_generic_detach(dev);
586 device_delete_child(dev, sc->miibus);
587
588 bus_teardown_intr(dev, sc->irq, sc->sc_ih);
589 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq);
590 bus_release_resource(dev, EPIC_RES, EPIC_RID, sc->res);
591
592 free(sc->pool, M_DEVBUF);
593
594 splx(s);
595
596 return(0);
597 }
598
599 #undef EPIC_RES
600 #undef EPIC_RID
601
602 /*
603 * Stop all chip I/O so that the kernel's probe routines don't
604 * get confused by errant DMAs when rebooting.
605 */
606 EPIC_STATIC void
epic_freebsd_shutdown(dev)607 epic_freebsd_shutdown(dev)
608 device_t dev;
609 {
610 epic_softc_t *sc;
611
612 sc = device_get_softc(dev);
613
614 epic_stop(sc);
615
616 return;
617 }
618 #endif /* __OpenBSD__ */
619
620 /* ------------------------------------------------------------------------
621 OS-independing part
622 ------------------------------------------------------------------------ */
623
624 /*
625 * This is if_ioctl handler.
626 */
627 EPIC_STATIC int
epic_ifioctl(ifp,command,data)628 epic_ifioctl(ifp, command, data)
629 struct ifnet *ifp;
630 u_long command;
631 caddr_t data;
632 {
633 epic_softc_t *sc = ifp->if_softc;
634 struct mii_data *mii;
635 struct ifreq *ifr = (struct ifreq *) data;
636 int x, error = 0;
637
638 x = splimp();
639
640 switch (command) {
641 #if defined(__FreeBSD__)
642 case SIOCSIFADDR:
643 case SIOCGIFADDR:
644 case SIOCSIFMTU:
645 error = ether_ioctl(ifp, command, data);
646 break;
647 #else /* __OpenBSD__ */
648 case SIOCSIFADDR: {
649 struct ifaddr *ifa = (struct ifaddr *)data;
650
651 ifp->if_flags |= IFF_UP;
652 switch(ifa->ifa_addr->sa_family) {
653 #if INET
654 case AF_INET:
655 epic_stop(sc);
656 epic_init(sc);
657 arp_ifinit(&sc->arpcom,ifa);
658 break;
659 #endif
660 #if NS
661 case AF_NS: {
662 register struct ns_addr * ina = &IA_SNS(ifa)->sns_addr;
663
664 if( ns_nullhost(*ina) )
665 ina->x_host =
666 *(union ns_host *) LLADDR(ifp->if_sadl);
667 else
668 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl),
669 ifp->if_addrlen);
670
671 epic_stop(sc);
672 epic_init(sc);
673 break;
674 }
675 #endif
676 default:
677 epic_stop(sc);
678 epic_init(sc);
679 break;
680 }
681 break;
682 }
683 #endif /* __FreeBSD__ */
684
685 case SIOCSIFFLAGS:
686 /*
687 * If the interface is marked up and stopped, then start it.
688 * If it is marked down and running, then stop it.
689 */
690 if (ifp->if_flags & IFF_UP) {
691 if ((ifp->if_flags & IFF_RUNNING) == 0) {
692 epic_init(sc);
693 break;
694 }
695 } else {
696 if (ifp->if_flags & IFF_RUNNING) {
697 epic_stop(sc);
698 break;
699 }
700 }
701
702 /* Handle IFF_PROMISC flag */
703 epic_stop_activity(sc);
704 epic_set_rx_mode(sc);
705 epic_start_activity(sc);
706 break;
707
708 case SIOCADDMULTI:
709 case SIOCDELMULTI:
710 /* Update out multicast list */
711 #if defined(__FreeBSD__) && __FreeBSD_version >= 300000
712 epic_set_mc_table(sc);
713 error = 0;
714 #else
715 error = (command == SIOCADDMULTI) ?
716 ether_addmulti((struct ifreq *)data, &sc->arpcom) :
717 ether_delmulti((struct ifreq *)data, &sc->arpcom);
718
719 if (error == ENETRESET) {
720 epic_set_mc_table(sc);
721 error = 0;
722 }
723 #endif
724 break;
725
726 case SIOCSIFMEDIA:
727 case SIOCGIFMEDIA:
728 mii = epic_mii_ptr(sc);
729 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
730 break;
731
732 default:
733 error = EINVAL;
734 }
735 splx(x);
736
737 return error;
738 }
739
740 /*
741 * OS-independed part of attach process. allocate memory for descriptors
742 * and frag lists, wake up chip, read MAC address and PHY identyfier.
743 * Return -1 on failure.
744 */
745 EPIC_STATIC int
epic_common_attach(sc)746 epic_common_attach(sc)
747 epic_softc_t *sc;
748 {
749 int i;
750 caddr_t pool;
751
752 i = sizeof(struct epic_frag_list)*TX_RING_SIZE +
753 sizeof(struct epic_rx_desc)*RX_RING_SIZE +
754 sizeof(struct epic_tx_desc)*TX_RING_SIZE + PAGE_SIZE;
755 sc->pool = (epic_softc_t *) malloc( i, M_DEVBUF, M_NOWAIT);
756
757 if (sc->pool == NULL) {
758 printf(": can't allocate memory for buffers\n");
759 return -1;
760 }
761 bzero(sc->pool, i);
762
763 /* Align pool on PAGE_SIZE */
764 pool = (caddr_t)sc->pool;
765 pool = (caddr_t)((u_int32_t)(pool + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1));
766
767 /* Distribute memory */
768 sc->tx_flist = (void *)pool;
769 pool += sizeof(struct epic_frag_list)*TX_RING_SIZE;
770 sc->rx_desc = (void *)pool;
771 pool += sizeof(struct epic_rx_desc)*RX_RING_SIZE;
772 sc->tx_desc = (void *)pool;
773
774 /* Bring the chip out of low-power mode. */
775 CSR_WRITE_4( sc, GENCTL, GENCTL_SOFT_RESET);
776 DELAY(500);
777
778 /* Workaround for Application Note 7-15 */
779 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
780
781 /* Read mac address from EEPROM */
782 for (i = 0; i < ETHER_ADDR_LEN / sizeof(u_int16_t); i++)
783 ((u_int16_t *)sc->sc_macaddr)[i] = epic_read_eeprom(sc,i);
784
785 /* Set defaults */
786 sc->tx_threshold = TRANSMIT_THRESHOLD;
787 sc->txcon = TXCON_DEFAULT;
788 sc->miicfg = MIICFG_SMI_ENABLE;
789 sc->phyid = EPIC_UNKN_PHY;
790 sc->serinst = -1;
791
792 if (sc->cardvend != SMC_VENDORID)
793 printf(EPIC_FORMAT ": unknown card vendor 0x%04x\n", EPIC_ARGS(sc), sc->cardvend);
794
795 return 0;
796 }
797
798 /*
799 * This is if_start handler. It takes mbufs from if_snd queue
800 * and queue them for transmit, one by one, until TX ring become full
801 * or queue become empty.
802 */
803 EPIC_STATIC void
epic_ifstart(ifp)804 epic_ifstart(ifp)
805 struct ifnet * ifp;
806 {
807 epic_softc_t *sc = ifp->if_softc;
808 struct epic_tx_buffer *buf;
809 struct epic_tx_desc *desc;
810 struct epic_frag_list *flist;
811 struct mbuf *m0;
812 register struct mbuf *m;
813 register int i;
814
815 while( sc->pending_txs < TX_RING_SIZE ){
816 buf = sc->tx_buffer + sc->cur_tx;
817 desc = sc->tx_desc + sc->cur_tx;
818 flist = sc->tx_flist + sc->cur_tx;
819
820 /* Get next packet to send */
821 IFQ_DEQUEUE( &ifp->if_snd, m0 );
822
823 /* If nothing to send, return */
824 if( NULL == m0 ) return;
825
826 /* Fill fragments list */
827 for( m=m0, i=0;
828 (NULL != m) && (i < EPIC_MAX_FRAGS);
829 m = m->m_next, i++ ) {
830 flist->frag[i].fraglen = m->m_len;
831 flist->frag[i].fragaddr = vtophys( mtod(m, caddr_t) );
832 }
833 flist->numfrags = i;
834
835 /* If packet was more than EPIC_MAX_FRAGS parts, */
836 /* recopy packet to new allocated mbuf cluster */
837 if( NULL != m ){
838 EPIC_MGETCLUSTER(m);
839 if( NULL == m ){
840 printf(EPIC_FORMAT ": cannot allocate mbuf cluster\n",EPIC_ARGS(sc));
841 m_freem(m0);
842 ifp->if_oerrors++;
843 continue;
844 }
845
846 m_copydata( m0, 0, m0->m_pkthdr.len, mtod(m,caddr_t) );
847 flist->frag[0].fraglen =
848 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
849 m->m_pkthdr.rcvif = ifp;
850
851 flist->numfrags = 1;
852 flist->frag[0].fragaddr = vtophys( mtod(m, caddr_t) );
853 m_freem(m0);
854 m0 = m;
855 }
856
857 buf->mbuf = m0;
858 sc->pending_txs++;
859 sc->cur_tx = ( sc->cur_tx + 1 ) & TX_RING_MASK;
860 desc->control = 0x01;
861 desc->txlength =
862 max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
863 desc->status = 0x8000;
864 CSR_WRITE_4( sc, COMMAND, COMMAND_TXQUEUED );
865
866 /* Set watchdog timer */
867 ifp->if_timer = 8;
868
869 #if NBPFILTER > 0
870 if( ifp->if_bpf )
871 bpf_mtap( EPIC_BPFTAP_ARG(ifp), m0 );
872 #endif
873 }
874
875 ifp->if_flags |= IFF_OACTIVE;
876
877 return;
878
879 }
880
881 /*
882 * Synopsis: Finish all received frames.
883 */
884 EPIC_STATIC void
epic_rx_done(sc)885 epic_rx_done(sc)
886 epic_softc_t *sc;
887 {
888 u_int16_t len;
889 struct epic_rx_buffer *buf;
890 struct epic_rx_desc *desc;
891 struct mbuf *m;
892
893 while( !(sc->rx_desc[sc->cur_rx].status & 0x8000) ) {
894 buf = sc->rx_buffer + sc->cur_rx;
895 desc = sc->rx_desc + sc->cur_rx;
896
897 /* Switch to next descriptor */
898 sc->cur_rx = (sc->cur_rx+1) & RX_RING_MASK;
899
900 /* Check for errors, this should happend */
901 /* only if SAVE_ERRORED_PACKETS is set, */
902 /* normaly rx errors generate RXE interrupt */
903 if( !(desc->status & 1) ) {
904 dprintf((EPIC_FORMAT ": Rx error status: 0x%x\n",EPIC_ARGS(sc),desc->status));
905 sc->sc_if.if_ierrors++;
906 desc->status = 0x8000;
907 continue;
908 }
909
910 /* Save packet length and mbuf contained packet */
911 len = desc->rxlength - ETHER_CRC_LEN;
912 m = buf->mbuf;
913
914 /* Try to get mbuf cluster */
915 EPIC_MGETCLUSTER( buf->mbuf );
916 if( NULL == buf->mbuf ) {
917 printf(EPIC_FORMAT ": cannot allocate mbuf cluster\n",EPIC_ARGS(sc));
918 buf->mbuf = m;
919 desc->status = 0x8000;
920 sc->sc_if.if_ierrors++;
921 continue;
922 }
923
924 /* Point to new mbuf, and give descriptor to chip */
925 desc->bufaddr = vtophys( mtod( buf->mbuf, caddr_t ) );
926 desc->status = 0x8000;
927
928 /*
929 * First mbuf in packet holds the ethernet and
930 * packet headers.
931 */
932 m->m_pkthdr.rcvif = &(sc->sc_if);
933 m->m_pkthdr.len = m->m_len = len;
934
935 #if !defined(__FreeBSD__)
936 #if NBPFILTER > 0
937 /* Give mbuf to BPFILTER */
938 if( sc->sc_if.if_bpf )
939 bpf_mtap( EPIC_BPFTAP_ARG(&sc->sc_if), m );
940 #endif /* NBPFILTER > 0 */
941 #endif /* !__FreeBSD__ */
942
943 /* Give mbuf to OS */
944 ether_input_mbuf(&sc->sc_if, m);
945
946 /* Successfuly received frame */
947 sc->sc_if.if_ipackets++;
948 }
949
950 return;
951 }
952
953 /*
954 * Synopsis: Do last phase of transmission. I.e. if desc is
955 * transmitted, decrease pending_txs counter, free mbuf contained
956 * packet, switch to next descriptor and repeat until no packets
957 * are pending or descriptor is not transmitted yet.
958 */
959 EPIC_STATIC void
epic_tx_done(sc)960 epic_tx_done(sc)
961 epic_softc_t *sc;
962 {
963 struct epic_tx_buffer *buf;
964 struct epic_tx_desc *desc;
965 u_int16_t status;
966
967 while( sc->pending_txs > 0 ){
968 buf = sc->tx_buffer + sc->dirty_tx;
969 desc = sc->tx_desc + sc->dirty_tx;
970 status = desc->status;
971
972 /* If packet is not transmitted, thou followed */
973 /* packets are not transmitted too */
974 if( status & 0x8000 ) break;
975
976 /* Packet is transmitted. Switch to next and */
977 /* free mbuf */
978 sc->pending_txs--;
979 sc->dirty_tx = (sc->dirty_tx + 1) & TX_RING_MASK;
980 m_freem( buf->mbuf );
981 buf->mbuf = NULL;
982
983 /* Check for errors and collisions */
984 if( status & 0x0001 ) sc->sc_if.if_opackets++;
985 else sc->sc_if.if_oerrors++;
986 sc->sc_if.if_collisions += (status >> 8) & 0x1F;
987 #if defined(EPIC_DEBUG)
988 if( (status & 0x1001) == 0x1001 )
989 dprintf((EPIC_FORMAT ": frame not transmitted due collisions\n",EPIC_ARGS(sc)));
990 #endif
991 }
992
993 if( sc->pending_txs < TX_RING_SIZE )
994 sc->sc_if.if_flags &= ~IFF_OACTIVE;
995 }
996
997 /*
998 * Interrupt function
999 */
1000 EPIC_STATIC EPIC_INTR_RET_TYPE
epic_intr(arg)1001 epic_intr(arg)
1002 void *arg;
1003 {
1004 epic_softc_t * sc = (epic_softc_t *) arg;
1005 int status,i=4;
1006 #if defined(__OpenBSD__)
1007 int claimed = 0;
1008 #endif
1009
1010 while( i-- && ((status = CSR_READ_4(sc, INTSTAT)) & INTSTAT_INT_ACTV) ){
1011 #if defined(__OpenBSD__)
1012 claimed = 1;
1013 #endif
1014 CSR_WRITE_4( sc, INTSTAT, status );
1015
1016 if( status & (INTSTAT_RQE|INTSTAT_RCC|INTSTAT_OVW) ) {
1017 epic_rx_done( sc );
1018 if( status & (INTSTAT_RQE|INTSTAT_OVW) ){
1019 #if defined(EPIC_DEBUG)
1020 if( status & INTSTAT_OVW )
1021 printf(EPIC_FORMAT ": RX buffer overflow\n",EPIC_ARGS(sc));
1022 if( status & INTSTAT_RQE )
1023 printf(EPIC_FORMAT ": RX FIFO overflow\n",EPIC_ARGS(sc));
1024 #endif
1025 if( !(CSR_READ_4( sc, COMMAND ) & COMMAND_RXQUEUED) )
1026 CSR_WRITE_4( sc, COMMAND, COMMAND_RXQUEUED );
1027 sc->sc_if.if_ierrors++;
1028 }
1029 }
1030
1031 if( status & (INTSTAT_TXC|INTSTAT_TCC|INTSTAT_TQE) ) {
1032 epic_tx_done( sc );
1033 if(!(sc->sc_if.if_flags & IFF_OACTIVE) &&
1034 !IFQ_IS_EMPTY( &sc->sc_if.if_snd ))
1035 epic_ifstart( &sc->sc_if );
1036 }
1037
1038 /* Check for errors */
1039 if( status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
1040 INTSTAT_APE|INTSTAT_DPE|INTSTAT_TXU|INTSTAT_RXE) ){
1041 if( status & (INTSTAT_FATAL|INTSTAT_PMA|INTSTAT_PTA|
1042 INTSTAT_APE|INTSTAT_DPE) ){
1043 printf(EPIC_FORMAT ": PCI fatal error occurred (%s%s%s%s)\n",
1044 EPIC_ARGS(sc),
1045 (status&INTSTAT_PMA)?"PMA":"",
1046 (status&INTSTAT_PTA)?" PTA":"",
1047 (status&INTSTAT_APE)?" APE":"",
1048 (status&INTSTAT_DPE)?" DPE":""
1049 );
1050
1051 epic_stop(sc);
1052 epic_init(sc);
1053
1054 break;
1055 }
1056
1057 if (status & INTSTAT_RXE) {
1058 dprintf((EPIC_FORMAT ": CRC/Alignment error\n",EPIC_ARGS(sc)));
1059 sc->sc_if.if_ierrors++;
1060 }
1061
1062 /* Tx FIFO underflow. Increase tx threshold, */
1063 /* if it grown above 2048, disable EARLY_TX */
1064 if (status & INTSTAT_TXU) {
1065 if( sc->tx_threshold > 0x800 ) {
1066 sc->txcon &= ~TXCON_EARLY_TRANSMIT_ENABLE;
1067 dprintf((EPIC_FORMAT ": TX underrun error, early tx disabled\n",EPIC_ARGS(sc)));
1068 } else {
1069 sc->tx_threshold += 0x40;
1070 dprintf((EPIC_FORMAT ": TX underrun error, tx threshold increased to %d\n",EPIC_ARGS(sc),sc->tx_threshold));
1071 }
1072
1073 CSR_WRITE_4(sc, COMMAND, COMMAND_TXUGO | COMMAND_TXQUEUED);
1074 epic_stop_activity(sc);
1075 epic_set_tx_mode(sc);
1076 epic_start_activity(sc);
1077 sc->sc_if.if_oerrors++;
1078 }
1079 }
1080 }
1081
1082 /* If no packets are pending, thus no timeouts */
1083 if( sc->pending_txs == 0 ) sc->sc_if.if_timer = 0;
1084
1085 #if defined(__OpenBSD__)
1086 return claimed;
1087 #endif
1088 }
1089
1090 /*
1091 * Synopsis: This one is called if packets wasn't transmitted
1092 * during timeout. Try to deallocate transmitted packets, and
1093 * if success continue to work.
1094 */
1095 EPIC_STATIC void
epic_ifwatchdog(ifp)1096 epic_ifwatchdog(ifp)
1097 struct ifnet *ifp;
1098 {
1099 epic_softc_t *sc = ifp->if_softc;
1100 int x;
1101
1102 x = splimp();
1103
1104 printf(EPIC_FORMAT ": device timeout %d packets, ",
1105 EPIC_ARGS(sc),sc->pending_txs);
1106
1107 /* Try to finish queued packets */
1108 epic_tx_done( sc );
1109
1110 /* If not successful */
1111 if( sc->pending_txs > 0 ){
1112
1113 ifp->if_oerrors+=sc->pending_txs;
1114
1115 /* Reinitialize board */
1116 printf("reinitialization\n");
1117 epic_stop(sc);
1118 epic_init(sc);
1119
1120 } else
1121 printf("seems we can continue normally\n");
1122
1123 /* Start output */
1124 if( !IFQ_IS_EMPTY( &ifp->if_snd ) ) epic_ifstart( ifp );
1125
1126 splx(x);
1127 }
1128
1129 /*
1130 * Set media options.
1131 */
1132 EPIC_STATIC int
epic_ifmedia_upd(ifp)1133 epic_ifmedia_upd(ifp)
1134 struct ifnet *ifp;
1135 {
1136 epic_softc_t *sc;
1137 struct mii_data *mii;
1138 struct ifmedia *ifm;
1139 struct mii_softc *miisc;
1140 int cfg, media;
1141
1142 sc = ifp->if_softc;
1143
1144 mii = epic_mii_ptr(sc);
1145
1146 ifm = &mii->mii_media;
1147 media = ifm->ifm_cur->ifm_media;
1148
1149 /* Do not do anything if interface is not up */
1150 if(!(ifp->if_flags & IFF_UP))
1151 return (0);
1152
1153 /*
1154 * Lookup current selected PHY
1155 */
1156 if (IFM_INST(media) == sc->serinst) {
1157 sc->phyid = EPIC_SERIAL;
1158 sc->physc = NULL;
1159 } else {
1160 /* If we're not selecting serial interface, select MII mode */
1161 sc->miicfg &= ~MIICFG_SERIAL_ENABLE;
1162 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1163
1164 dprintf((EPIC_FORMAT ": MII selected\n", EPIC_ARGS(sc)));
1165
1166 /* Default to unknown PHY */
1167 sc->phyid = EPIC_UNKN_PHY;
1168
1169 /* Lookup selected PHY */
1170 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1171 miisc = LIST_NEXT(miisc, mii_list)) {
1172 if (IFM_INST(media) == miisc->mii_inst) {
1173 sc->physc = miisc;
1174 break;
1175 }
1176 }
1177
1178 /* Identify selected PHY */
1179 if (sc->physc) {
1180 int id1, id2, model, oui;
1181
1182 id1 = PHY_READ(sc->physc, MII_PHYIDR1);
1183 id2 = PHY_READ(sc->physc, MII_PHYIDR2);
1184
1185 oui = MII_OUI(id1, id2);
1186 model = MII_MODEL(id2);
1187 switch (oui) {
1188 case MII_OUI_QUALITYSEMI:
1189 if (model == MII_MODEL_QUALITYSEMI_QS6612)
1190 sc->phyid = EPIC_QS6612_PHY;
1191 break;
1192 case MII_OUI_xxALTIMA:
1193 if (model == MII_MODEL_xxALTIMA_AC101)
1194 sc->phyid = EPIC_AC101_PHY;
1195 break;
1196 case MII_OUI_xxLEVEL1:
1197 if (model == MII_MODEL_xxLEVEL1_LXT970)
1198 sc->phyid = EPIC_LXT970_PHY;
1199 break;
1200 }
1201 }
1202 }
1203
1204 /*
1205 * Do PHY specific card setup
1206 */
1207
1208 /* Call this, to isolate all not selected PHYs and
1209 * set up selected
1210 */
1211 mii_mediachg(mii);
1212
1213 /* Do our own setup */
1214 switch (sc->phyid) {
1215 case EPIC_QS6612_PHY:
1216 break;
1217 case EPIC_AC101_PHY:
1218 /* We have to powerup fiber transceivers */
1219 if (IFM_SUBTYPE(media) == IFM_100_FX)
1220 sc->miicfg |= MIICFG_694_ENABLE;
1221 else
1222 sc->miicfg &= ~MIICFG_694_ENABLE;
1223 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1224
1225 break;
1226 case EPIC_LXT970_PHY:
1227 /* We have to powerup fiber transceivers */
1228 cfg = PHY_READ(sc->physc, MII_LXTPHY_CONFIG);
1229 if (IFM_SUBTYPE(media) == IFM_100_FX)
1230 cfg |= CONFIG_LEDC1 | CONFIG_LEDC0;
1231 else
1232 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1233 PHY_WRITE(sc->physc, MII_LXTPHY_CONFIG, cfg);
1234
1235 break;
1236 case EPIC_SERIAL:
1237 /* Select serial PHY, (10base2/BNC usually) */
1238 sc->miicfg |= MIICFG_694_ENABLE | MIICFG_SERIAL_ENABLE;
1239 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1240
1241 /* There is no driver to fill this */
1242 mii->mii_media_active = media;
1243 mii->mii_media_status = 0;
1244
1245 /* We need to call this manualy as i wasn't called
1246 * in mii_mediachg()
1247 */
1248 epic_miibus_statchg(&sc->dev);
1249
1250 dprintf((EPIC_FORMAT ": SERIAL selected\n", EPIC_ARGS(sc)));
1251
1252 break;
1253 default:
1254 printf(EPIC_FORMAT ": ERROR! Unknown PHY selected\n", EPIC_ARGS(sc));
1255 return (EINVAL);
1256 }
1257
1258 return(0);
1259 }
1260
1261 /*
1262 * Report current media status.
1263 */
1264 EPIC_STATIC void
epic_ifmedia_sts(ifp,ifmr)1265 epic_ifmedia_sts(ifp, ifmr)
1266 struct ifnet *ifp;
1267 struct ifmediareq *ifmr;
1268 {
1269 epic_softc_t *sc;
1270 struct mii_data *mii;
1271 struct ifmedia *ifm;
1272
1273 sc = ifp->if_softc;
1274 mii = epic_mii_ptr(sc);
1275 ifm = &mii->mii_media;
1276
1277 /* Nothing should be selected if interface is down */
1278 if(!(ifp->if_flags & IFF_UP)) {
1279 ifmr->ifm_active = IFM_NONE;
1280 ifmr->ifm_status = 0;
1281
1282 return;
1283 }
1284
1285 /* Call underlying pollstat, if not serial PHY */
1286 if (sc->phyid != EPIC_SERIAL)
1287 mii_pollstat(mii);
1288
1289 /* Simply copy media info */
1290 ifmr->ifm_active = mii->mii_media_active;
1291 ifmr->ifm_status = mii->mii_media_status;
1292
1293 return;
1294 }
1295
1296 /*
1297 * Callback routine, called on media change.
1298 */
1299 EPIC_STATIC void
epic_miibus_statchg(dev)1300 epic_miibus_statchg(dev)
1301 struct device* dev;
1302 {
1303 epic_softc_t *sc;
1304 struct mii_data *mii;
1305 int media;
1306
1307 sc = epic_dev_ptr(dev);
1308 mii = epic_mii_ptr(sc);
1309 media = mii->mii_media_active;
1310
1311 sc->txcon &= ~(TXCON_LOOPBACK_MODE | TXCON_FULL_DUPLEX);
1312
1313 /* If we are in full-duplex mode or loopback operation,
1314 * we need to decouple receiver and transmitter.
1315 */
1316 if (IFM_OPTIONS(media) & (IFM_FDX | IFM_LOOP))
1317 sc->txcon |= TXCON_FULL_DUPLEX;
1318
1319 /* On some cards we need manualy set fullduplex led */
1320 if (sc->cardid == SMC9432FTX ||
1321 sc->cardid == SMC9432FTX_SC) {
1322 if (IFM_OPTIONS(media) & IFM_FDX)
1323 sc->miicfg |= MIICFG_694_ENABLE;
1324 else
1325 sc->miicfg &= ~MIICFG_694_ENABLE;
1326
1327 CSR_WRITE_4(sc, MIICFG, sc->miicfg);
1328 }
1329
1330 /* Update baudrate */
1331 if (IFM_SUBTYPE(media) == IFM_100_TX ||
1332 IFM_SUBTYPE(media) == IFM_100_FX)
1333 sc->sc_if.if_baudrate = 100000000;
1334 else
1335 sc->sc_if.if_baudrate = 10000000;
1336
1337 epic_set_tx_mode(sc);
1338
1339 return;
1340 }
1341
epic_miibus_mediainit(dev)1342 EPIC_STATIC void epic_miibus_mediainit(dev)
1343 struct device* dev;
1344 {
1345 epic_softc_t *sc;
1346 struct mii_data *mii;
1347 struct ifmedia *ifm;
1348 int media;
1349
1350 sc = epic_dev_ptr(dev);
1351 mii = epic_mii_ptr(sc);
1352 ifm = &mii->mii_media;
1353
1354 /* Add Serial Media Interface if present, this applies to
1355 * SMC9432BTX serie
1356 */
1357 if(CSR_READ_4(sc, MIICFG) & MIICFG_PHY_PRESENT) {
1358 /* Store its instance */
1359 sc->serinst = mii->mii_instance++;
1360
1361 /* Add as 10base2/BNC media */
1362 media = IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->serinst);
1363 ifmedia_add(ifm, media, 0, NULL);
1364
1365 /* Report to user */
1366 printf(EPIC_FORMAT ": serial PHY detected (10Base2/BNC)\n",EPIC_ARGS(sc));
1367 }
1368
1369 return;
1370 }
1371
1372
1373 /*
1374 * Reset chip, allocate rings, and update media.
1375 */
1376 EPIC_STATIC int
epic_init(sc)1377 epic_init(sc)
1378 epic_softc_t *sc;
1379 {
1380 struct ifnet *ifp = &sc->sc_if;
1381 struct mii_data *mii;
1382 int s,i;
1383
1384 s = splimp();
1385
1386 /* If interface is already running, then we need not do anything */
1387 if (ifp->if_flags & IFF_RUNNING) {
1388 splx(s);
1389 return 0;
1390 }
1391
1392 /* Soft reset the chip (we have to power up card before) */
1393 CSR_WRITE_4( sc, GENCTL, 0 );
1394 CSR_WRITE_4( sc, GENCTL, GENCTL_SOFT_RESET );
1395
1396 /*
1397 * Reset takes 15 pci ticks which depends on PCI bus speed.
1398 * Assuming it >= 33000000 hz, we have wait at least 495e-6 sec.
1399 */
1400 DELAY(500);
1401
1402 /* Wake up */
1403 CSR_WRITE_4( sc, GENCTL, 0 );
1404
1405 /* Workaround for Application Note 7-15 */
1406 for (i=0; i<16; i++) CSR_WRITE_4(sc, TEST1, TEST1_CLOCK_TEST);
1407
1408 /* Initialize rings */
1409 if( epic_init_rings( sc ) ) {
1410 printf(EPIC_FORMAT ": failed to init rings\n",EPIC_ARGS(sc));
1411 splx(s);
1412 return -1;
1413 }
1414
1415 /* Give rings to EPIC */
1416 CSR_WRITE_4( sc, PRCDAR, vtophys( sc->rx_desc ) );
1417 CSR_WRITE_4( sc, PTCDAR, vtophys( sc->tx_desc ) );
1418
1419 /* Put node address to EPIC */
1420 CSR_WRITE_4( sc, LAN0, ((u_int16_t *)sc->sc_macaddr)[0] );
1421 CSR_WRITE_4( sc, LAN1, ((u_int16_t *)sc->sc_macaddr)[1] );
1422 CSR_WRITE_4( sc, LAN2, ((u_int16_t *)sc->sc_macaddr)[2] );
1423
1424 /* Set tx mode, includeing transmit threshold */
1425 epic_set_tx_mode(sc);
1426
1427 /* Compute and set RXCON. */
1428 epic_set_rx_mode( sc );
1429
1430 /* Set multicast table */
1431 epic_set_mc_table( sc );
1432
1433 /* Enable interrupts by setting the interrupt mask. */
1434 CSR_WRITE_4( sc, INTMASK,
1435 INTSTAT_RCC | /* INTSTAT_RQE | INTSTAT_OVW | INTSTAT_RXE | */
1436 /* INTSTAT_TXC | */ INTSTAT_TCC | INTSTAT_TQE | INTSTAT_TXU |
1437 INTSTAT_FATAL);
1438
1439 /* Acknowledge all pending interrupts */
1440 CSR_WRITE_4(sc, INTSTAT, CSR_READ_4(sc, INTSTAT));
1441
1442 /* Enable interrupts, set for PCI read multiple and etc */
1443 CSR_WRITE_4( sc, GENCTL,
1444 GENCTL_ENABLE_INTERRUPT | GENCTL_MEMORY_READ_MULTIPLE |
1445 GENCTL_ONECOPY | GENCTL_RECEIVE_FIFO_THRESHOLD64 );
1446
1447 /* Mark interface running ... */
1448 if( ifp->if_flags & IFF_UP ) ifp->if_flags |= IFF_RUNNING;
1449 else ifp->if_flags &= ~IFF_RUNNING;
1450
1451 /* ... and free */
1452 ifp->if_flags &= ~IFF_OACTIVE;
1453
1454 /* Start Rx process */
1455 epic_start_activity(sc);
1456
1457 /* Reset all PHYs */
1458 mii = epic_mii_ptr(sc);
1459 if (mii->mii_instance) {
1460 struct mii_softc *miisc;
1461 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1462 mii_phy_reset(miisc);
1463 }
1464
1465 /* Set appropriate media */
1466 epic_ifmedia_upd(ifp);
1467
1468 splx(s);
1469
1470 timeout_add(&sc->sc_tmo, hz);
1471
1472 return 0;
1473 }
1474
1475 /*
1476 * Synopsis: calculate and set Rx mode. Chip must be in idle state to
1477 * access RXCON.
1478 */
1479 EPIC_STATIC void
epic_set_rx_mode(sc)1480 epic_set_rx_mode(sc)
1481 epic_softc_t *sc;
1482 {
1483 u_int32_t flags = sc->sc_if.if_flags;
1484 u_int32_t rxcon = RXCON_DEFAULT;
1485
1486 rxcon |= (flags & IFF_PROMISC) ? RXCON_PROMISCUOUS_MODE : 0;
1487
1488 CSR_WRITE_4( sc, RXCON, rxcon );
1489
1490 return;
1491 }
1492
1493 /*
1494 * Synopsis: Set transmit control register. Chip must be in idle state to
1495 * access TXCON.
1496 */
1497 EPIC_STATIC void
epic_set_tx_mode(sc)1498 epic_set_tx_mode(sc)
1499 epic_softc_t *sc;
1500 {
1501 if (sc->txcon & TXCON_EARLY_TRANSMIT_ENABLE)
1502 CSR_WRITE_4 (sc, ETXTHR, sc->tx_threshold);
1503
1504 CSR_WRITE_4 (sc, TXCON, sc->txcon);
1505 }
1506
1507 /*
1508 * Synopsis: This function should update multicast hash table.
1509 * I suppose there is a bug in chips MC filter so this function
1510 * only set it to receive all MC packets. The second problem is
1511 * that we should wait for TX and RX processes to stop before
1512 * reprogramming MC filter. The epic_stop_activity() and
1513 * epic_start_activity() should help to do this.
1514 */
1515 EPIC_STATIC void
epic_set_mc_table(sc)1516 epic_set_mc_table(sc)
1517 epic_softc_t *sc;
1518 {
1519 struct ifnet *ifp = &sc->sc_if;
1520
1521 if( ifp->if_flags & IFF_MULTICAST ){
1522 CSR_WRITE_4( sc, MC0, 0xFFFF );
1523 CSR_WRITE_4( sc, MC1, 0xFFFF );
1524 CSR_WRITE_4( sc, MC2, 0xFFFF );
1525 CSR_WRITE_4( sc, MC3, 0xFFFF );
1526 }
1527
1528 return;
1529 }
1530
1531
1532 /*
1533 * Synopsis: Start receive process and transmit one, if they need.
1534 */
1535 EPIC_STATIC void
epic_start_activity(sc)1536 epic_start_activity(sc)
1537 epic_softc_t *sc;
1538 {
1539 /* Start rx process */
1540 CSR_WRITE_4(sc, COMMAND,
1541 COMMAND_RXQUEUED | COMMAND_START_RX |
1542 (sc->pending_txs?COMMAND_TXQUEUED:0));
1543 dprintf((EPIC_FORMAT ": activity started\n",EPIC_ARGS(sc)));
1544 }
1545
1546 /*
1547 * Synopsis: Completely stop Rx and Tx processes. If TQE is set additional
1548 * packet needs to be queued to stop Tx DMA.
1549 */
1550 EPIC_STATIC void
epic_stop_activity(sc)1551 epic_stop_activity(sc)
1552 epic_softc_t *sc;
1553 {
1554 int i;
1555
1556 /* Stop Tx and Rx DMA */
1557 CSR_WRITE_4(sc,COMMAND,COMMAND_STOP_RX|COMMAND_STOP_RDMA|COMMAND_STOP_TDMA);
1558
1559 /* Wait Rx and Tx DMA to stop (why 1 ms ??? XXX) */
1560 dprintf((EPIC_FORMAT ": waiting Rx and Tx DMA to stop\n",EPIC_ARGS(sc)));
1561 for(i=0;i<0x1000;i++) {
1562 if((CSR_READ_4(sc,INTSTAT) & (INTSTAT_TXIDLE | INTSTAT_RXIDLE)) ==
1563 (INTSTAT_TXIDLE | INTSTAT_RXIDLE) )
1564 break;
1565 DELAY(1);
1566 }
1567
1568 if( !(CSR_READ_4(sc,INTSTAT)&INTSTAT_RXIDLE) )
1569 printf(EPIC_FORMAT ": can't stop Rx DMA\n",EPIC_ARGS(sc));
1570
1571 if( !(CSR_READ_4(sc,INTSTAT)&INTSTAT_TXIDLE) )
1572 printf(EPIC_FORMAT ": can't stop Tx DMA\n",EPIC_ARGS(sc));
1573
1574 /* Catch all finished packets */
1575 epic_rx_done(sc);
1576 epic_tx_done(sc);
1577
1578 /*
1579 * May need to queue one more packet if TQE, this is rare but existing
1580 * case.
1581 */
1582 if( (CSR_READ_4( sc, INTSTAT ) & INTSTAT_TQE) &&
1583 !(CSR_READ_4( sc, INTSTAT ) & INTSTAT_TXIDLE) ) {
1584 struct epic_tx_desc *desc;
1585 struct epic_frag_list *flist;
1586 struct epic_tx_buffer *buf;
1587 struct mbuf *m0;
1588
1589 dprintf((EPIC_FORMAT ": queue last packet\n",EPIC_ARGS(sc)));
1590
1591 desc = sc->tx_desc + sc->cur_tx;
1592 flist = sc->tx_flist + sc->cur_tx;
1593 buf = sc->tx_buffer + sc->cur_tx;
1594
1595 if ((desc->status & 0x8000) || (buf->mbuf != NULL))
1596 return;
1597
1598 MGETHDR(m0,M_DONTWAIT,MT_DATA);
1599 if (NULL == m0)
1600 return;
1601
1602 /* Prepare mbuf */
1603 m0->m_len = min(MHLEN,ETHER_MIN_LEN-ETHER_CRC_LEN);
1604 flist->frag[0].fraglen = m0->m_len;
1605 m0->m_pkthdr.len = m0->m_len;
1606 m0->m_pkthdr.rcvif = &sc->sc_if;
1607 bzero(mtod(m0,caddr_t),m0->m_len);
1608
1609 /* Fill fragments list */
1610 flist->frag[0].fraglen = m0->m_len;
1611 flist->frag[0].fragaddr = vtophys( mtod(m0, caddr_t) );
1612 flist->numfrags = 1;
1613
1614 /* Fill in descriptor */
1615 buf->mbuf = m0;
1616 sc->pending_txs++;
1617 sc->cur_tx = (sc->cur_tx + 1) & TX_RING_MASK;
1618 desc->control = 0x01;
1619 desc->txlength = max(m0->m_pkthdr.len,ETHER_MIN_LEN-ETHER_CRC_LEN);
1620 desc->status = 0x8000;
1621
1622 /* Launch transmition */
1623 CSR_WRITE_4(sc, COMMAND, COMMAND_STOP_TDMA | COMMAND_TXQUEUED);
1624
1625 /* Wait Tx DMA to stop (for how long??? XXX) */
1626 dprintf((EPIC_FORMAT ": waiting Tx DMA to stop\n",EPIC_ARGS(sc)));
1627 for(i=0;i<1000;i++) {
1628 if( (CSR_READ_4(sc,INTSTAT)&INTSTAT_TXIDLE) == INTSTAT_TXIDLE )
1629 break;
1630 DELAY(1);
1631 }
1632
1633 if( !(CSR_READ_4(sc,INTSTAT)&INTSTAT_TXIDLE) )
1634 printf(EPIC_FORMAT ": can't stop TX DMA\n",EPIC_ARGS(sc));
1635 else
1636 epic_tx_done(sc);
1637 }
1638
1639 dprintf((EPIC_FORMAT ": activity stoped\n",EPIC_ARGS(sc)));
1640 }
1641
1642 /*
1643 * Synopsis: Shut down board and deallocates rings.
1644 */
1645 EPIC_STATIC void
epic_stop(sc)1646 epic_stop(sc)
1647 epic_softc_t *sc;
1648 {
1649 int s;
1650
1651 timeout_del(&sc->sc_tmo);
1652
1653 s = splimp();
1654
1655 sc->sc_if.if_timer = 0;
1656
1657 /* Disable interrupts */
1658 CSR_WRITE_4( sc, INTMASK, 0 );
1659 CSR_WRITE_4( sc, GENCTL, 0 );
1660
1661 /* Try to stop Rx and TX processes */
1662 epic_stop_activity(sc);
1663
1664 /* Reset chip */
1665 CSR_WRITE_4( sc, GENCTL, GENCTL_SOFT_RESET );
1666 DELAY(1000);
1667
1668 /* Make chip go to bed */
1669 CSR_WRITE_4(sc, GENCTL, GENCTL_POWER_DOWN);
1670
1671 /* Free memory allocated for rings */
1672 epic_free_rings(sc);
1673
1674 /* Mark as stoped */
1675 sc->sc_if.if_flags &= ~IFF_RUNNING;
1676
1677 splx(s);
1678 return;
1679 }
1680
1681 /*
1682 * Synopsis: This function should free all memory allocated for rings.
1683 */
1684 EPIC_STATIC void
epic_free_rings(sc)1685 epic_free_rings(sc)
1686 epic_softc_t *sc;
1687 {
1688 int i;
1689
1690 for(i=0;i<RX_RING_SIZE;i++){
1691 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1692 struct epic_rx_desc *desc = sc->rx_desc + i;
1693
1694 desc->status = 0;
1695 desc->buflength = 0;
1696 desc->bufaddr = 0;
1697
1698 if( buf->mbuf ) m_freem( buf->mbuf );
1699 buf->mbuf = NULL;
1700 }
1701
1702 for(i=0;i<TX_RING_SIZE;i++){
1703 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1704 struct epic_tx_desc *desc = sc->tx_desc + i;
1705
1706 desc->status = 0;
1707 desc->buflength = 0;
1708 desc->bufaddr = 0;
1709
1710 if( buf->mbuf ) m_freem( buf->mbuf );
1711 buf->mbuf = NULL;
1712 }
1713 }
1714
1715 /*
1716 * Synopsis: Allocates mbufs for Rx ring and point Rx descs to them.
1717 * Point Tx descs to fragment lists. Check that all descs and fraglists
1718 * are bounded and aligned properly.
1719 */
1720 EPIC_STATIC int
epic_init_rings(sc)1721 epic_init_rings(sc)
1722 epic_softc_t *sc;
1723 {
1724 int i;
1725
1726 sc->cur_rx = sc->cur_tx = sc->dirty_tx = sc->pending_txs = 0;
1727
1728 for (i = 0; i < RX_RING_SIZE; i++) {
1729 struct epic_rx_buffer *buf = sc->rx_buffer + i;
1730 struct epic_rx_desc *desc = sc->rx_desc + i;
1731
1732 desc->status = 0; /* Owned by driver */
1733 desc->next = vtophys( sc->rx_desc + ((i+1) & RX_RING_MASK) );
1734
1735 if( (desc->next & 3) || ((desc->next & 0xFFF) + sizeof(struct epic_rx_desc) > 0x1000 ) )
1736 printf(EPIC_FORMAT ": WARNING! rx_desc is misbound or misaligned\n",EPIC_ARGS(sc));
1737
1738 EPIC_MGETCLUSTER( buf->mbuf );
1739 if( NULL == buf->mbuf ) {
1740 epic_free_rings(sc);
1741 return -1;
1742 }
1743 desc->bufaddr = vtophys( mtod(buf->mbuf,caddr_t) );
1744
1745 desc->buflength = ETHER_MAX_FRAME_LEN;
1746 desc->status = 0x8000; /* Give to EPIC */
1747
1748 }
1749
1750 for (i = 0; i < TX_RING_SIZE; i++) {
1751 struct epic_tx_buffer *buf = sc->tx_buffer + i;
1752 struct epic_tx_desc *desc = sc->tx_desc + i;
1753
1754 desc->status = 0;
1755 desc->next = vtophys( sc->tx_desc + ( (i+1) & TX_RING_MASK ) );
1756
1757 if( (desc->next & 3) || ((desc->next & 0xFFF) + sizeof(struct epic_tx_desc) > 0x1000 ) )
1758 printf(EPIC_FORMAT ": WARNING! tx_desc is misbound or misaligned\n",EPIC_ARGS(sc));
1759
1760 buf->mbuf = NULL;
1761 desc->bufaddr = vtophys( sc->tx_flist + i );
1762 if( (desc->bufaddr & 3) || ((desc->bufaddr & 0xFFF) + sizeof(struct epic_frag_list) > 0x1000 ) )
1763 printf(EPIC_FORMAT ": WARNING! frag_list is misbound or misaligned\n",EPIC_ARGS(sc));
1764 }
1765
1766 return 0;
1767 }
1768
1769 /*
1770 * EEPROM operation functions
1771 */
1772 EPIC_STATIC void
epic_write_eepromreg(sc,val)1773 epic_write_eepromreg(sc, val)
1774 epic_softc_t *sc;
1775 u_int8_t val;
1776 {
1777 u_int16_t i;
1778
1779 CSR_WRITE_1( sc, EECTL, val );
1780
1781 for (i=0; i<0xFF; i++)
1782 if( !(CSR_READ_1( sc, EECTL ) & 0x20) ) break;
1783
1784 return;
1785 }
1786
1787 EPIC_STATIC u_int8_t
epic_read_eepromreg(sc)1788 epic_read_eepromreg(sc)
1789 epic_softc_t *sc;
1790 {
1791 return CSR_READ_1(sc, EECTL);
1792 }
1793
1794 EPIC_STATIC u_int8_t
epic_eeprom_clock(sc,val)1795 epic_eeprom_clock(sc, val)
1796 epic_softc_t *sc;
1797 u_int8_t val;
1798 {
1799 epic_write_eepromreg( sc, val );
1800 epic_write_eepromreg( sc, (val | 0x4) );
1801 epic_write_eepromreg( sc, val );
1802
1803 return epic_read_eepromreg( sc );
1804 }
1805
1806 EPIC_STATIC void
epic_output_eepromw(sc,val)1807 epic_output_eepromw(sc, val)
1808 epic_softc_t *sc;
1809 u_int16_t val;
1810 {
1811 int i;
1812 for( i = 0xF; i >= 0; i--){
1813 if( (val & (1 << i)) ) epic_eeprom_clock( sc, 0x0B );
1814 else epic_eeprom_clock( sc, 3);
1815 }
1816 }
1817
1818 EPIC_STATIC u_int16_t
epic_input_eepromw(sc)1819 epic_input_eepromw(sc)
1820 epic_softc_t *sc;
1821 {
1822 int i;
1823 int tmp;
1824 u_int16_t retval = 0;
1825
1826 for( i = 0xF; i >= 0; i--) {
1827 tmp = epic_eeprom_clock( sc, 0x3 );
1828 if( tmp & 0x10 ){
1829 retval |= (1 << i);
1830 }
1831 }
1832 return retval;
1833 }
1834
1835 EPIC_STATIC int
epic_read_eeprom(sc,loc)1836 epic_read_eeprom(sc, loc)
1837 epic_softc_t *sc;
1838 u_int16_t loc;
1839 {
1840 u_int16_t dataval;
1841 u_int16_t read_cmd;
1842
1843 epic_write_eepromreg( sc , 3);
1844
1845 if( epic_read_eepromreg( sc ) & 0x40 )
1846 read_cmd = ( loc & 0x3F ) | 0x180;
1847 else
1848 read_cmd = ( loc & 0xFF ) | 0x600;
1849
1850 epic_output_eepromw( sc, read_cmd );
1851
1852 dataval = epic_input_eepromw( sc );
1853
1854 epic_write_eepromreg( sc, 1 );
1855
1856 return dataval;
1857 }
1858
1859 /*
1860 * Here goes MII read/write routines
1861 */
1862 EPIC_STATIC int
epic_read_phy_reg(sc,phy,reg)1863 epic_read_phy_reg(sc, phy, reg)
1864 epic_softc_t *sc;
1865 int phy, reg;
1866 {
1867 int i;
1868
1869 CSR_WRITE_4 (sc, MIICTL, ((reg << 4) | (phy << 9) | 0x01));
1870
1871 for (i=0;i<0x100;i++) {
1872 if( !(CSR_READ_4(sc, MIICTL) & 0x01) ) break;
1873 DELAY(1);
1874 }
1875
1876 return (CSR_READ_4 (sc, MIIDATA));
1877 }
1878
1879 EPIC_STATIC void
epic_write_phy_reg(sc,phy,reg,val)1880 epic_write_phy_reg(sc, phy, reg, val)
1881 epic_softc_t *sc;
1882 int phy, reg, val;
1883 {
1884 int i;
1885
1886 CSR_WRITE_4 (sc, MIIDATA, val);
1887 CSR_WRITE_4 (sc, MIICTL, ((reg << 4) | (phy << 9) | 0x02));
1888
1889 for(i=0;i<0x100;i++) {
1890 if( !(CSR_READ_4(sc, MIICTL) & 0x02) ) break;
1891 DELAY(1);
1892 }
1893
1894 return;
1895 }
1896
1897 EPIC_STATIC int
epic_miibus_readreg(dev,phy,reg)1898 epic_miibus_readreg(dev, phy, reg)
1899 struct device* dev;
1900 int phy, reg;
1901 {
1902 epic_softc_t *sc;
1903
1904 sc = epic_dev_ptr(dev);
1905
1906 return (PHY_READ_2(sc, phy, reg));
1907 }
1908
1909 EPIC_STATIC EPIC_MIIBUS_WRITEREG_RET_TYPE
epic_miibus_writereg(dev,phy,reg,data)1910 epic_miibus_writereg(dev, phy, reg, data)
1911 struct device* dev;
1912 int phy, reg, data;
1913 {
1914 epic_softc_t *sc;
1915
1916 sc = epic_dev_ptr(dev);
1917
1918 PHY_WRITE_2(sc, phy, reg, data);
1919
1920 #if !defined(__OpenBSD__)
1921 return (0);
1922 #endif
1923 }
1924
1925 EPIC_STATIC void
epic_tick(vsc)1926 epic_tick(vsc)
1927 void *vsc;
1928 {
1929 epic_softc_t *sc = vsc;
1930 struct mii_data *mii;
1931
1932 mii = epic_mii_ptr(sc);
1933 if (sc->phyid != EPIC_SERIAL)
1934 mii_tick(mii);
1935 }
1936