1 /**************************************************************************
2
3 Copyright (c) 2001-2003, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32 ***************************************************************************/
33
34 /*$FreeBSD: if_em.c,v 1.38 2004/03/17 17:50:31 njl Exp $*/
35 /* $OpenBSD: if_em.c,v 1.21 2004/05/04 06:00:51 henric Exp $ */
36
37 #include "bpfilter.h"
38 #include "vlan.h"
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sockio.h>
43 #include <sys/mbuf.h>
44 #include <sys/malloc.h>
45 #include <sys/kernel.h>
46 #include <sys/device.h>
47 #include <sys/socket.h>
48
49 #include <net/if.h>
50 #include <net/if_dl.h>
51 #include <net/if_media.h>
52
53 #ifdef INET
54 #include <netinet/in.h>
55 #include <netinet/in_systm.h>
56 #include <netinet/in_var.h>
57 #include <netinet/ip.h>
58 #include <netinet/if_ether.h>
59 #endif
60
61 #if NVLAN > 0
62 #include <net/if_types.h>
63 #include <net/if_vlan_var.h>
64 #endif
65
66 #if NBPFILTER > 0
67 #include <net/bpf.h>
68 #endif
69
70 #include <uvm/uvm_extern.h>
71
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
74 #include <dev/pci/pcidevs.h>
75
76 #include <dev/pci/if_em.h>
77
78 /*********************************************************************
79 * Set this to one to display debug statistics
80 *********************************************************************/
81 int em_display_debug_stats = 0;
82
83 /*********************************************************************
84 * Linked list of board private structures for all NICs found
85 *********************************************************************/
86
87 struct em_softc *em_adapter_list = NULL;
88
89
90 /*********************************************************************
91 * Driver version
92 *********************************************************************/
93
94 char em_driver_version[] = "1.7.25";
95
96 #ifdef __OpenBSD__
97 /*********************************************************************
98 * PCI Device ID Table
99 *********************************************************************/
100 const struct pci_matchid em_devices[] = {
101 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_DPT },
102 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_DPT },
103 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_CPR_SPT },
104 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_80003ES2LAN_SDS_SPT },
105 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM },
106 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EM_LOM },
107 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP },
108 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LOM },
109 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82540EP_LP },
110 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI },
111 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541EI_MOBILE },
112 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER },
113 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541ER_LOM },
114 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI },
115 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_LF },
116 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82541GI_MOBILE },
117 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82542 },
118 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_COPPER },
119 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82543GC_FIBER },
120 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_COPPER },
121 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544EI_FIBER },
122 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_COPPER },
123 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82544GC_LOM },
124 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_COPPER },
125 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545EM_FIBER },
126 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_COPPER },
127 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_FIBER },
128 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82545GM_SERDES },
129 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_COPPER },
130 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_FIBER },
131 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546EB_QUAD_COPPER },
132 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_COPPER },
133 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_FIBER },
134 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_PCIE },
135 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_COPPER },
136 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_QUAD_CPR_K },
137 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_SERDES },
138 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82546GB_2 },
139 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI },
140 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547EI_MOBILE },
141 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82547GI },
142 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AF },
143 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_AT },
144 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_COPPER },
145 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_FIBER },
146 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR },
147 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_CPR_LP },
148 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_QUAD_FBR },
149 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SERDES },
150 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_DUAL },
151 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571EB_SDS_QUAD },
152 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82571PT_QUAD_CPR },
153 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_COPPER },
154 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_FIBER },
155 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI_SERDES },
156 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82572EI },
157 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E },
158 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_IAMT },
159 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573E_PM },
160 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L },
161 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_1 },
162 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573L_PL_2 },
163 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82573V_PM },
164 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574L },
165 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82574LA },
166 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_COPPER },
167 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575EB_SERDES },
168 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QUAD_CPR },
169 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82575GB_QP_PM },
170 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576 },
171 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_FIBER },
172 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES },
173 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_COPPER },
174 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_QUAD_CU_ET2 },
175 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS },
176 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_NS_SERDES },
177 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82576_SERDES_QUAD },
178 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LC },
179 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82577LM },
180 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DC },
181 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82578DM },
182 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579LM },
183 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82579V },
184 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER },
185 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_FIBER },
186 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES },
187 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SGMII },
188 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_COPPER_NF },
189 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I210_SERDES_NF },
190 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I211_COPPER },
191 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_LM },
192 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I217_V },
193 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM },
194 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_2 },
195 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_LM_3 },
196 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V },
197 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_2 },
198 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I218_V_3 },
199 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER },
200 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_FIBER },
201 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SERDES },
202 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_SGMII },
203 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_COPPER_DUAL },
204 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82580_QUAD_FIBER },
205 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SGMII },
206 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SERDES },
207 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_BPLANE },
208 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_DH89XXCC_SFP },
209 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82583V },
210 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_COPPER },
211 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_FIBER },
212 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SERDES },
213 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I350_SGMII },
214 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_1GBPS },
215 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_BP_2_5GBPS },
216 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_I354_SGMII },
217 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_82567V_3 },
218 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE },
219 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_G },
220 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IFE_GT },
221 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_AMT },
222 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_C },
223 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M },
224 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH8_IGP_M_AMT },
225 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_BM },
226 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE },
227 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_G },
228 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IFE_GT },
229 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_AMT },
230 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_C },
231 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M },
232 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_AMT },
233 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH9_IGP_M_V },
234 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LF },
235 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_D_BM_LM },
236 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LF },
237 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_LM },
238 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_ICH10_R_BM_V },
239 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_1 },
240 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_2 },
241 { PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_EP80579_LAN_3 }
242 };
243 #endif /* __OpenBSD__ */
244
245 /*********************************************************************
246 * Function prototypes
247 *********************************************************************/
248 #ifdef __FreeBSD__
249 int em_probe(device_t);
250 int em_attach(device_t);
251 int em_detach(device_t);
252 int em_shutdown(device_t);
253 void em_intr(void *);
254 #endif /* __FreeBSD__ */
255 #ifdef __OpenBSD__
256 int em_probe(struct device *, void *, void *);
257 void em_attach(struct device *, struct device *, void *);
258 int em_intr(void *);
259 #endif /* __OpenBSD__ */
260 void em_start(struct ifnet *);
261 void em_start_locked(struct ifnet *);
262 int em_ioctl(struct ifnet *, u_long, caddr_t);
263 void em_watchdog(struct ifnet *);
264 void em_init(void *);
265 void em_init_locked(struct em_softc *);
266 void em_stop(void *);
267 void em_media_status(struct ifnet *, struct ifmediareq *);
268 int em_media_change(struct ifnet *);
269 void em_identify_hardware(struct em_softc *);
270 int em_allocate_pci_resources(struct em_softc *);
271 void em_free_pci_resources(struct em_softc *);
272 void em_local_timer(void *);
273 int em_hardware_init(struct em_softc *);
274 #ifdef __FreeBSD__
275 void em_setup_interface(device_t, struct em_softc *);
276 #endif
277 #ifdef __OpenBSD__
278 void em_setup_interface(struct em_softc *);
279 #endif
280 int em_setup_transmit_structures(struct em_softc *);
281 void em_initialize_transmit_unit(struct em_softc *);
282 int em_setup_receive_structures(struct em_softc *);
283 void em_initialize_receive_unit(struct em_softc *);
284 void em_enable_intr(struct em_softc *);
285 void em_disable_intr(struct em_softc *);
286 void em_free_transmit_structures(struct em_softc *);
287 void em_free_receive_structures(struct em_softc *);
288 void em_update_stats_counters(struct em_softc *);
289 void em_clean_transmit_interrupts(struct em_softc *);
290 int em_allocate_receive_structures(struct em_softc *);
291 int em_allocate_transmit_structures(struct em_softc *);
292 void em_process_receive_interrupts(struct em_softc *, int);
293 void em_receive_checksum(struct em_softc *,
294 struct em_rx_desc *,
295 struct mbuf *);
296 void em_transmit_checksum_setup(struct em_softc *,
297 struct mbuf *,
298 u_int32_t *,
299 u_int32_t *);
300 void em_set_promisc(struct em_softc *);
301 void em_disable_promisc(struct em_softc *);
302 void em_set_multi(struct em_softc *);
303 void em_print_hw_stats(struct em_softc *);
304 void em_print_link_status(struct em_softc *);
305 void em_update_link_status(struct em_softc *);
306 int em_get_buf(int i, struct em_softc *,
307 struct mbuf *);
308 void em_enable_vlans(struct em_softc *);
309 int em_encap(struct em_softc *, struct mbuf *);
310 void em_smartspeed(struct em_softc *);
311 int em_82547_fifo_workaround(struct em_softc *, int);
312 void em_82547_update_fifo_head(struct em_softc *, int);
313 int em_82547_tx_fifo_reset(struct em_softc *);
314 void em_82547_move_tail(void *arg);
315 void em_82547_move_tail_locked(struct em_softc *);
316 int em_dma_malloc(struct em_softc *, bus_size_t,
317 struct em_dma_alloc *, int);
318 void em_dma_free(struct em_softc *, struct em_dma_alloc *);
319 void em_print_debug_info(struct em_softc *);
320 int em_is_valid_ether_addr(u_int8_t *);
321 #ifdef __FreeBSD__
322 int em_sysctl_stats(SYSCTL_HANDLER_ARGS);
323 int em_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
324 #endif /* __FreeBSD__ */
325 u_int32_t em_fill_descriptors (u_int64_t address,
326 u_int32_t length,
327 PDESC_ARRAY desc_array);
328 #ifdef __FreeBSD__
329 int em_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
330 void em_add_int_delay_sysctl(struct em_softc *, const char *,
331 const char *, struct em_int_delay_info *,
332 int, int);
333 #endif /* __FreeBSD__ */
334
335 /*********************************************************************
336 * FreeBSD Device Interface Entry Points
337 *********************************************************************/
338
339 #ifdef __FreeBSD__
340 device_method_t em_methods[] = {
341 /* Device interface */
342 DEVMETHOD(device_probe, em_probe),
343 DEVMETHOD(device_attach, em_attach),
344 DEVMETHOD(device_detach, em_detach),
345 DEVMETHOD(device_shutdown, em_shutdown),
346 {0, 0}
347 };
348
349 driver_t em_driver = {
350 "em", em_methods, sizeof(struct em_softc ),
351 };
352
353 devclass_t em_devclass;
354 DRIVER_MODULE(em, pci, em_driver, em_devclass, 0, 0);
355 MODULE_DEPEND(em, pci, 1, 1, 1);
356 MODULE_DEPEND(em, ether, 1, 1, 1);
357 #endif /* __FreeBSD__ */
358
359 #ifdef __OpenBSD__
360 struct cfattach em_ca = {
361 sizeof(struct em_softc), em_probe, em_attach
362 };
363
364 struct cfdriver em_cd = {
365 0, "em", DV_IFNET
366 };
367 #endif /* __OpenBSD__ */
368
369 /*********************************************************************
370 * Tunable default values.
371 *********************************************************************/
372
373 #define E1000_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
374 #define E1000_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
375
376 int em_tx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TIDV);
377 int em_rx_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RDTR);
378 int em_tx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_TADV);
379 int em_rx_abs_int_delay_dflt = E1000_TICKS_TO_USECS(EM_RADV);
380
381 #ifdef __FreeBSD__
382 TUNABLE_INT("hw.em.tx_int_delay", &em_tx_int_delay_dflt);
383 TUNABLE_INT("hw.em.rx_int_delay", &em_rx_int_delay_dflt);
384 TUNABLE_INT("hw.em.tx_abs_int_delay", &em_tx_abs_int_delay_dflt);
385 TUNABLE_INT("hw.em.rx_abs_int_delay", &em_rx_abs_int_delay_dflt);
386 #endif /* __FreeBSD__ */
387
388 /*********************************************************************
389 * Device identification routine
390 *
391 * em_probe determines if the driver should be loaded on
392 * adapter based on PCI vendor/device id of the adapter.
393 *
394 * return 0 on success, positive on failure
395 *********************************************************************/
396
397 #ifdef __FreeBSD__
398 int
em_probe(device_t dev)399 em_probe(device_t dev)
400 {
401 em_vendor_info_t *ent;
402
403 u_int16_t pci_vendor_id = 0;
404 u_int16_t pci_device_id = 0;
405 u_int16_t pci_subvendor_id = 0;
406 u_int16_t pci_subdevice_id = 0;
407 char adapter_name[60];
408
409 INIT_DEBUGOUT("em_probe: begin");
410
411 pci_vendor_id = pci_get_vendor(dev);
412 if (pci_vendor_id != EM_VENDOR_ID)
413 return(ENXIO);
414
415 pci_device_id = pci_get_device(dev);
416 pci_subvendor_id = pci_get_subvendor(dev);
417 pci_subdevice_id = pci_get_subdevice(dev);
418
419 ent = em_vendor_info_array;
420 while (ent->vendor_id != 0) {
421 if ((pci_vendor_id == ent->vendor_id) &&
422 (pci_device_id == ent->device_id) &&
423
424 ((pci_subvendor_id == ent->subvendor_id) ||
425 (ent->subvendor_id == PCI_ANY_ID)) &&
426
427 ((pci_subdevice_id == ent->subdevice_id) ||
428 (ent->subdevice_id == PCI_ANY_ID))) {
429 sprintf(adapter_name, "%s, Version - %s",
430 em_strings[ent->index],
431 em_driver_version);
432 device_set_desc_copy(dev, adapter_name);
433 return(0);
434 }
435 ent++;
436 }
437
438 return(ENXIO);
439 }
440 #endif /* __FreeBSD__ */
441
442 #ifdef __OpenBSD__
443 int
em_probe(struct device * parent,void * match,void * aux)444 em_probe(struct device *parent, void *match, void *aux)
445 {
446 INIT_DEBUGOUT("em_probe: begin");
447
448 return (pci_matchbyid((struct pci_attach_args *)aux, em_devices,
449 sizeof(em_devices)/sizeof(em_devices[0])));
450 }
451 #endif /* __OpenBSD__ */
452
453 /*********************************************************************
454 * Device initialization routine
455 *
456 * The attach entry point is called when the driver is being loaded.
457 * This routine identifies the type of hardware, allocates all resources
458 * and initializes the hardware.
459 *
460 * return 0 on success, positive on failure
461 *********************************************************************/
462
463 #ifdef __FreeBSD__
464 int
em_attach(device_t dev)465 em_attach(device_t dev)
466 {
467 pci_chipset_tag_t pc = pa->pa_pc;
468 #endif /* __FreeBSD__ */
469 #ifdef __OpenBSD__
470 void
471 em_attach(struct device *parent, struct device *self, void *aux)
472 {
473 struct pci_attach_args *pa = aux;
474 #endif /* __OpenBSD__ */
475 struct em_softc *sc;
476 int tsize, rsize;
477 int error = 0;
478
479 INIT_DEBUGOUT("em_attach: begin");
480
481 #ifdef __FreeBSD__
482 /* Allocate, clear, and link in our sc structure */
483 if (!(sc = device_get_softc(dev))) {
484 printf("em: sc structure allocation failed\n");
485 return(ENOMEM);
486 }
487 bzero(sc, sizeof(struct em_softc ));
488 sc->dev = dev;
489 sc->osdep.dev = dev;
490 sc->sc_dv.dv_xname = device_get_unit(dev);
491 EM_LOCK_INIT(sc, device_get_nameunit(dev));
492 #endif /* __FreeBSD__ */
493
494
495 #ifdef __OpenBSD__
496 sc = (struct em_softc *)self;
497 sc->osdep.em_pa = *pa;
498 #endif
499
500 if (em_adapter_list != NULL)
501 em_adapter_list->prev = sc;
502 sc->next = em_adapter_list;
503 em_adapter_list = sc;
504
505 #ifdef __FreeBSD__
506 /* SYSCTL stuff */
507 sysctl_ctx_init(&sc->sysctl_ctx);
508 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
509 SYSCTL_STATIC_CHILDREN(_hw),
510 OID_AUTO,
511 device_get_nameunit(dev),
512 CTLFLAG_RD,
513 0, "");
514 if (sc->sysctl_tree == NULL) {
515 error = EIO;
516 goto err_sysctl;
517 }
518
519 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
520 SYSCTL_CHILDREN(sc->sysctl_tree),
521 OID_AUTO, "debug_info", CTLTYPE_INT|CTLFLAG_RW,
522 (void *)sc, 0,
523 em_sysctl_debug_info, "I", "Debug Information");
524
525 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
526 SYSCTL_CHILDREN(sc->sysctl_tree),
527 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW,
528 (void *)sc, 0,
529 em_sysctl_stats, "I", "Statistics");
530
531 callout_init(&sc->timer, CALLOUT_MPSAFE);
532 callout_init(&sc->tx_fifo_timer, CALLOUT_MPSAFE);
533 #endif /* __FreeBSD__ */
534
535 #ifdef __OpenBSD__
536 timeout_set(&sc->timer_handle, em_local_timer, sc);
537 timeout_set(&sc->tx_fifo_timer_handle, em_82547_move_tail, sc);
538 #endif /* __OpenBSD__ */
539
540 /* Determine hardware revision */
541 em_identify_hardware(sc);
542
543 #ifdef __FreeBSD__
544 /* Set up some sysctls for the tunable interrupt delays */
545 em_add_int_delay_sysctl(sc, "rx_int_delay",
546 "receive interrupt delay in usecs", &sc->rx_int_delay,
547 E1000_REG_OFFSET(&sc->hw, RDTR), em_rx_int_delay_dflt);
548 em_add_int_delay_sysctl(sc, "tx_int_delay",
549 "transmit interrupt delay in usecs", &sc->tx_int_delay,
550 E1000_REG_OFFSET(&sc->hw, TIDV), em_tx_int_delay_dflt);
551 if (sc->hw.mac_type >= em_82540) {
552 em_add_int_delay_sysctl(sc, "rx_abs_int_delay",
553 "receive interrupt delay limit in usecs",
554 &sc->rx_abs_int_delay,
555 E1000_REG_OFFSET(&sc->hw, RADV),
556 em_rx_abs_int_delay_dflt);
557 em_add_int_delay_sysctl(sc, "tx_abs_int_delay",
558 "transmit interrupt delay limit in usecs",
559 &sc->tx_abs_int_delay,
560 E1000_REG_OFFSET(&sc->hw, TADV),
561 em_tx_abs_int_delay_dflt);
562 }
563 #endif /* __FreeBSD__ */
564
565 /* Parameters (to be read from user) */
566 sc->num_tx_desc = EM_MIN_TXD;
567 sc->num_rx_desc = EM_MIN_RXD;
568 sc->hw.autoneg = DO_AUTO_NEG;
569 sc->hw.wait_autoneg_complete = WAIT_FOR_AUTO_NEG_DEFAULT;
570 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
571 sc->hw.tbi_compatibility_en = TRUE;
572 sc->rx_buffer_len = EM_RXBUFFER_2048;
573
574 /*
575 * These parameters control the automatic generation(Tx) and
576 * response(Rx) to Ethernet PAUSE frames.
577 */
578 sc->hw.fc_high_water = FC_DEFAULT_HI_THRESH;
579 sc->hw.fc_low_water = FC_DEFAULT_LO_THRESH;
580 sc->hw.fc_pause_time = FC_DEFAULT_TX_TIMER;
581 sc->hw.fc_send_xon = TRUE;
582 sc->hw.fc = em_fc_full;
583
584 sc->hw.phy_init_script = 1;
585 sc->hw.phy_reset_disable = FALSE;
586
587 #ifndef EM_MASTER_SLAVE
588 sc->hw.master_slave = em_ms_hw_default;
589 #else
590 sc->hw.master_slave = EM_MASTER_SLAVE;
591 #endif
592 /*
593 * Set the max frame size assuming standard ethernet
594 * sized frames
595 */
596 sc->hw.max_frame_size =
597 ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
598
599 sc->hw.min_frame_size =
600 MINIMUM_ETHERNET_PACKET_SIZE + ETHER_CRC_LEN;
601
602 /*
603 * This controls when hardware reports transmit completion
604 * status.
605 */
606 sc->hw.report_tx_early = 1;
607
608
609 if (em_allocate_pci_resources(sc)) {
610 printf("%s: Allocation of PCI resources failed\n",
611 sc->sc_dv.dv_xname);
612 error = ENXIO;
613 goto err_pci;
614 }
615
616
617 /* Initialize eeprom parameters */
618 em_init_eeprom_params(&sc->hw);
619
620 tsize = EM_ROUNDUP(sc->num_tx_desc *
621 sizeof(struct em_tx_desc), 4096);
622
623 /* Allocate Transmit Descriptor ring */
624 if (em_dma_malloc(sc, tsize, &sc->txdma, BUS_DMA_NOWAIT)) {
625 printf("%s: Unable to allocate tx_desc memory\n",
626 sc->sc_dv.dv_xname);
627 error = ENOMEM;
628 goto err_tx_desc;
629 }
630 sc->tx_desc_base = (struct em_tx_desc *)sc->txdma.dma_vaddr;
631
632 rsize = EM_ROUNDUP(sc->num_rx_desc *
633 sizeof(struct em_rx_desc), 4096);
634
635 /* Allocate Receive Descriptor ring */
636 if (em_dma_malloc(sc, rsize, &sc->rxdma, BUS_DMA_NOWAIT)) {
637 printf("%s: Unable to allocate rx_desc memory\n",
638 sc->sc_dv.dv_xname);
639 error = ENOMEM;
640 goto err_rx_desc;
641 }
642 sc->rx_desc_base = (struct em_rx_desc *) sc->rxdma.dma_vaddr;
643
644 /* Initialize the hardware */
645 if (em_hardware_init(sc)) {
646 printf("%s: Unable to initialize the hardware\n",
647 sc->sc_dv.dv_xname);
648 error = EIO;
649 goto err_hw_init;
650 }
651
652 /* Copy the permanent MAC address out of the EEPROM */
653 if (em_read_mac_addr(&sc->hw) < 0) {
654 printf("%s: EEPROM read error while reading mac address\n",
655 sc->sc_dv.dv_xname);
656 error = EIO;
657 goto err_mac_addr;
658 }
659
660 if (!em_is_valid_ether_addr(sc->hw.mac_addr)) {
661 printf("%s: Invalid mac address\n", sc->sc_dv.dv_xname);
662 error = EIO;
663 goto err_mac_addr;
664 }
665
666 bcopy(sc->hw.mac_addr, sc->interface_data.ac_enaddr,
667 ETHER_ADDR_LEN);
668
669 /* Setup OS specific network interface */
670 em_setup_interface(sc);
671
672 /* Initialize statistics */
673 em_clear_hw_cntrs(&sc->hw);
674 em_update_stats_counters(sc);
675 sc->hw.get_link_status = 1;
676 em_check_for_link(&sc->hw);
677
678 /* Print the link status */
679 if (sc->link_active == 1) {
680 em_get_speed_and_duplex(&sc->hw, &sc->link_speed,
681 &sc->link_duplex);
682 #ifdef __FreeBSD__
683 printf("%s: Speed:%d Mbps Duplex:%s\n",
684 sc->sc_dv.dv_xname,
685 sc->link_speed,
686 sc->link_duplex == FULL_DUPLEX ? "Full" : "Half");
687 } else
688 printf("%s: Speed:N/A Duplex:N/A\n", sc->sc_dv.dv_xname);
689 #endif /* __FreeBSD__ */
690 #ifdef __OpenBSD__
691 }
692
693 printf(", address: %s\n", ether_sprintf(sc->interface_data.ac_enaddr));
694 #endif /* __OpenBSD__ */
695
696 /* Identify 82544 on PCIX */
697 em_get_bus_info(&sc->hw);
698 if(sc->hw.bus_type == em_bus_type_pcix &&
699 sc->hw.mac_type == em_82544) {
700 sc->pcix_82544 = TRUE;
701 }
702 else {
703 sc->pcix_82544 = FALSE;
704 }
705 INIT_DEBUGOUT("em_attach: end");
706 #ifdef __FreeBSD__
707 return(0);
708 #endif
709 #ifdef __OpenBSD__
710 return;
711 #endif
712
713 err_mac_addr:
714 err_hw_init:
715 em_dma_free(sc, &sc->rxdma);
716 err_rx_desc:
717 em_dma_free(sc, &sc->txdma);
718 err_tx_desc:
719 err_pci:
720 em_free_pci_resources(sc);
721 #ifdef __FreeBSD__
722 sysctl_ctx_free(&sc->sysctl_ctx);
723 err_sysctl:
724 return(error);
725 #endif /* __FreeBSD__ */
726
727 }
728
729 /*********************************************************************
730 * Device removal routine
731 *
732 * The detach entry point is called when the driver is being removed.
733 * This routine stops the adapter and deallocates all the resources
734 * that were allocated for driver operation.
735 *
736 * return 0 on success, positive on failure
737 *********************************************************************/
738
739 #ifdef __FreeBSD__
740 int
em_detach(device_t dev)741 em_detach(device_t dev)
742 {
743 struct em_softc * sc = device_get_softc(dev);
744 struct ifnet *ifp = &sc->interface_data.ac_if;
745 EM_LOCK_STATE();
746
747 INIT_DEBUGOUT("em_detach: begin");
748
749 EM_LOCK(sc);
750 sc->in_detach = 1;
751 em_stop(sc);
752 em_phy_hw_reset(&sc->hw);
753 EM_UNLOCK(sc);
754 #if __FreeBSD_version < 500000
755 ether_ifdetach(&sc->interface_data.ac_if, ETHER_BPF_SUPPORTED);
756 #else
757 ether_ifdetach(&sc->interface_data.ac_if);
758 #endif
759 em_free_pci_resources(sc);
760 bus_generic_detach(dev);
761
762 /* Free Transmit Descriptor ring */
763 if (sc->tx_desc_base) {
764 em_dma_free(sc, &sc->txdma);
765 sc->tx_desc_base = NULL;
766 }
767
768 /* Free Receive Descriptor ring */
769 if (sc->rx_desc_base) {
770 em_dma_free(sc, &sc->rxdma);
771 sc->rx_desc_base = NULL;
772 }
773
774 /* Free the sysctl tree */
775 sysctl_ctx_free(&sc->sysctl_ctx);
776
777 /* Remove from the sc list */
778 if (em_adapter_list == sc)
779 em_adapter_list = sc->next;
780 if (sc->next != NULL)
781 sc->next->prev = sc->prev;
782 if (sc->prev != NULL)
783 sc->prev->next = sc->next;
784
785 EM_LOCK_DESTROY(sc);
786
787 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
788 ifp->if_timer = 0;
789
790 return(0);
791 }
792 #endif /* __FreeBSD__ */
793
794 /*********************************************************************
795 *
796 * Shutdown entry point
797 *
798 **********************************************************************/
799
800 #ifdef __FreeBSD__
801 int
em_shutdown(device_t dev)802 em_shutdown(device_t dev)
803 {
804 struct em_softc *sc = device_get_softc(dev);
805 EM_LOCK_STATE();
806
807 EM_LOCK(sc);
808 em_stop(sc);
809 EM_UNLOCK(sc);
810 return(0);
811 }
812 #endif /* __FreeBSD__ */
813
814
815 /*********************************************************************
816 * Transmit entry point
817 *
818 * em_start is called by the stack to initiate a transmit.
819 * The driver will remain in this routine as long as there are
820 * packets to transmit and transmit resources are available.
821 * In case resources are not available stack is notified and
822 * the packet is requeued.
823 **********************************************************************/
824
825 void
em_start_locked(struct ifnet * ifp)826 em_start_locked(struct ifnet *ifp)
827 {
828 struct mbuf *m_head;
829 struct em_softc *sc = ifp->if_softc;
830
831 mtx_assert(&sc->mtx, MA_OWNED);
832
833 if (!sc->link_active)
834 return;
835
836 for (;;) {
837 IFQ_POLL(&ifp->if_snd, m_head);
838
839 if (m_head == NULL) break;
840
841 if (em_encap(sc, m_head)) {
842 ifp->if_flags |= IFF_OACTIVE;
843 break;
844 }
845
846 IFQ_DEQUEUE(&ifp->if_snd, m_head);
847
848 #if NBPFILTER > 0
849 /* Send a copy of the frame to the BPF listener */
850 if (ifp->if_bpf)
851 bpf_mtap(ifp->if_bpf, m_head);
852 #endif
853
854 /* Set timeout in case hardware has problems transmitting */
855 ifp->if_timer = EM_TX_TIMEOUT;
856
857 }
858 return;
859 }
860
861 void
em_start(struct ifnet * ifp)862 em_start(struct ifnet *ifp)
863 {
864 struct em_softc *sc = ifp->if_softc;
865 EM_LOCK_STATE();
866
867 EM_LOCK(sc);
868 em_start_locked(ifp);
869 EM_UNLOCK(sc);
870 return;
871 }
872
873 /*********************************************************************
874 * Ioctl entry point
875 *
876 * em_ioctl is called when the user wants to configure the
877 * interface.
878 *
879 * return 0 on success, positive on failure
880 **********************************************************************/
881
882 int
em_ioctl(struct ifnet * ifp,u_long command,caddr_t data)883 em_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
884 {
885 int error = 0;
886 struct ifreq *ifr = (struct ifreq *) data;
887 struct em_softc * sc = ifp->if_softc;
888 EM_LOCK_STATE();
889
890 #ifdef __OpenBSD__
891 struct ifaddr *ifa = (struct ifaddr *)data;
892 EM_LOCK(sc);
893 error = ether_ioctl(ifp, &sc->interface_data, command, data);
894 EM_UNLOCK(sc);
895
896 if (error > 0)
897 return (error);
898 #endif /* __OpenBSD__ */
899 if (sc->in_detach) return(error);
900
901 switch (command) {
902 case SIOCSIFADDR:
903 #ifdef __FreeBSD__
904 case SIOCGIFADDR:
905 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFADDR (Get/Set Interface Addr)");
906 ether_ioctl(ifp, command, data);
907 break;
908 #endif /* __FreeBSD__ */
909 #ifdef __OpenBSD__
910 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFADDR (Set Interface "
911 "Addr)");
912 ifp->if_flags |= IFF_UP;
913 em_init(sc);
914 switch (ifa->ifa_addr->sa_family) {
915 #ifdef INET
916 case AF_INET:
917 arp_ifinit(&sc->interface_data, ifa);
918 break;
919 #endif /* INET */
920 default:
921 break;
922 }
923 break;
924 #endif /* __OpenBSD__ */
925 case SIOCSIFMTU:
926 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFMTU (Set Interface MTU)");
927 if (ifr->ifr_mtu > MAX_JUMBO_FRAME_SIZE - ETHER_HDR_LEN) {
928 error = EINVAL;
929 } else {
930 EM_LOCK(sc);
931 ifp->if_mtu = ifr->ifr_mtu;
932 sc->hw.max_frame_size =
933 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
934 em_init_locked(sc);
935 EM_UNLOCK(sc);
936 }
937 break;
938 case SIOCSIFFLAGS:
939 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFFLAGS (Set Interface Flags)");
940 EM_LOCK(sc);
941 if (ifp->if_flags & IFF_UP) {
942 if (!(ifp->if_flags & IFF_RUNNING)) {
943 em_init_locked(sc);
944 }
945
946 em_disable_promisc(sc);
947 em_set_promisc(sc);
948 } else {
949 if (ifp->if_flags & IFF_RUNNING) {
950 em_stop(sc);
951 }
952 }
953 EM_UNLOCK(sc);
954 break;
955 case SIOCADDMULTI:
956 case SIOCDELMULTI:
957 IOCTL_DEBUGOUT("ioctl rcv'd: SIOC(ADD|DEL)MULTI");
958 #ifdef __OpenBSD__
959 error = (command == SIOCADDMULTI)
960 ? ether_addmulti(ifr, &sc->interface_data)
961 : ether_delmulti(ifr, &sc->interface_data);
962
963 if (error == ENETRESET) {
964 #endif /* __OpenBSD__ */
965 if (ifp->if_flags & IFF_RUNNING) {
966 EM_LOCK(sc);
967 em_disable_intr(sc);
968 em_set_multi(sc);
969 if (sc->hw.mac_type == em_82542_rev2_0) {
970 em_initialize_receive_unit(sc);
971 }
972 #ifdef DEVICE_POLLING
973 if (!(ifp->if_flags & IFF_POLLING))
974 #endif
975 em_enable_intr(sc);
976 EM_UNLOCK(sc);
977 }
978 #ifdef __OpenBSD__
979 error = 0;
980 }
981 #endif /* __OpenBSD__ */
982 break;
983 case SIOCSIFMEDIA:
984 case SIOCGIFMEDIA:
985 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCxIFMEDIA (Get/Set Interface Media)");
986 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
987 break;
988 #ifdef __FreeBSD__
989 case SIOCSIFCAP:
990 IOCTL_DEBUGOUT("ioctl rcv'd: SIOCSIFCAP (Set Capabilities)");
991 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
992 if (mask & IFCAP_HWCSUM) {
993 if (IFCAP_HWCSUM & ifp->if_capenable)
994 ifp->if_capenable &= ~IFCAP_HWCSUM;
995 else
996 ifp->if_capenable |= IFCAP_HWCSUM;
997 if (ifp->if_flags & IFF_RUNNING)
998 em_init(sc);
999 }
1000 break;
1001 #endif /* __FreeBSD__ */
1002 default:
1003 IOCTL_DEBUGOUT1("ioctl received: UNKNOWN (0x%x)\n", (int)command);
1004 error = EINVAL;
1005 }
1006
1007 return(error);
1008 }
1009
1010 /*********************************************************************
1011 * Watchdog entry point
1012 *
1013 * This routine is called whenever hardware quits transmitting.
1014 *
1015 **********************************************************************/
1016
1017 void
em_watchdog(struct ifnet * ifp)1018 em_watchdog(struct ifnet *ifp)
1019 {
1020 struct em_softc * sc;
1021 sc = ifp->if_softc;
1022
1023 /* If we are in this routine because of pause frames, then
1024 * don't reset the hardware.
1025 */
1026 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_TXOFF) {
1027 ifp->if_timer = EM_TX_TIMEOUT;
1028 return;
1029 }
1030
1031 if (em_check_for_link(&sc->hw))
1032 printf("%s: watchdog timeout -- resetting\n", sc->sc_dv.dv_xname);
1033
1034 ifp->if_flags &= ~IFF_RUNNING;
1035
1036 em_init(sc);
1037
1038 ifp->if_oerrors++;
1039 return;
1040 }
1041
1042 /*********************************************************************
1043 * Init entry point
1044 *
1045 * This routine is used in two ways. It is used by the stack as
1046 * init entry point in network interface structure. It is also used
1047 * by the driver as a hw/sw initialization routine to get to a
1048 * consistent state.
1049 *
1050 * return 0 on success, positive on failure
1051 **********************************************************************/
1052
1053 void
em_init_locked(struct em_softc * sc)1054 em_init_locked(struct em_softc *sc)
1055 {
1056 struct ifnet *ifp = &sc->interface_data.ac_if;
1057
1058 INIT_DEBUGOUT("em_init: begin");
1059
1060 mtx_assert(&sc->mtx, MA_OWNED);
1061
1062 em_stop(sc);
1063
1064 if (ifp->if_flags & IFF_UP) {
1065 sc->num_tx_desc = EM_MAX_TXD;
1066 sc->num_rx_desc = EM_MAX_RXD;
1067 } else {
1068 sc->num_tx_desc = EM_MIN_TXD;
1069 sc->num_rx_desc = EM_MIN_RXD;
1070 }
1071 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1);
1072
1073 #ifdef __FreeBSD__
1074 /* Get the latest mac address, User can use a LAA */
1075 bcopy(sc->interface_data.ac_enaddr, sc->hw.mac_addr,
1076 ETHER_ADDR_LEN);
1077 #endif /* __FreeBSD__ */
1078
1079 /* Initialize the hardware */
1080 if (em_hardware_init(sc)) {
1081 printf("%s: Unable to initialize the hardware\n",
1082 sc->sc_dv.dv_xname);
1083 return;
1084 }
1085
1086 /* em_enable_vlans(sc); */
1087
1088 /* Prepare transmit descriptors and buffers */
1089 if (em_setup_transmit_structures(sc)) {
1090 printf("%s: Could not setup transmit structures\n",
1091 sc->sc_dv.dv_xname);
1092 em_stop(sc);
1093 return;
1094 }
1095 em_initialize_transmit_unit(sc);
1096
1097 /* Setup Multicast table */
1098 em_set_multi(sc);
1099
1100 /* Prepare receive descriptors and buffers */
1101 if (em_setup_receive_structures(sc)) {
1102 printf("%s: Could not setup receive structures\n",
1103 sc->sc_dv.dv_xname);
1104 em_stop(sc);
1105 return;
1106 }
1107 em_initialize_receive_unit(sc);
1108
1109 /* Don't loose promiscuous settings */
1110 em_set_promisc(sc);
1111
1112 ifp->if_flags |= IFF_RUNNING;
1113 ifp->if_flags &= ~IFF_OACTIVE;
1114
1115 #ifdef __FreeBSD__
1116 if (sc->hw.mac_type >= em_82543) {
1117 if (ifp->if_capenable & IFCAP_TXCSUM)
1118 ifp->if_hwassist = EM_CHECKSUM_FEATURES;
1119 else
1120 ifp->if_hwassist = 0;
1121 }
1122
1123 callout_reset(&sc->timer, 2*hz, em_local_timer, sc);
1124 #endif /* __FreeBSD__ */
1125 #ifdef __OpenBSD__
1126 timeout_add(&sc->timer_handle, 2*hz);
1127 #endif
1128 em_clear_hw_cntrs(&sc->hw);
1129 #ifdef DEVICE_POLLING
1130 /*
1131 * Only enable interrupts if we are not polling, make sure
1132 * they are off otherwise.
1133 */
1134 if (ifp->if_flags & IFF_POLLING)
1135 em_disable_intr(sc);
1136 else
1137 #endif /* DEVICE_POLLING */
1138 em_enable_intr(sc);
1139
1140 /* Don't reset the phy next time init gets called */
1141 sc->hw.phy_reset_disable = TRUE;
1142
1143 return;
1144 }
1145
1146 void
em_init(void * arg)1147 em_init(void *arg)
1148 {
1149 struct em_softc * sc = arg;
1150 EM_LOCK_STATE();
1151
1152 EM_LOCK(sc);
1153 em_init_locked(sc);
1154 EM_UNLOCK(sc);
1155 return;
1156 }
1157
1158
1159 #ifdef DEVICE_POLLING
1160 poll_handler_t em_poll;
1161
1162 void
em_poll_locked(struct ifnet * ifp,enum poll_cmd cmd,int count)1163 em_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
1164 {
1165 struct em_softc *sc = ifp->if_softc;
1166 u_int32_t reg_icr;
1167
1168 mtx_assert(&sc->mtx, MA_OWNED);
1169
1170 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1171 em_enable_intr(sc);
1172 return;
1173 }
1174 if (cmd == POLL_AND_CHECK_STATUS) {
1175 reg_icr = E1000_READ_REG(&sc->hw, ICR);
1176 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1177 callout_stop(&sc->timer);
1178 sc->hw.get_link_status = 1;
1179 em_check_for_link(&sc->hw);
1180 em_update_link_status(sc);
1181 callout_reset(&sc->timer, 2*hz, em_local_timer, sc);
1182 }
1183 }
1184 if (ifp->if_flags & IFF_RUNNING) {
1185 em_process_receive_interrupts(sc, count);
1186 em_clean_transmit_interrupts(sc);
1187 }
1188
1189 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1190 em_start_locked(ifp);
1191 }
1192
1193 void
em_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)1194 em_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1195 {
1196 struct em_softc *sc = ifp->if_softc;
1197 EM_LOCK_STATE();
1198
1199 EM_LOCK(sc);
1200 em_poll_locked(ifp, cmd, count);
1201 EM_UNLOCK(sc);
1202 }
1203 #endif /* DEVICE_POLLING */
1204
1205 /*********************************************************************
1206 *
1207 * Interrupt Service routine
1208 *
1209 **********************************************************************/
1210 #ifdef __FreeBSD__
1211 void
1212 #endif
1213 #ifdef __OpenBSD__
1214 int
1215 #endif
em_intr(void * arg)1216 em_intr(void *arg)
1217 {
1218 u_int32_t loop_cnt = EM_MAX_INTR;
1219 u_int32_t reg_icr;
1220 struct ifnet *ifp;
1221 struct em_softc *sc = arg;
1222 EM_LOCK_STATE();
1223
1224 EM_LOCK(sc);
1225
1226 ifp = &sc->interface_data.ac_if;
1227
1228 #ifdef DEVICE_POLLING
1229 if (ifp->if_flags & IFF_POLLING) {
1230 EM_UNLOCK(sc);
1231 return;
1232 }
1233
1234 if (ether_poll_register(em_poll, ifp)) {
1235 em_disable_intr(sc);
1236 em_poll_locked(ifp, 0, 1);
1237 EM_UNLOCK(sc);
1238 return;
1239 }
1240 #endif /* DEVICE_POLLING */
1241
1242 reg_icr = E1000_READ_REG(&sc->hw, ICR);
1243 if (!reg_icr) {
1244 EM_UNLOCK(sc);
1245 #ifdef __FreeBSD__
1246 return;
1247 #endif
1248 #ifdef __OpenBSD__
1249 return (0);
1250 #endif
1251 }
1252
1253 /* Link status change */
1254 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1255 #ifdef __FreeBSD__
1256 callout_stop(&sc->timer);
1257 #endif
1258 #ifdef __OpenBSD__
1259 timeout_del(&sc->timer_handle);
1260 #endif
1261 sc->hw.get_link_status = 1;
1262 em_check_for_link(&sc->hw);
1263 em_update_link_status(sc);
1264 #ifdef __FreeBSD__
1265 callout_reset(&sc->timer, 2*hz, em_local_timer, sc);
1266 #endif
1267 #ifdef __OpenBSD__
1268 timeout_add(&sc->timer_handle, 2*hz);
1269 #endif
1270 }
1271
1272 while (loop_cnt > 0) {
1273 if (ifp->if_flags & IFF_RUNNING) {
1274 em_process_receive_interrupts(sc, -1);
1275 em_clean_transmit_interrupts(sc);
1276 }
1277 loop_cnt--;
1278 }
1279
1280 #ifdef __FreeBSD__
1281 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL)
1282 #endif
1283 #ifdef __OpenBSD__
1284 if (ifp->if_flags & IFF_RUNNING && IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1285 #endif
1286 em_start_locked(ifp);
1287
1288 EM_UNLOCK(sc);
1289 #ifdef __FreeBSD__
1290 return;
1291 #endif
1292 #ifdef __OpenBSD__
1293 return (1);
1294 #endif
1295 }
1296
1297
1298
1299 /*********************************************************************
1300 *
1301 * Media Ioctl callback
1302 *
1303 * This routine is called whenever the user queries the status of
1304 * the interface using ifconfig.
1305 *
1306 **********************************************************************/
1307 void
em_media_status(struct ifnet * ifp,struct ifmediareq * ifmr)1308 em_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1309 {
1310 struct em_softc * sc= ifp->if_softc;
1311
1312 INIT_DEBUGOUT("em_media_status: begin");
1313
1314 em_check_for_link(&sc->hw);
1315 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) {
1316 if (sc->link_active == 0) {
1317 em_get_speed_and_duplex(&sc->hw,
1318 &sc->link_speed,
1319 &sc->link_duplex);
1320 sc->link_active = 1;
1321 }
1322 } else {
1323 if (sc->link_active == 1) {
1324 sc->link_speed = 0;
1325 sc->link_duplex = 0;
1326 sc->link_active = 0;
1327 }
1328 }
1329
1330 ifmr->ifm_status = IFM_AVALID;
1331 ifmr->ifm_active = IFM_ETHER;
1332
1333 if (!sc->link_active)
1334 return;
1335
1336 ifmr->ifm_status |= IFM_ACTIVE;
1337
1338 if (sc->hw.media_type == em_media_type_fiber) {
1339 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1340 } else {
1341 switch (sc->link_speed) {
1342 case 10:
1343 ifmr->ifm_active |= IFM_10_T;
1344 break;
1345 case 100:
1346 ifmr->ifm_active |= IFM_100_TX;
1347 break;
1348 case 1000:
1349 #if defined(__FreeBSD__) && __FreeBSD_version < 500000
1350 ifmr->ifm_active |= IFM_1000_TX;
1351 #else
1352 ifmr->ifm_active |= IFM_1000_T;
1353 #endif
1354 break;
1355 }
1356 if (sc->link_duplex == FULL_DUPLEX)
1357 ifmr->ifm_active |= IFM_FDX;
1358 else
1359 ifmr->ifm_active |= IFM_HDX;
1360 }
1361 return;
1362 }
1363
1364 /*********************************************************************
1365 *
1366 * Media Ioctl callback
1367 *
1368 * This routine is called when the user changes speed/duplex using
1369 * media/mediopt option with ifconfig.
1370 *
1371 **********************************************************************/
1372 int
em_media_change(struct ifnet * ifp)1373 em_media_change(struct ifnet *ifp)
1374 {
1375 struct em_softc * sc = ifp->if_softc;
1376 struct ifmedia *ifm = &sc->media;
1377
1378 INIT_DEBUGOUT("em_media_change: begin");
1379
1380 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1381 return(EINVAL);
1382
1383 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1384 case IFM_AUTO:
1385 sc->hw.autoneg = DO_AUTO_NEG;
1386 sc->hw.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1387 break;
1388 case IFM_1000_SX:
1389 #if defined(__FreeBSD__) && __FreeBSD_version < 500000
1390 case IFM_1000_TX:
1391 #else
1392 case IFM_1000_T:
1393 #endif
1394 sc->hw.autoneg = DO_AUTO_NEG;
1395 sc->hw.autoneg_advertised = ADVERTISE_1000_FULL;
1396 break;
1397 case IFM_100_TX:
1398 sc->hw.autoneg = FALSE;
1399 sc->hw.autoneg_advertised = 0;
1400 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1401 sc->hw.forced_speed_duplex = em_100_full;
1402 else
1403 sc->hw.forced_speed_duplex = em_100_half;
1404 break;
1405 case IFM_10_T:
1406 sc->hw.autoneg = FALSE;
1407 sc->hw.autoneg_advertised = 0;
1408 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1409 sc->hw.forced_speed_duplex = em_10_full;
1410 else
1411 sc->hw.forced_speed_duplex = em_10_half;
1412 break;
1413 default:
1414 printf("%s: Unsupported media type\n", sc->sc_dv.dv_xname);
1415 }
1416
1417 /* As the speed/duplex settings my have changed we need to
1418 * reset the PHY.
1419 */
1420 sc->hw.phy_reset_disable = FALSE;
1421
1422 em_init(sc);
1423
1424 return(0);
1425 }
1426
1427 #ifdef __FreeBSD__
1428 void
em_tx_cb(void * arg,bus_dma_segment_t * seg,int nsegs,bus_size_t mapsize,int error)1429 em_tx_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1430 {
1431 struct em_q *q = arg;
1432
1433 if (error)
1434 return;
1435 KASSERT(nsegs <= EM_MAX_SCATTER,
1436 ("Too many DMA segments returned when mapping tx packet"));
1437 q->nsegs = nsegs;
1438 bcopy(seg, q->segs, nsegs * sizeof(seg[0]));
1439 }
1440 #endif /* __FreeBSD__ */
1441
1442 #define EM_FIFO_HDR 0x10
1443 #define EM_82547_PKT_THRESH 0x3e0
1444 #define EM_82547_TX_FIFO_SIZE 0x2800
1445 #define EM_82547_TX_FIFO_BEGIN 0xf00
1446 /*********************************************************************
1447 *
1448 * This routine maps the mbufs to tx descriptors.
1449 *
1450 * return 0 on success, positive on failure
1451 **********************************************************************/
1452 int
em_encap(struct em_softc * sc,struct mbuf * m_head)1453 em_encap(struct em_softc *sc, struct mbuf *m_head)
1454 {
1455 u_int32_t txd_upper;
1456 u_int32_t txd_lower, txd_used = 0, txd_saved = 0;
1457 int i, j, error;
1458 u_int64_t address;
1459
1460 /* For 82544 Workaround */
1461 DESC_ARRAY desc_array;
1462 u_int32_t array_elements;
1463 u_int32_t counter;
1464 #if NVLAN > 0
1465 struct ifvlan *ifv = NULL;
1466 #endif
1467 struct em_q q;
1468
1469 struct em_buffer *tx_buffer = NULL;
1470 struct em_tx_desc *current_tx_desc = NULL;
1471 /*struct ifnet *ifp = &sc->interface_data.ac_if;*/
1472
1473 /*
1474 * Force a cleanup if number of TX descriptors
1475 * available hits the threshold
1476 */
1477 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1478 em_clean_transmit_interrupts(sc);
1479 if (sc->num_tx_desc_avail <= EM_TX_CLEANUP_THRESHOLD) {
1480 sc->no_tx_desc_avail1++;
1481 return (ENOBUFS);
1482 }
1483 }
1484
1485 /*
1486 * Map the packet for DMA.
1487 */
1488 if (bus_dmamap_create(sc->txtag, MCLBYTES, 32, 0, 0, BUS_DMA_NOWAIT,
1489 &q.map)) {
1490 sc->no_tx_map_avail++;
1491 return (ENOMEM);
1492 }
1493 error = bus_dmamap_load_mbuf(sc->txtag, q.map,
1494 m_head, BUS_DMA_NOWAIT);
1495 if (error != 0) {
1496 sc->no_tx_dma_setup++;
1497 bus_dmamap_destroy(sc->txtag, q.map);
1498 return (error);
1499 }
1500 EM_KASSERT(q.map->dm_nsegs!= 0, ("em_encap: empty packet"));
1501
1502 if (q.map->dm_nsegs > sc->num_tx_desc_avail) {
1503 sc->no_tx_desc_avail2++;
1504 bus_dmamap_destroy(sc->txtag, q.map);
1505 return (ENOBUFS);
1506 }
1507
1508
1509 #ifdef __FreeBSD__
1510 if (ifp->if_hwassist > 0) {
1511 em_transmit_checksum_setup(sc, m_head,
1512 &txd_upper, &txd_lower);
1513 } else
1514 #endif /* __FreeBSD__ */
1515 txd_upper = txd_lower = 0;
1516
1517
1518 /* Find out if we are in vlan mode */
1519 #if NVLAN > 0
1520 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
1521 m_head->m_pkthdr.rcvif != NULL &&
1522 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
1523 ifv = m_head->m_pkthdr.rcvif->if_softc;
1524 #endif
1525
1526 i = sc->next_avail_tx_desc;
1527 if (sc->pcix_82544) {
1528 txd_saved = i;
1529 txd_used = 0;
1530 }
1531 for (j = 0; j < q.map->dm_nsegs; j++) {
1532 /* If sc is 82544 and on PCIX bus */
1533 if(sc->pcix_82544) {
1534 array_elements = 0;
1535 address = htole64(q.map->dm_segs[j].ds_addr);
1536 /*
1537 * Check the Address and Length combination and
1538 * split the data accordingly
1539 */
1540 array_elements = em_fill_descriptors(address,
1541 htole32(q.map->dm_segs[j].ds_len),
1542 &desc_array);
1543 for (counter = 0; counter < array_elements; counter++) {
1544 if (txd_used == sc->num_tx_desc_avail) {
1545 sc->next_avail_tx_desc = txd_saved;
1546 sc->no_tx_desc_avail2++;
1547 bus_dmamap_destroy(sc->txtag, q.map);
1548 return (ENOBUFS);
1549 }
1550 tx_buffer = &sc->tx_buffer_area[i];
1551 current_tx_desc = &sc->tx_desc_base[i];
1552 current_tx_desc->buffer_addr = htole64(
1553 desc_array.descriptor[counter].address);
1554 current_tx_desc->lower.data = htole32(
1555 (sc->txd_cmd | txd_lower |
1556 (u_int16_t)desc_array.descriptor[counter].length));
1557 current_tx_desc->upper.data = htole32((txd_upper));
1558 if (++i == sc->num_tx_desc)
1559 i = 0;
1560
1561 tx_buffer->m_head = NULL;
1562 txd_used++;
1563 }
1564 } else {
1565 tx_buffer = &sc->tx_buffer_area[i];
1566 current_tx_desc = &sc->tx_desc_base[i];
1567
1568 current_tx_desc->buffer_addr = htole64(q.map->dm_segs[j].ds_addr);
1569 current_tx_desc->lower.data = htole32(
1570 sc->txd_cmd | txd_lower | q.map->dm_segs[j].ds_len);
1571 current_tx_desc->upper.data = htole32(txd_upper);
1572
1573 if (++i == sc->num_tx_desc)
1574 i = 0;
1575
1576 tx_buffer->m_head = NULL;
1577 }
1578 }
1579
1580 sc->next_avail_tx_desc = i;
1581 if (sc->pcix_82544) {
1582 sc->num_tx_desc_avail -= txd_used;
1583 }
1584 else {
1585 sc->num_tx_desc_avail -= q.map->dm_nsegs;
1586 }
1587
1588 #if NVLAN > 0
1589 if (ifv != NULL) {
1590 /* Set the vlan id */
1591 current_tx_desc->upper.fields.special = htole16(ifv->ifv_tag);
1592
1593 /* Tell hardware to add tag */
1594 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_VLE);
1595 }
1596 #endif
1597
1598 tx_buffer->m_head = m_head;
1599 tx_buffer->map = q.map;
1600 bus_dmamap_sync(sc->txtag, q.map, 0, q.map->dm_mapsize,
1601 BUS_DMASYNC_PREWRITE);
1602
1603 /*
1604 * Last Descriptor of Packet needs End Of Packet (EOP)
1605 */
1606 current_tx_desc->lower.data |= htole32(E1000_TXD_CMD_EOP);
1607
1608 /*
1609 * Advance the Transmit Descriptor Tail (Tdt), this tells the E1000
1610 * that this frame is available to transmit.
1611 */
1612 if (sc->hw.mac_type == em_82547 &&
1613 sc->link_duplex == HALF_DUPLEX) {
1614 em_82547_move_tail_locked(sc);
1615 } else {
1616 E1000_WRITE_REG(&sc->hw, TDT, i);
1617 if (sc->hw.mac_type == em_82547) {
1618 em_82547_update_fifo_head(sc, m_head->m_pkthdr.len);
1619 }
1620 }
1621
1622 return (0);
1623 }
1624
1625 /*********************************************************************
1626 *
1627 * 82547 workaround to avoid controller hang in half-duplex environment.
1628 * The workaround is to avoid queuing a large packet that would span
1629 * the internal Tx FIFO ring boundary. We need to reset the FIFO pointers
1630 * in this case. We do that only when FIFO is quiescent.
1631 *
1632 **********************************************************************/
1633 void
em_82547_move_tail_locked(struct em_softc * sc)1634 em_82547_move_tail_locked(struct em_softc *sc)
1635 {
1636 uint16_t hw_tdt;
1637 uint16_t sw_tdt;
1638 struct em_tx_desc *tx_desc;
1639 uint16_t length = 0;
1640 boolean_t eop = 0;
1641
1642 EM_LOCK_ASSERT(sc);
1643
1644 hw_tdt = E1000_READ_REG(&sc->hw, TDT);
1645 sw_tdt = sc->next_avail_tx_desc;
1646
1647 while (hw_tdt != sw_tdt) {
1648 tx_desc = &sc->tx_desc_base[hw_tdt];
1649 length += tx_desc->lower.flags.length;
1650 eop = tx_desc->lower.data & E1000_TXD_CMD_EOP;
1651 if(++hw_tdt == sc->num_tx_desc)
1652 hw_tdt = 0;
1653
1654 if(eop) {
1655 if (em_82547_fifo_workaround(sc, length)) {
1656 sc->tx_fifo_wrk++;
1657 #ifdef __FreeBSD__
1658 callout_reset(&sc->tx_fifo_timer, 1,
1659 em_82547_move_tail, sc);
1660 #endif
1661 #ifdef __OpenBSD__
1662 timeout_add(&sc->tx_fifo_timer_handle, 1);
1663 #endif
1664 break;
1665 }
1666 E1000_WRITE_REG(&sc->hw, TDT, hw_tdt);
1667 em_82547_update_fifo_head(sc, length);
1668 length = 0;
1669 }
1670 }
1671 return;
1672 }
1673
1674 void
em_82547_move_tail(void * arg)1675 em_82547_move_tail(void *arg)
1676 {
1677 struct em_softc *sc = arg;
1678 EM_LOCK_STATE();
1679
1680 EM_LOCK(sc);
1681 em_82547_move_tail_locked(sc);
1682 EM_UNLOCK(sc);
1683 }
1684
1685 int
em_82547_fifo_workaround(struct em_softc * sc,int len)1686 em_82547_fifo_workaround(struct em_softc *sc, int len)
1687 {
1688 int fifo_space, fifo_pkt_len;
1689
1690 fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR);
1691
1692 if (sc->link_duplex == HALF_DUPLEX) {
1693 fifo_space = EM_82547_TX_FIFO_SIZE - sc->tx_fifo_head;
1694
1695 if (fifo_pkt_len >= (EM_82547_PKT_THRESH + fifo_space)) {
1696 if (em_82547_tx_fifo_reset(sc)) {
1697 return(0);
1698 }
1699 else {
1700 return(1);
1701 }
1702 }
1703 }
1704
1705 return(0);
1706 }
1707
1708 void
em_82547_update_fifo_head(struct em_softc * sc,int len)1709 em_82547_update_fifo_head(struct em_softc *sc, int len)
1710 {
1711 int fifo_pkt_len = EM_ROUNDUP(len + EM_FIFO_HDR, EM_FIFO_HDR);
1712
1713 /* tx_fifo_head is always 16 byte aligned */
1714 sc->tx_fifo_head += fifo_pkt_len;
1715 if (sc->tx_fifo_head >= EM_82547_TX_FIFO_SIZE) {
1716 sc->tx_fifo_head -= EM_82547_TX_FIFO_SIZE;
1717 }
1718
1719 return;
1720 }
1721
1722
1723 int
em_82547_tx_fifo_reset(struct em_softc * sc)1724 em_82547_tx_fifo_reset(struct em_softc *sc)
1725 {
1726 uint32_t tctl;
1727
1728 if ( (E1000_READ_REG(&sc->hw, TDT) ==
1729 E1000_READ_REG(&sc->hw, TDH)) &&
1730 (E1000_READ_REG(&sc->hw, TDFT) ==
1731 E1000_READ_REG(&sc->hw, TDFH)) &&
1732 (E1000_READ_REG(&sc->hw, TDFTS) ==
1733 E1000_READ_REG(&sc->hw, TDFHS)) &&
1734 (E1000_READ_REG(&sc->hw, TDFPC) == 0)) {
1735
1736 /* Disable TX unit */
1737 tctl = E1000_READ_REG(&sc->hw, TCTL);
1738 E1000_WRITE_REG(&sc->hw, TCTL, tctl & ~E1000_TCTL_EN);
1739
1740 /* Reset FIFO pointers */
1741 E1000_WRITE_REG(&sc->hw, TDFT, EM_82547_TX_FIFO_BEGIN);
1742 E1000_WRITE_REG(&sc->hw, TDFH, EM_82547_TX_FIFO_BEGIN);
1743 E1000_WRITE_REG(&sc->hw, TDFTS, EM_82547_TX_FIFO_BEGIN);
1744 E1000_WRITE_REG(&sc->hw, TDFHS, EM_82547_TX_FIFO_BEGIN);
1745
1746 /* Re-enable TX unit */
1747 E1000_WRITE_REG(&sc->hw, TCTL, tctl);
1748 E1000_WRITE_FLUSH(&sc->hw);
1749
1750 sc->tx_fifo_head = 0;
1751 sc->tx_fifo_reset++;
1752
1753 return(TRUE);
1754 }
1755 else {
1756 return(FALSE);
1757 }
1758 }
1759
1760 void
em_set_promisc(struct em_softc * sc)1761 em_set_promisc(struct em_softc * sc)
1762 {
1763
1764 u_int32_t reg_rctl;
1765 struct ifnet *ifp = &sc->interface_data.ac_if;
1766
1767 reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
1768
1769 if (ifp->if_flags & IFF_PROMISC) {
1770 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1771 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
1772 } else if (ifp->if_flags & IFF_ALLMULTI) {
1773 reg_rctl |= E1000_RCTL_MPE;
1774 reg_rctl &= ~E1000_RCTL_UPE;
1775 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
1776 }
1777
1778 return;
1779 }
1780
1781 void
em_disable_promisc(struct em_softc * sc)1782 em_disable_promisc(struct em_softc * sc)
1783 {
1784 u_int32_t reg_rctl;
1785
1786 reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
1787
1788 reg_rctl &= (~E1000_RCTL_UPE);
1789 reg_rctl &= (~E1000_RCTL_MPE);
1790 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
1791
1792 return;
1793 }
1794
1795
1796 /*********************************************************************
1797 * Multicast Update
1798 *
1799 * This routine is called whenever multicast address list is updated.
1800 *
1801 **********************************************************************/
1802
1803 void
em_set_multi(struct em_softc * sc)1804 em_set_multi(struct em_softc * sc)
1805 {
1806 u_int32_t reg_rctl = 0;
1807 u_int8_t mta[MAX_NUM_MULTICAST_ADDRESSES * ETH_LENGTH_OF_ADDRESS];
1808 #ifdef __FreeBSD__
1809 struct ifmultiaddr *ifma;
1810 #endif
1811 int mcnt = 0;
1812 struct ifnet *ifp = &sc->interface_data.ac_if;
1813 #ifdef __OpenBSD__
1814 struct arpcom *ac = &sc->interface_data;
1815 struct ether_multi *enm;
1816 struct ether_multistep step;
1817 #endif /* __OpenBSD__ */
1818
1819 IOCTL_DEBUGOUT("em_set_multi: begin");
1820
1821 if (sc->hw.mac_type == em_82542_rev2_0) {
1822 reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
1823 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
1824 em_pci_clear_mwi(&sc->hw);
1825 }
1826 reg_rctl |= E1000_RCTL_RST;
1827 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
1828 msec_delay(5);
1829 }
1830
1831 #ifdef __FreeBSD__
1832 #if __FreeBSD_version < 500000
1833 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1834 #else
1835 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1836 #endif
1837 if (ifma->ifma_addr->sa_family != AF_LINK)
1838 continue;
1839
1840 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) break;
1841
1842 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1843 &mta[mcnt*ETH_LENGTH_OF_ADDRESS], ETH_LENGTH_OF_ADDRESS);
1844 mcnt++;
1845 }
1846 #endif /* __FreeBSD__ */
1847 #ifdef __OpenBSD__
1848 ETHER_FIRST_MULTI(step, ac, enm);
1849 while (enm != NULL) {
1850 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1851 ifp->if_flags |= IFF_ALLMULTI;
1852 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
1853 }
1854 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1855 break;
1856 bcopy(enm->enm_addrlo, &mta[mcnt*ETH_LENGTH_OF_ADDRESS],
1857 ETH_LENGTH_OF_ADDRESS);
1858 mcnt++;
1859 ETHER_NEXT_MULTI(step, enm);
1860 }
1861 #endif /* __OpenBSD__ */
1862
1863 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1864 reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
1865 reg_rctl |= E1000_RCTL_MPE;
1866 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
1867 } else
1868 em_mc_addr_list_update(&sc->hw, mta, mcnt, 0, 1);
1869
1870 if (sc->hw.mac_type == em_82542_rev2_0) {
1871 reg_rctl = E1000_READ_REG(&sc->hw, RCTL);
1872 reg_rctl &= ~E1000_RCTL_RST;
1873 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
1874 msec_delay(5);
1875 if (sc->hw.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) {
1876 em_pci_set_mwi(&sc->hw);
1877 }
1878 }
1879
1880 return;
1881 }
1882
1883
1884 /*********************************************************************
1885 * Timer routine
1886 *
1887 * This routine checks for link status and updates statistics.
1888 *
1889 **********************************************************************/
1890
1891 void
1892 em_local_timer(void *arg)
1893 {
1894 struct ifnet *ifp;
1895 struct em_softc * sc = arg;
1896 EM_LOCK_STATE();
1897
1898 ifp = &sc->interface_data.ac_if;
1899
1900 EM_LOCK(sc);
1901
1902 em_check_for_link(&sc->hw);
1903 em_update_link_status(sc);
1904 em_update_stats_counters(sc);
1905 if (em_display_debug_stats && ifp->if_flags & IFF_RUNNING) {
1906 em_print_hw_stats(sc);
1907 }
1908 em_smartspeed(sc);
1909
1910 #ifdef __FreeBSD__
1911 callout_reset(&sc->timer, 2*hz, em_local_timer, sc);
1912 #endif /* __FreeBSD__ */
1913 #ifdef __OpenBSD__
1914 timeout_add(&sc->timer_handle, 2*hz);
1915 #endif /* __OpenBSD__ */
1916
1917 EM_UNLOCK(sc);
1918 return;
1919 }
1920
1921 void
1922 em_print_link_status(struct em_softc * sc)
1923 {
1924 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) {
1925 if (sc->link_active == 0) {
1926 em_get_speed_and_duplex(&sc->hw,
1927 &sc->link_speed,
1928 &sc->link_duplex);
1929 printf("%s: Link is up %d Mbps %s\n",
1930 sc->sc_dv.dv_xname,
1931 sc->link_speed,
1932 ((sc->link_duplex == FULL_DUPLEX) ?
1933 "Full Duplex" : "Half Duplex"));
1934 sc->link_active = 1;
1935 sc->smartspeed = 0;
1936 }
1937 } else {
1938 if (sc->link_active == 1) {
1939 sc->link_speed = 0;
1940 sc->link_duplex = 0;
1941 printf("%s: Link is Down\n", sc->sc_dv.dv_xname);
1942 sc->link_active = 0;
1943 }
1944 }
1945
1946 return;
1947 }
1948
1949 void
1950 em_update_link_status(struct em_softc * sc)
1951 {
1952 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU) {
1953 if (sc->link_active == 0) {
1954 em_get_speed_and_duplex(&sc->hw,
1955 &sc->link_speed,
1956 &sc->link_duplex);
1957 sc->link_active = 1;
1958 sc->smartspeed = 0;
1959 }
1960 } else {
1961 if (sc->link_active == 1) {
1962 sc->link_speed = 0;
1963 sc->link_duplex = 0;
1964 sc->link_active = 0;
1965 }
1966 }
1967
1968 return;
1969
1970 }
1971
1972 /*********************************************************************
1973 *
1974 * This routine disables all traffic on the sc by issuing a
1975 * global reset on the MAC and deallocates TX/RX buffers.
1976 *
1977 **********************************************************************/
1978
1979 void
1980 em_stop(void *arg)
1981 {
1982 struct ifnet *ifp;
1983 struct em_softc * sc = arg;
1984 ifp = &sc->interface_data.ac_if;
1985
1986 mtx_assert(&sc->mtx, MA_OWNED);
1987
1988 INIT_DEBUGOUT("em_stop: begin");
1989 em_disable_intr(sc);
1990 em_reset_hw(&sc->hw);
1991 #ifdef __FreeBSD__
1992 callout_stop(&sc->timer);
1993 callout_stop(&sc->tx_fifo_timer);
1994 #endif /* __FreeBSD__ */
1995 #ifdef __OpenBSD__
1996 timeout_del(&sc->timer_handle);
1997 timeout_del(&sc->tx_fifo_timer_handle);
1998 #endif /* __OpenBSD__ */
1999 em_free_transmit_structures(sc);
2000 em_free_receive_structures(sc);
2001
2002
2003 /* Tell the stack that the interface is no longer active */
2004 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2005
2006 return;
2007 }
2008
2009
2010 /*********************************************************************
2011 *
2012 * Determine hardware revision.
2013 *
2014 **********************************************************************/
2015 void
2016 em_identify_hardware(struct em_softc * sc)
2017 {
2018 u_int32_t reg;
2019 struct pci_attach_args *pa = &sc->osdep.em_pa;
2020
2021 /* Make sure our PCI config space has the necessary stuff set */
2022 sc->hw.pci_cmd_word = pci_conf_read(pa->pa_pc, pa->pa_tag,
2023 PCI_COMMAND_STATUS_REG);
2024 if (!((sc->hw.pci_cmd_word & PCI_COMMAND_MASTER_ENABLE) &&
2025 (sc->hw.pci_cmd_word & PCI_COMMAND_MEM_ENABLE))) {
2026 printf("%s: Memory Access and/or Bus Master bits were not set!\n",
2027 sc->sc_dv.dv_xname);
2028 sc->hw.pci_cmd_word |=
2029 (PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE);
2030 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
2031 sc->hw.pci_cmd_word);
2032 }
2033
2034 /* Save off the information about this board */
2035 sc->hw.vendor_id = PCI_VENDOR(pa->pa_id);
2036 sc->hw.device_id = PCI_PRODUCT(pa->pa_id);
2037
2038 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG);
2039 sc->hw.revision_id = PCI_REVISION(reg);
2040
2041 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
2042
2043 sc->hw.subsystem_vendor_id = PCI_VENDOR(reg);
2044 sc->hw.subsystem_id = PCI_PRODUCT(reg);
2045
2046 /* Identify the MAC */
2047 if (em_set_mac_type(&sc->hw))
2048 printf("%s: Unknown MAC Type\n", sc->sc_dv.dv_xname);
2049
2050 if(sc->hw.mac_type == em_82541 ||
2051 sc->hw.mac_type == em_82541_rev_2 ||
2052 sc->hw.mac_type == em_82547 ||
2053 sc->hw.mac_type == em_82547_rev_2)
2054 sc->hw.phy_init_script = TRUE;
2055
2056 return;
2057 }
2058
2059 int
2060 em_allocate_pci_resources(struct em_softc * sc)
2061 {
2062 int i, val, rid;
2063 pci_intr_handle_t ih;
2064 const char *intrstr = NULL;
2065 struct pci_attach_args *pa = &sc->osdep.em_pa;
2066 pci_chipset_tag_t pc = pa->pa_pc;
2067
2068 val = pci_conf_read(pa->pa_pc, pa->pa_tag, EM_MMBA);
2069 if (PCI_MAPREG_TYPE(val) != PCI_MAPREG_TYPE_MEM) {
2070 printf(": mmba isn't memory");
2071 return (ENXIO);
2072 }
2073 if (pci_mapreg_map(pa, EM_MMBA, PCI_MAPREG_MEM_TYPE(val), 0,
2074 &sc->osdep.mem_bus_space_tag, &sc->osdep.mem_bus_space_handle,
2075 &sc->osdep.em_membase, &sc->osdep.em_memsize, 0)) {
2076 printf(": can't find mem space\n");
2077 return (ENXIO);
2078 }
2079
2080 if (sc->hw.mac_type > em_82543) {
2081 /* Figure our where our IO BAR is ? */
2082 rid = EM_MMBA;
2083 for (i = 0; i < 5; i++) {
2084 val = pci_conf_read(pa->pa_pc, pa->pa_tag, rid);
2085 if (val & 0x00000001) {
2086 sc->io_rid = rid;
2087 break;
2088 }
2089 rid += 4;
2090 }
2091 if (pci_mapreg_map(pa, rid, PCI_MAPREG_TYPE_IO, 0,
2092 &sc->osdep.em_iobtag,
2093 &sc->osdep.em_iobhandle,
2094 &sc->osdep.em_iobase,
2095 &sc->osdep.em_iosize, 0)) {
2096 printf(": can't find io space\n");
2097 return (ENXIO);
2098 }
2099
2100 #ifdef __FreeBSD__
2101 sc->hw.io_base =
2102 rman_get_start(sc->res_ioport);
2103 #endif
2104 #ifdef __OpenBSD__
2105 sc->hw.io_base = 0;
2106 #endif
2107 }
2108
2109 if (pci_intr_map(pa, &ih)) {
2110 printf(": couldn't map interrupt\n");
2111 return (ENXIO);
2112 }
2113
2114 intrstr = pci_intr_string(pc, ih);
2115 sc->sc_intrhand = pci_intr_establish(pc, ih, IPL_NET, em_intr, sc,
2116 sc->sc_dv.dv_xname);
2117 if (sc->sc_intrhand == NULL) {
2118 printf(": couldn't establish interrupt");
2119 if (intrstr != NULL)
2120 printf(" at %s", intrstr);
2121 printf("\n");
2122 return (ENXIO);
2123 }
2124 printf(": %s", intrstr);
2125
2126 sc->hw.back = &sc->osdep;
2127
2128 return(0);
2129 }
2130
2131 void
2132 em_free_pci_resources(struct em_softc* sc)
2133 {
2134 struct pci_attach_args *pa = &sc->osdep.em_pa;
2135 pci_chipset_tag_t pc = pa->pa_pc;
2136
2137 if(sc->sc_intrhand)
2138 pci_intr_disestablish(pc, sc->sc_intrhand);
2139 sc->sc_intrhand = 0;
2140
2141 if(sc->osdep.em_iobase)
2142 bus_space_unmap(sc->osdep.em_iobtag, sc->osdep.em_iobhandle,
2143 sc->osdep.em_iosize);
2144 sc->osdep.em_iobase = 0;
2145
2146 if(sc->osdep.em_membase)
2147 bus_space_unmap(sc->osdep.mem_bus_space_tag, sc->osdep.mem_bus_space_handle,
2148 sc->osdep.em_memsize);
2149 sc->osdep.em_membase = 0;
2150
2151 }
2152
2153 /*********************************************************************
2154 *
2155 * Initialize the hardware to a configuration as specified by the
2156 * em_softc structure. The controller is reset, the EEPROM is
2157 * verified, the MAC address is set, then the shared initialization
2158 * routines are called.
2159 *
2160 **********************************************************************/
2161 int
2162 em_hardware_init(struct em_softc * sc)
2163 {
2164 INIT_DEBUGOUT("em_hardware_init: begin");
2165 /* Issue a global reset */
2166 em_reset_hw(&sc->hw);
2167
2168 /* When hardware is reset, fifo_head is also reset */
2169 sc->tx_fifo_head = 0;
2170
2171 /* Make sure we have a good EEPROM before we read from it */
2172 if (em_validate_eeprom_checksum(&sc->hw) < 0) {
2173 printf("%s: The EEPROM Checksum Is Not Valid\n",
2174 sc->sc_dv.dv_xname);
2175 return(EIO);
2176 }
2177
2178 if (em_read_part_num(&sc->hw, &(sc->part_num)) < 0) {
2179 printf("%s: EEPROM read error while reading part number\n",
2180 sc->sc_dv.dv_xname);
2181 return(EIO);
2182 }
2183
2184 if (em_init_hw(&sc->hw) < 0) {
2185 printf("%s: Hardware Initialization Failed",
2186 sc->sc_dv.dv_xname);
2187 return(EIO);
2188 }
2189
2190 em_check_for_link(&sc->hw);
2191 if (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)
2192 sc->link_active = 1;
2193 else
2194 sc->link_active = 0;
2195
2196 if (sc->link_active) {
2197 em_get_speed_and_duplex(&sc->hw,
2198 &sc->link_speed,
2199 &sc->link_duplex);
2200 } else {
2201 sc->link_speed = 0;
2202 sc->link_duplex = 0;
2203 }
2204
2205 return(0);
2206 }
2207
2208 /*********************************************************************
2209 *
2210 * Setup networking device structure and register an interface.
2211 *
2212 **********************************************************************/
2213 void
2214 #ifdef __FreeBSD__
2215 em_setup_interface(device_t dev, struct em_softc * sc)
2216 #endif
2217 #ifdef __OpenBSD__
2218 em_setup_interface(struct em_softc * sc)
2219 #endif
2220 {
2221 struct ifnet *ifp;
2222 INIT_DEBUGOUT("em_setup_interface: begin");
2223
2224 ifp = &sc->interface_data.ac_if;
2225 #ifdef __FreeBSD__
2226 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2227 #endif
2228 #ifdef __OpenBSD__
2229 strlcpy(ifp->if_xname, sc->sc_dv.dv_xname, IFNAMSIZ);
2230 #endif
2231
2232 ifp->if_mtu = ETHERMTU;
2233 ifp->if_output = ether_output;
2234 ifp->if_baudrate = 1000000000;
2235 #ifdef __FreeBSD__
2236 ifp->if_init = em_init;
2237 #endif
2238 ifp->if_softc = sc;
2239 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2240 ifp->if_ioctl = em_ioctl;
2241 ifp->if_start = em_start;
2242 ifp->if_watchdog = em_watchdog;
2243 #ifdef __FreeBSD__
2244 ifp->if_snd.ifq_maxlen = sc->num_tx_desc - 1;
2245 #endif
2246 #ifdef __OpenBSD__
2247 IFQ_SET_MAXLEN(&ifp->if_snd, sc->num_tx_desc - 1);
2248 IFQ_SET_READY(&ifp->if_snd);
2249 #endif
2250
2251 #ifdef __FreeBSD__
2252 if (sc->hw.mac_type >= em_82543) {
2253 ifp->if_capabilities = IFCAP_HWCSUM;
2254 ifp->if_capenable = ifp->if_capabilities;
2255 }
2256
2257 /*
2258 * Tell the upper layer(s) we support long frames.
2259 */
2260 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2261 #if __FreeBSD_version >= 500000
2262 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
2263 #endif
2264 #endif /* __FreeBSD__ */
2265
2266 #ifdef __OpenBSD__
2267 ifp->if_capabilities |= IFCAP_VLAN_MTU;
2268 #endif
2269
2270 /*
2271 * Specify the media types supported by this adapter and register
2272 * callbacks to update media and link information
2273 */
2274 ifmedia_init(&sc->media, IFM_IMASK, em_media_change,
2275 em_media_status);
2276 if (sc->hw.media_type == em_media_type_fiber) {
2277 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2278 0, NULL);
2279 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX,
2280 0, NULL);
2281 } else {
2282 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2283 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2284 0, NULL);
2285 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX,
2286 0, NULL);
2287 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2288 0, NULL);
2289 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T | IFM_FDX,
2290 0, NULL);
2291 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_T, 0, NULL);
2292 }
2293 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2294 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2295
2296 #ifdef __OpenBSD__
2297 if_attach(ifp);
2298 ether_ifattach(ifp);
2299 #endif
2300 return;
2301 }
2302
2303
2304 /*********************************************************************
2305 *
2306 * Workaround for SmartSpeed on 82541 and 82547 controllers
2307 *
2308 **********************************************************************/
2309 void
2310 em_smartspeed(struct em_softc *sc)
2311 {
2312 uint16_t phy_tmp;
2313
2314 if(sc->link_active || (sc->hw.phy_type != em_phy_igp) ||
2315 !sc->hw.autoneg || !(sc->hw.autoneg_advertised & ADVERTISE_1000_FULL))
2316 return;
2317
2318 if(sc->smartspeed == 0) {
2319 /* If Master/Slave config fault is asserted twice,
2320 * we assume back-to-back */
2321 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2322 if(!(phy_tmp & SR_1000T_MS_CONFIG_FAULT)) return;
2323 em_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2324 if(phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2325 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL,
2326 &phy_tmp);
2327 if(phy_tmp & CR_1000T_MS_ENABLE) {
2328 phy_tmp &= ~CR_1000T_MS_ENABLE;
2329 em_write_phy_reg(&sc->hw,
2330 PHY_1000T_CTRL, phy_tmp);
2331 sc->smartspeed++;
2332 if(sc->hw.autoneg &&
2333 !em_phy_setup_autoneg(&sc->hw) &&
2334 !em_read_phy_reg(&sc->hw, PHY_CTRL,
2335 &phy_tmp)) {
2336 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2337 MII_CR_RESTART_AUTO_NEG);
2338 em_write_phy_reg(&sc->hw,
2339 PHY_CTRL, phy_tmp);
2340 }
2341 }
2342 }
2343 return;
2344 } else if(sc->smartspeed == EM_SMARTSPEED_DOWNSHIFT) {
2345 /* If still no link, perhaps using 2/3 pair cable */
2346 em_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2347 phy_tmp |= CR_1000T_MS_ENABLE;
2348 em_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2349 if(sc->hw.autoneg &&
2350 !em_phy_setup_autoneg(&sc->hw) &&
2351 !em_read_phy_reg(&sc->hw, PHY_CTRL, &phy_tmp)) {
2352 phy_tmp |= (MII_CR_AUTO_NEG_EN |
2353 MII_CR_RESTART_AUTO_NEG);
2354 em_write_phy_reg(&sc->hw, PHY_CTRL, phy_tmp);
2355 }
2356 }
2357 /* Restart process after EM_SMARTSPEED_MAX iterations */
2358 if(sc->smartspeed++ == EM_SMARTSPEED_MAX)
2359 sc->smartspeed = 0;
2360
2361 return;
2362 }
2363
2364
2365 /*
2366 * Manage DMA'able memory.
2367 */
2368 #ifdef __FreeBSD__
2369 void
2370 em_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2371 {
2372 if (error)
2373 return;
2374 *(bus_addr_t*) arg = segs->ds_addr;
2375 return;
2376 }
2377 #endif /* __FreeBSD__ */
2378
2379 int
2380 em_dma_malloc(struct em_softc *sc, bus_size_t size,
2381 struct em_dma_alloc *dma, int mapflags)
2382 {
2383 int r;
2384
2385 #ifdef __FreeBSD__
2386 r = bus_dma_tag_create(NULL, /* parent */
2387 PAGE_SIZE, 0, /* alignment, bounds */
2388 BUS_SPACE_MAXADDR, /* lowaddr */
2389 BUS_SPACE_MAXADDR, /* highaddr */
2390 NULL, NULL, /* filter, filterarg */
2391 size, /* maxsize */
2392 1, /* nsegments */
2393 size, /* maxsegsize */
2394 BUS_DMA_ALLOCNOW, /* flags */
2395 NULL, /* lockfunc */
2396 NULL, /* lockarg */
2397 &dma->dma_tag);
2398 if (r != 0) {
2399 printf("%s: em_dma_malloc: bus_dma_tag_create failed; "
2400 "error %u\n", sc->sc_dv.dv_xname, r);
2401 goto fail_0;
2402 }
2403
2404 r = bus_dmamap_create(dma->dma_tag, BUS_DMA_NOWAIT, &dma->dma_map);
2405 #endif /* __FreeBSD__ */
2406 #ifdef __OpenBSD__
2407 dma->dma_tag = sc->osdep.em_pa.pa_dmat;
2408 r = bus_dmamap_create(dma->dma_tag, size, 1,
2409 size, 0, BUS_DMA_NOWAIT, &dma->dma_map);
2410 #endif /* __OpenBSD__ */
2411 if (r != 0) {
2412 printf("%s: em_dma_malloc: bus_dmamap_create failed; "
2413 "error %u\n", sc->sc_dv.dv_xname, r);
2414 goto fail_0;
2415 }
2416
2417 r = bus_dmamem_alloc(dma->dma_tag, size, PAGE_SIZE, 0, &dma->dma_seg,
2418 1, &dma->dma_nseg, BUS_DMA_NOWAIT);
2419 if (r != 0) {
2420 printf("%s: em_dma_malloc: bus_dmammem_alloc failed; "
2421 "size %lu, error %d\n", sc->sc_dv.dv_xname,
2422 (unsigned long)size, r);
2423 goto fail_1;
2424 }
2425
2426 r = bus_dmamem_map(dma->dma_tag, &dma->dma_seg, dma->dma_nseg, size,
2427 &dma->dma_vaddr, BUS_DMA_NOWAIT);
2428 if (r != 0) {
2429 printf("%s: em_dma_malloc: bus_dmammem_map failed; "
2430 "size %lu, error %d\n", sc->sc_dv.dv_xname,
2431 (unsigned long)size, r);
2432 goto fail_2;
2433 }
2434
2435 r = bus_dmamap_load(sc->osdep.em_pa.pa_dmat, dma->dma_map,
2436 dma->dma_vaddr,
2437 size,
2438 NULL,
2439 mapflags | BUS_DMA_NOWAIT);
2440 if (r != 0) {
2441 printf("%s: em_dma_malloc: bus_dmamap_load failed; "
2442 "error %u\n", sc->sc_dv.dv_xname, r);
2443 goto fail_3;
2444 }
2445
2446 dma->dma_size = size;
2447 return (0);
2448
2449 /* fail_4: */
2450 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2451 fail_3:
2452 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size);
2453 fail_2:
2454 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg);
2455 fail_1:
2456 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
2457 bus_dma_tag_destroy(dma->dma_tag);
2458 fail_0:
2459 dma->dma_map = NULL;
2460 /* dma->dma_tag = NULL; */
2461 return (r);
2462 }
2463
2464 void
2465 em_dma_free(struct em_softc *sc, struct em_dma_alloc *dma)
2466 {
2467 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
2468 bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, dma->dma_size);
2469 bus_dmamem_free(dma->dma_tag, &dma->dma_seg, dma->dma_nseg);
2470 bus_dmamap_destroy(dma->dma_tag, dma->dma_map);
2471 bus_dma_tag_destroy(dma->dma_tag);
2472 }
2473
2474
2475 /*********************************************************************
2476 *
2477 * Allocate memory for tx_buffer structures. The tx_buffer stores all
2478 * the information needed to transmit a packet on the wire.
2479 *
2480 **********************************************************************/
2481 int
2482 em_allocate_transmit_structures(struct em_softc * sc)
2483 {
2484 if (!(sc->tx_buffer_area =
2485 (struct em_buffer *) malloc(sizeof(struct em_buffer) *
2486 sc->num_tx_desc, M_DEVBUF,
2487 M_NOWAIT))) {
2488 printf("%s: Unable to allocate tx_buffer memory\n",
2489 sc->sc_dv.dv_xname);
2490 return ENOMEM;
2491 }
2492
2493 bzero(sc->tx_buffer_area,
2494 sizeof(struct em_buffer) * sc->num_tx_desc);
2495
2496 return 0;
2497 }
2498
2499 /*********************************************************************
2500 *
2501 * Allocate and initialize transmit structures.
2502 *
2503 **********************************************************************/
2504 int
2505 em_setup_transmit_structures(struct em_softc* sc)
2506 {
2507 #ifdef __FreeBSD__
2508 /*
2509 * Setup DMA descriptor areas.
2510 */
2511 if (bus_dma_tag_create(NULL, /* parent */
2512 PAGE_SIZE, 0, /* alignment, bounds */
2513 BUS_SPACE_MAXADDR, /* lowaddr */
2514 BUS_SPACE_MAXADDR, /* highaddr */
2515 NULL, NULL, /* filter, filterarg */
2516 MCLBYTES * 8, /* maxsize */
2517 EM_MAX_SCATTER, /* nsegments */
2518 MCLBYTES * 8, /* maxsegsize */
2519 BUS_DMA_ALLOCNOW, /* flags */
2520 NULL, /* lockfunc */
2521 NULL, /* lockarg */
2522 &sc->txtag)) {
2523 printf("%s: Unable to allocate TX DMA tag\n", sc->sc_dv.dv_xname);
2524 return (ENOMEM);
2525 }
2526
2527 #endif /* __FreeBSD__ */
2528 #ifdef __OpenBSD__
2529 sc->txtag = sc->osdep.em_pa.pa_dmat;
2530 #endif
2531
2532 if (em_allocate_transmit_structures(sc))
2533 return (ENOMEM);
2534
2535 bzero((void *) sc->tx_desc_base,
2536 (sizeof(struct em_tx_desc)) * sc->num_tx_desc);
2537
2538 sc->next_avail_tx_desc = 0;
2539 sc->oldest_used_tx_desc = 0;
2540
2541 /* Set number of descriptors available */
2542 sc->num_tx_desc_avail = sc->num_tx_desc;
2543
2544 /* Set checksum context */
2545 sc->active_checksum_context = OFFLOAD_NONE;
2546
2547 return (0);
2548 }
2549
2550 /*********************************************************************
2551 *
2552 * Enable transmit unit.
2553 *
2554 **********************************************************************/
2555 void
2556 em_initialize_transmit_unit(struct em_softc * sc)
2557 {
2558 u_int32_t reg_tctl;
2559 u_int32_t reg_tipg = 0;
2560 u_int64_t bus_addr;
2561
2562 INIT_DEBUGOUT("em_initialize_transmit_unit: begin");
2563 /* Setup the Base and Length of the Tx Descriptor Ring */
2564 bus_addr = sc->txdma.dma_map->dm_segs[0].ds_addr;
2565 E1000_WRITE_REG(&sc->hw, TDBAL, (u_int32_t)bus_addr);
2566 E1000_WRITE_REG(&sc->hw, TDBAH, (u_int32_t)(bus_addr >> 32));
2567 E1000_WRITE_REG(&sc->hw, TDLEN,
2568 sc->num_tx_desc *
2569 sizeof(struct em_tx_desc));
2570
2571 /* Setup the HW Tx Head and Tail descriptor pointers */
2572 E1000_WRITE_REG(&sc->hw, TDH, 0);
2573 E1000_WRITE_REG(&sc->hw, TDT, 0);
2574
2575
2576 HW_DEBUGOUT2("Base = %x, Length = %x\n",
2577 E1000_READ_REG(&sc->hw, TDBAL),
2578 E1000_READ_REG(&sc->hw, TDLEN));
2579
2580 /* Set the default values for the Tx Inter Packet Gap timer */
2581 switch (sc->hw.mac_type) {
2582 case em_82542_rev2_0:
2583 case em_82542_rev2_1:
2584 reg_tipg = DEFAULT_82542_TIPG_IPGT;
2585 reg_tipg |= DEFAULT_82542_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2586 reg_tipg |= DEFAULT_82542_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2587 break;
2588 default:
2589 if (sc->hw.media_type == em_media_type_fiber)
2590 reg_tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2591 else
2592 reg_tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2593 reg_tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2594 reg_tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2595 }
2596
2597 E1000_WRITE_REG(&sc->hw, TIPG, reg_tipg);
2598 E1000_WRITE_REG(&sc->hw, TIDV, sc->tx_int_delay.value);
2599 if(sc->hw.mac_type >= em_82540)
2600 E1000_WRITE_REG(&sc->hw, TADV,
2601 sc->tx_abs_int_delay.value);
2602
2603 /* Program the Transmit Control Register */
2604 reg_tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
2605 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2606 if (sc->link_duplex == 1) {
2607 reg_tctl |= E1000_FDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2608 } else {
2609 reg_tctl |= E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2610 }
2611 E1000_WRITE_REG(&sc->hw, TCTL, reg_tctl);
2612
2613 /* Setup Transmit Descriptor Settings for this adapter */
2614 sc->txd_cmd = E1000_TXD_CMD_IFCS | E1000_TXD_CMD_RS;
2615
2616 if (sc->tx_int_delay.value > 0)
2617 sc->txd_cmd |= E1000_TXD_CMD_IDE;
2618
2619 return;
2620 }
2621
2622 /*********************************************************************
2623 *
2624 * Free all transmit related data structures.
2625 *
2626 **********************************************************************/
2627 void
2628 em_free_transmit_structures(struct em_softc* sc)
2629 {
2630 struct em_buffer *tx_buffer;
2631 int i;
2632
2633 INIT_DEBUGOUT("free_transmit_structures: begin");
2634
2635 if (sc->tx_buffer_area != NULL) {
2636 tx_buffer = sc->tx_buffer_area;
2637 for (i = 0; i < sc->num_tx_desc; i++, tx_buffer++) {
2638 if (tx_buffer->m_head != NULL) {
2639 bus_dmamap_unload(sc->txtag, tx_buffer->map);
2640 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2641 m_freem(tx_buffer->m_head);
2642 }
2643 tx_buffer->m_head = NULL;
2644 }
2645 }
2646 if (sc->tx_buffer_area != NULL) {
2647 free(sc->tx_buffer_area, M_DEVBUF);
2648 sc->tx_buffer_area = NULL;
2649 }
2650 if (sc->txtag != NULL) {
2651 bus_dma_tag_destroy(sc->txtag);
2652 sc->txtag = NULL;
2653 }
2654 return;
2655 }
2656
2657 /*********************************************************************
2658 *
2659 * The offload context needs to be set when we transfer the first
2660 * packet of a particular protocol (TCP/UDP). We change the
2661 * context only if the protocol type changes.
2662 *
2663 **********************************************************************/
2664 #ifdef __FreeBSD__
2665 void
2666 em_transmit_checksum_setup(struct em_softc * sc,
2667 struct mbuf *mp,
2668 u_int32_t *txd_upper,
2669 u_int32_t *txd_lower)
2670 {
2671 struct em_context_desc *TXD;
2672 struct em_buffer *tx_buffer;
2673 int curr_txd;
2674
2675 if (mp->m_pkthdr.csum) {
2676
2677 if (mp->m_pkthdr.csum & CSUM_TCP) {
2678 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2679 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2680 if (sc->active_checksum_context == OFFLOAD_TCP_IP)
2681 return;
2682 else
2683 sc->active_checksum_context = OFFLOAD_TCP_IP;
2684
2685 } else if (mp->m_pkthdr.csum & CSUM_UDP) {
2686 *txd_upper = E1000_TXD_POPTS_TXSM << 8;
2687 *txd_lower = E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
2688 if (sc->active_checksum_context == OFFLOAD_UDP_IP)
2689 return;
2690 else
2691 sc->active_checksum_context = OFFLOAD_UDP_IP;
2692 } else {
2693 *txd_upper = 0;
2694 *txd_lower = 0;
2695 return;
2696 }
2697 } else {
2698 *txd_upper = 0;
2699 *txd_lower = 0;
2700 return;
2701 }
2702
2703 /* If we reach this point, the checksum offload context
2704 * needs to be reset.
2705 */
2706 curr_txd = sc->next_avail_tx_desc;
2707 tx_buffer = &sc->tx_buffer_area[curr_txd];
2708 TXD = (struct em_context_desc *) &sc->tx_desc_base[curr_txd];
2709
2710 TXD->lower_setup.ip_fields.ipcss = ETHER_HDR_LEN;
2711 TXD->lower_setup.ip_fields.ipcso =
2712 ETHER_HDR_LEN + offsetof(struct ip, ip_sum);
2713 TXD->lower_setup.ip_fields.ipcse =
2714 htole16(ETHER_HDR_LEN + sizeof(struct ip) - 1);
2715
2716 TXD->upper_setup.tcp_fields.tucss =
2717 ETHER_HDR_LEN + sizeof(struct ip);
2718 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2719
2720 if (sc->active_checksum_context == OFFLOAD_TCP_IP) {
2721 TXD->upper_setup.tcp_fields.tucso =
2722 ETHER_HDR_LEN + sizeof(struct ip) +
2723 offsetof(struct tcphdr, th_sum);
2724 } else if (sc->active_checksum_context == OFFLOAD_UDP_IP) {
2725 TXD->upper_setup.tcp_fields.tucso =
2726 ETHER_HDR_LEN + sizeof(struct ip) +
2727 offsetof(struct udphdr, uh_sum);
2728 }
2729
2730 TXD->tcp_seg_setup.data = htole32(0);
2731 TXD->cmd_and_length = htole32(sc->txd_cmd | E1000_TXD_CMD_DEXT);
2732
2733 tx_buffer->m_head = NULL;
2734
2735 if (++curr_txd == sc->num_tx_desc)
2736 curr_txd = 0;
2737
2738 sc->num_tx_desc_avail--;
2739 sc->next_avail_tx_desc = curr_txd;
2740
2741 return;
2742 }
2743 #endif /* __FreeBSD__ */
2744
2745 /**********************************************************************
2746 *
2747 * Examine each tx_buffer in the used queue. If the hardware is done
2748 * processing the packet then free associated resources. The
2749 * tx_buffer is put back on the free queue.
2750 *
2751 **********************************************************************/
2752 void
2753 em_clean_transmit_interrupts(struct em_softc* sc)
2754 {
2755 int i, num_avail;
2756 struct em_buffer *tx_buffer;
2757 struct em_tx_desc *tx_desc;
2758 struct ifnet *ifp = &sc->interface_data.ac_if;
2759
2760 mtx_assert(&sc->mtx, MA_OWNED);
2761
2762 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2763 return;
2764
2765 #ifdef DBG_STATS
2766 sc->clean_tx_interrupts++;
2767 #endif
2768 num_avail = sc->num_tx_desc_avail;
2769 i = sc->oldest_used_tx_desc;
2770
2771 tx_buffer = &sc->tx_buffer_area[i];
2772 tx_desc = &sc->tx_desc_base[i];
2773
2774 while(tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2775
2776 tx_desc->upper.data = 0;
2777 num_avail++;
2778
2779 if (tx_buffer->m_head) {
2780 ifp->if_opackets++;
2781 bus_dmamap_sync(sc->txtag, tx_buffer->map,
2782 0, tx_buffer->map->dm_mapsize,
2783 BUS_DMASYNC_POSTWRITE);
2784 bus_dmamap_unload(sc->txtag, tx_buffer->map);
2785 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2786
2787 m_freem(tx_buffer->m_head);
2788 tx_buffer->m_head = NULL;
2789 }
2790
2791 if (++i == sc->num_tx_desc)
2792 i = 0;
2793
2794 tx_buffer = &sc->tx_buffer_area[i];
2795 tx_desc = &sc->tx_desc_base[i];
2796 }
2797
2798 sc->oldest_used_tx_desc = i;
2799
2800 /*
2801 * If we have enough room, clear IFF_OACTIVE to tell the stack
2802 * that it is OK to send packets.
2803 * If there are no pending descriptors, clear the timeout. Otherwise,
2804 * if some descriptors have been freed, restart the timeout.
2805 */
2806 if (num_avail > EM_TX_CLEANUP_THRESHOLD) {
2807 ifp->if_flags &= ~IFF_OACTIVE;
2808 if (num_avail == sc->num_tx_desc)
2809 ifp->if_timer = 0;
2810 else if (num_avail == sc->num_tx_desc_avail)
2811 ifp->if_timer = EM_TX_TIMEOUT;
2812 }
2813 sc->num_tx_desc_avail = num_avail;
2814 return;
2815 }
2816
2817 /*********************************************************************
2818 *
2819 * Get a buffer from system mbuf buffer pool.
2820 *
2821 **********************************************************************/
2822 int
2823 em_get_buf(int i, struct em_softc *sc,
2824 struct mbuf *nmp)
2825 {
2826 struct mbuf *mp = nmp;
2827 struct em_buffer *rx_buffer;
2828 struct ifnet *ifp;
2829 int error;
2830
2831 ifp = &sc->interface_data.ac_if;
2832
2833 if (mp == NULL) {
2834 MGETHDR(mp, M_DONTWAIT, MT_DATA);
2835 if (mp == NULL) {
2836 sc->mbuf_alloc_failed++;
2837 return(ENOBUFS);
2838 }
2839 MCLGET(mp, M_DONTWAIT);
2840 if ((mp->m_flags & M_EXT) == 0) {
2841 m_freem(mp);
2842 sc->mbuf_cluster_failed++;
2843 return(ENOBUFS);
2844 }
2845 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2846 } else {
2847 mp->m_len = mp->m_pkthdr.len = MCLBYTES;
2848 mp->m_data = mp->m_ext.ext_buf;
2849 mp->m_next = NULL;
2850 }
2851
2852 if (ifp->if_mtu <= ETHERMTU) {
2853 m_adj(mp, ETHER_ALIGN);
2854 }
2855
2856 rx_buffer = &sc->rx_buffer_area[i];
2857
2858 /*
2859 * Using memory from the mbuf cluster pool, invoke the
2860 * bus_dma machinery to arrange the memory mapping.
2861 */
2862 error = bus_dmamap_load(sc->rxtag, rx_buffer->map,
2863 mtod(mp, void *), mp->m_len, NULL,
2864 0);
2865 if (error) {
2866 m_free(mp);
2867 return(error);
2868 }
2869 rx_buffer->m_head = mp;
2870 sc->rx_desc_base[i].buffer_addr = htole64(rx_buffer->map->dm_segs[0].ds_addr);
2871 bus_dmamap_sync(sc->rxtag, rx_buffer->map, 0,
2872 rx_buffer->map->dm_mapsize, BUS_DMASYNC_PREREAD);
2873
2874 return(0);
2875 }
2876
2877 /*********************************************************************
2878 *
2879 * Allocate memory for rx_buffer structures. Since we use one
2880 * rx_buffer per received packet, the maximum number of rx_buffer's
2881 * that we'll need is equal to the number of receive descriptors
2882 * that we've allocated.
2883 *
2884 **********************************************************************/
2885 int
2886 em_allocate_receive_structures(struct em_softc* sc)
2887 {
2888 int i, error;
2889 struct em_buffer *rx_buffer;
2890
2891 if (!(sc->rx_buffer_area =
2892 (struct em_buffer *) malloc(sizeof(struct em_buffer) *
2893 sc->num_rx_desc, M_DEVBUF,
2894 M_NOWAIT))) {
2895 printf("%s: Unable to allocate rx_buffer memory\n",
2896 sc->sc_dv.dv_xname);
2897 return(ENOMEM);
2898 }
2899
2900 bzero(sc->rx_buffer_area,
2901 sizeof(struct em_buffer) * sc->num_rx_desc);
2902
2903 #ifdef __FreeBSD__
2904 error = bus_dma_tag_create(NULL, /* parent */
2905 PAGE_SIZE, 0, /* alignment, bounds */
2906 BUS_SPACE_MAXADDR, /* lowaddr */
2907 BUS_SPACE_MAXADDR, /* highaddr */
2908 NULL, NULL, /* filter, filterarg */
2909 MCLBYTES, /* maxsize */
2910 1, /* nsegments */
2911 MCLBYTES, /* maxsegsize */
2912 BUS_DMA_ALLOCNOW, /* flags */
2913 &sc->rxtag);
2914 if (error != 0) {
2915 printf("%s: em_allocate_receive_structures: "
2916 "bus_dma_tag_create failed; error %u\n",
2917 sc->sc_dv.dv_xname, error);
2918 goto fail_0;
2919 }
2920 #endif /* __FreeBSD__ */
2921 #ifdef __OpenBSD__
2922 sc->rxtag = sc->osdep.em_pa.pa_dmat;
2923 #endif
2924
2925 rx_buffer = sc->rx_buffer_area;
2926 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) {
2927 error = bus_dmamap_create(sc->rxtag, MCLBYTES, 1,
2928 MCLBYTES, 0, BUS_DMA_NOWAIT,
2929 &rx_buffer->map);
2930 if (error != 0) {
2931 printf("%s: em_allocate_receive_structures: "
2932 "bus_dmamap_create failed; error %u\n",
2933 sc->sc_dv.dv_xname, error);
2934 goto fail_1;
2935 }
2936 }
2937
2938 for (i = 0; i < sc->num_rx_desc; i++) {
2939 error = em_get_buf(i, sc, NULL);
2940 if (error != 0) {
2941 sc->rx_buffer_area[i].m_head = NULL;
2942 sc->rx_desc_base[i].buffer_addr = 0;
2943 return(error);
2944 }
2945 }
2946
2947 return(0);
2948
2949 fail_1:
2950 bus_dma_tag_destroy(sc->rxtag);
2951 /* fail_0: */
2952 sc->rxtag = NULL;
2953 free(sc->rx_buffer_area, M_DEVBUF);
2954 sc->rx_buffer_area = NULL;
2955 return (error);
2956 }
2957
2958 /*********************************************************************
2959 *
2960 * Allocate and initialize receive structures.
2961 *
2962 **********************************************************************/
2963 int
2964 em_setup_receive_structures(struct em_softc * sc)
2965 {
2966 bzero((void *) sc->rx_desc_base,
2967 (sizeof(struct em_rx_desc)) * sc->num_rx_desc);
2968
2969 if (em_allocate_receive_structures(sc))
2970 return ENOMEM;
2971
2972 /* Setup our descriptor pointers */
2973 sc->next_rx_desc_to_check = 0;
2974 return(0);
2975 }
2976
2977 /*********************************************************************
2978 *
2979 * Enable receive unit.
2980 *
2981 **********************************************************************/
2982 void
2983 em_initialize_receive_unit(struct em_softc * sc)
2984 {
2985 u_int32_t reg_rctl;
2986 #ifdef __FreeBSD__
2987 u_int32_t reg_rxcsum;
2988 #endif
2989 struct ifnet *ifp;
2990 u_int64_t bus_addr;
2991
2992 INIT_DEBUGOUT("em_initialize_receive_unit: begin");
2993 ifp = &sc->interface_data.ac_if;
2994
2995 /* Make sure receives are disabled while setting up the descriptor ring */
2996 E1000_WRITE_REG(&sc->hw, RCTL, 0);
2997
2998 /* Set the Receive Delay Timer Register */
2999 E1000_WRITE_REG(&sc->hw, RDTR,
3000 sc->rx_int_delay.value | E1000_RDT_FPDB);
3001
3002 if(sc->hw.mac_type >= em_82540) {
3003 E1000_WRITE_REG(&sc->hw, RADV,
3004 sc->rx_abs_int_delay.value);
3005
3006 /* Set the interrupt throttling rate. Value is calculated
3007 * as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
3008 #define MAX_INTS_PER_SEC 8000
3009 #define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
3010 E1000_WRITE_REG(&sc->hw, ITR, DEFAULT_ITR);
3011 }
3012
3013 /* Setup the Base and Length of the Rx Descriptor Ring */
3014 #ifdef __FreeBSD__
3015 bus_addr = sc->rxdma.dma_paddr;
3016 #endif
3017 #ifdef __OpenBSD__
3018 bus_addr = sc->rxdma.dma_map->dm_segs[0].ds_addr;
3019 #endif
3020 E1000_WRITE_REG(&sc->hw, RDBAL, (u_int32_t)bus_addr);
3021 E1000_WRITE_REG(&sc->hw, RDBAH, (u_int32_t)(bus_addr >> 32));
3022 E1000_WRITE_REG(&sc->hw, RDLEN, sc->num_rx_desc *
3023 sizeof(struct em_rx_desc));
3024
3025 /* Setup the HW Rx Head and Tail Descriptor Pointers */
3026 E1000_WRITE_REG(&sc->hw, RDH, 0);
3027 E1000_WRITE_REG(&sc->hw, RDT, sc->num_rx_desc - 1);
3028
3029 /* Setup the Receive Control Register */
3030 reg_rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3031 E1000_RCTL_RDMTS_HALF |
3032 (sc->hw.mc_filter_type << E1000_RCTL_MO_SHIFT);
3033
3034 if (sc->hw.tbi_compatibility_on == TRUE)
3035 reg_rctl |= E1000_RCTL_SBP;
3036
3037
3038 switch (sc->rx_buffer_len) {
3039 default:
3040 case EM_RXBUFFER_2048:
3041 reg_rctl |= E1000_RCTL_SZ_2048;
3042 break;
3043 case EM_RXBUFFER_4096:
3044 reg_rctl |= E1000_RCTL_SZ_4096|E1000_RCTL_BSEX|E1000_RCTL_LPE;
3045 break;
3046 case EM_RXBUFFER_8192:
3047 reg_rctl |= E1000_RCTL_SZ_8192|E1000_RCTL_BSEX|E1000_RCTL_LPE;
3048 break;
3049 case EM_RXBUFFER_16384:
3050 reg_rctl |= E1000_RCTL_SZ_16384|E1000_RCTL_BSEX|E1000_RCTL_LPE;
3051 break;
3052 }
3053
3054 if (ifp->if_mtu > ETHERMTU)
3055 reg_rctl |= E1000_RCTL_LPE;
3056
3057 #ifdef __FreeBSD__
3058 /* Enable 82543 Receive Checksum Offload for TCP and UDP */
3059 if ((sc->hw.mac_type >= em_82543) &&
3060 (ifp->if_capenable & IFCAP_RXCSUM)) {
3061 reg_rxcsum = E1000_READ_REG(&sc->hw, RXCSUM);
3062 reg_rxcsum |= (E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL);
3063 E1000_WRITE_REG(&sc->hw, RXCSUM, reg_rxcsum);
3064 }
3065 #endif /* __FreeBSD__ */
3066
3067 /* Enable Receives */
3068 E1000_WRITE_REG(&sc->hw, RCTL, reg_rctl);
3069
3070 return;
3071 }
3072
3073 /*********************************************************************
3074 *
3075 * Free receive related data structures.
3076 *
3077 **********************************************************************/
3078 void
3079 em_free_receive_structures(struct em_softc * sc)
3080 {
3081 struct em_buffer *rx_buffer;
3082 int i;
3083
3084 INIT_DEBUGOUT("free_receive_structures: begin");
3085
3086 if (sc->rx_buffer_area != NULL) {
3087 rx_buffer = sc->rx_buffer_area;
3088 for (i = 0; i < sc->num_rx_desc; i++, rx_buffer++) {
3089 if (rx_buffer->map != NULL) {
3090 bus_dmamap_unload(sc->rxtag, rx_buffer->map);
3091 bus_dmamap_destroy(sc->rxtag, rx_buffer->map);
3092 }
3093 if (rx_buffer->m_head != NULL)
3094 m_freem(rx_buffer->m_head);
3095 rx_buffer->m_head = NULL;
3096 }
3097 }
3098 if (sc->rx_buffer_area != NULL) {
3099 free(sc->rx_buffer_area, M_DEVBUF);
3100 sc->rx_buffer_area = NULL;
3101 }
3102 if (sc->rxtag != NULL) {
3103 bus_dma_tag_destroy(sc->rxtag);
3104 sc->rxtag = NULL;
3105 }
3106 return;
3107 }
3108
3109 /*********************************************************************
3110 *
3111 * This routine executes in interrupt context. It replenishes
3112 * the mbufs in the descriptor and sends data which has been
3113 * dma'ed into host memory to upper layer.
3114 *
3115 * We loop at most count times if count is > 0, or until done if
3116 * count < 0.
3117 *
3118 *********************************************************************/
3119 void
3120 em_process_receive_interrupts(struct em_softc* sc, int count)
3121 {
3122 struct ifnet *ifp;
3123 struct mbuf *mp;
3124 #ifdef __FreeBSD__
3125 #if __FreeBSD_version < 500000
3126 struct ether_header *eh;
3127 #endif
3128 #endif /* __FreeBSD__ */
3129 u_int8_t accept_frame = 0;
3130 u_int8_t eop = 0;
3131 u_int16_t len, desc_len, prev_len_adj;
3132 int i;
3133
3134 /* Pointer to the receive descriptor being examined. */
3135 struct em_rx_desc *current_desc;
3136
3137 mtx_assert(&sc->mtx, MA_OWNED);
3138
3139 ifp = &sc->interface_data.ac_if;
3140 i = sc->next_rx_desc_to_check;
3141 current_desc = &sc->rx_desc_base[i];
3142
3143 if (!((current_desc->status) & E1000_RXD_STAT_DD)) {
3144 #ifdef DBG_STATS
3145 sc->no_pkts_avail++;
3146 #endif
3147 return;
3148 }
3149
3150 while ((current_desc->status & E1000_RXD_STAT_DD) && (count != 0)) {
3151
3152 mp = sc->rx_buffer_area[i].m_head;
3153 bus_dmamap_sync(sc->rxtag, sc->rx_buffer_area[i].map,
3154 0, sc->rx_buffer_area[i].map->dm_mapsize,
3155 BUS_DMASYNC_POSTREAD);
3156 bus_dmamap_unload(sc->rxtag, sc->rx_buffer_area[i].map);
3157
3158 accept_frame = 1;
3159 prev_len_adj = 0;
3160 desc_len = letoh16(current_desc->length);
3161 if (current_desc->status & E1000_RXD_STAT_EOP) {
3162 count--;
3163 eop = 1;
3164 if (desc_len < ETHER_CRC_LEN) {
3165 len = 0;
3166 prev_len_adj = ETHER_CRC_LEN - desc_len;
3167 }
3168 else {
3169 len = desc_len - ETHER_CRC_LEN;
3170 }
3171 } else {
3172 eop = 0;
3173 len = desc_len;
3174 }
3175
3176 if (current_desc->errors & E1000_RXD_ERR_FRAME_ERR_MASK) {
3177 u_int8_t last_byte;
3178 u_int32_t pkt_len = desc_len;
3179
3180 if (sc->fmp != NULL)
3181 pkt_len += sc->fmp->m_pkthdr.len;
3182
3183 last_byte = *(mtod(mp, caddr_t) + desc_len - 1);
3184
3185 if (TBI_ACCEPT(&sc->hw, current_desc->status,
3186 current_desc->errors,
3187 pkt_len, last_byte)) {
3188 em_tbi_adjust_stats(&sc->hw,
3189 &sc->stats,
3190 pkt_len,
3191 sc->hw.mac_addr);
3192 if (len > 0) len--;
3193 }
3194 else {
3195 accept_frame = 0;
3196 }
3197 }
3198
3199 if (accept_frame) {
3200
3201 if (em_get_buf(i, sc, NULL) == ENOBUFS) {
3202 sc->dropped_pkts++;
3203 em_get_buf(i, sc, mp);
3204 if (sc->fmp != NULL)
3205 m_freem(sc->fmp);
3206 sc->fmp = NULL;
3207 sc->lmp = NULL;
3208 break;
3209 }
3210
3211 /* Assign correct length to the current fragment */
3212 mp->m_len = len;
3213
3214 if (sc->fmp == NULL) {
3215 mp->m_pkthdr.len = len;
3216 sc->fmp = mp; /* Store the first mbuf */
3217 sc->lmp = mp;
3218 } else {
3219 /* Chain mbuf's together */
3220 mp->m_flags &= ~M_PKTHDR;
3221 /*
3222 * Adjust length of previous mbuf in chain if we
3223 * received less than 4 bytes in the last descriptor.
3224 */
3225 if (prev_len_adj > 0) {
3226 sc->lmp->m_len -= prev_len_adj;
3227 sc->fmp->m_pkthdr.len -= prev_len_adj;
3228 }
3229 sc->lmp->m_next = mp;
3230 sc->lmp = sc->lmp->m_next;
3231 sc->fmp->m_pkthdr.len += len;
3232 }
3233
3234 if (eop) {
3235 sc->fmp->m_pkthdr.rcvif = ifp;
3236 ifp->if_ipackets++;
3237
3238 #ifdef __OpenBSD__
3239 #if NBPFILTER > 0
3240 /*
3241 * Handle BPF listeners. Let the BPF
3242 * user see the packet.
3243 */
3244 if (ifp->if_bpf)
3245 bpf_mtap(ifp->if_bpf, sc->fmp);
3246 #endif
3247 em_receive_checksum(sc, current_desc,
3248 sc->fmp);
3249 ether_input_mbuf(ifp, sc->fmp);
3250 #endif /* __OpenBSD__ */
3251 #ifdef __FreeBSD__
3252 #if __FreeBSD_version < 500000
3253 eh = mtod(sc->fmp, struct ether_header *);
3254 /* Remove ethernet header from mbuf */
3255 m_adj(sc->fmp, sizeof(struct ether_header));
3256 em_receive_checksum(sc, current_desc,
3257 sc->fmp);
3258 if (current_desc->status & E1000_RXD_STAT_VP)
3259 VLAN_INPUT_TAG(eh, sc->fmp,
3260 (current_desc->special &
3261 E1000_RXD_SPC_VLAN_MASK));
3262 else
3263 ether_input(ifp, eh, sc->fmp);
3264 #else
3265
3266 em_receive_checksum(sc, current_desc,
3267 sc->fmp);
3268 if (current_desc->status & E1000_RXD_STAT_VP)
3269 VLAN_INPUT_TAG(ifp, sc->fmp,
3270 (current_desc->special &
3271 E1000_RXD_SPC_VLAN_MASK),
3272 sc->fmp = NULL);
3273
3274 if (sc->fmp != NULL) {
3275 EM_UNLOCK(sc);
3276 (*ifp->if_input)(ifp, sc->fmp);
3277 EM_LOCK(sc);
3278 }
3279 #endif
3280 #endif /* __FreeBSD__ */
3281 sc->fmp = NULL;
3282 sc->lmp = NULL;
3283 }
3284 } else {
3285 sc->dropped_pkts++;
3286 em_get_buf(i, sc, mp);
3287 if (sc->fmp != NULL)
3288 m_freem(sc->fmp);
3289 sc->fmp = NULL;
3290 sc->lmp = NULL;
3291 }
3292
3293 /* Zero out the receive descriptors status */
3294 current_desc->status = 0;
3295
3296 /* Advance the E1000's Receive Queue #0 "Tail Pointer". */
3297 E1000_WRITE_REG(&sc->hw, RDT, i);
3298
3299 /* Advance our pointers to the next descriptor */
3300 if (++i == sc->num_rx_desc) {
3301 i = 0;
3302 current_desc = sc->rx_desc_base;
3303 } else
3304 current_desc++;
3305 }
3306 sc->next_rx_desc_to_check = i;
3307 return;
3308 }
3309
3310 /*********************************************************************
3311 *
3312 * Verify that the hardware indicated that the checksum is valid.
3313 * Inform the stack about the status of checksum so that stack
3314 * doesn't spend time verifying the checksum.
3315 *
3316 *********************************************************************/
3317 void
3318 em_receive_checksum(struct em_softc *sc,
3319 struct em_rx_desc *rx_desc,
3320 struct mbuf *mp)
3321 {
3322 #ifdef __FreeBSD__
3323 /* 82543 or newer only */
3324 if ((sc->hw.mac_type < em_82543) ||
3325 /* Ignore Checksum bit is set */
3326 (rx_desc->status & E1000_RXD_STAT_IXSM)) {
3327 mp->m_pkthdr.csum = 0;
3328 return;
3329 }
3330
3331 if (rx_desc->status & E1000_RXD_STAT_IPCS) {
3332 /* Did it pass? */
3333 if (!(rx_desc->errors & E1000_RXD_ERR_IPE)) {
3334 /* IP Checksum Good */
3335 mp->m_pkthdr.csum = CSUM_IP_CHECKED;
3336 mp->m_pkthdr.csum |= CSUM_IP_VALID;
3337
3338 } else {
3339 mp->m_pkthdr.csum = 0;
3340 }
3341 }
3342
3343 if (rx_desc->status & E1000_RXD_STAT_TCPCS) {
3344 /* Did it pass? */
3345 if (!(rx_desc->errors & E1000_RXD_ERR_TCPE)) {
3346 mp->m_pkthdr.csum |=
3347 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
3348 mp->m_pkthdr.csum_data = htons(0xffff);
3349 }
3350 }
3351
3352 return;
3353 #endif /* __FreeBSD__ */
3354 #ifdef __OpenBSD__
3355 /* 82543 or newer only */
3356 if ((sc->hw.mac_type < em_82543) ||
3357 /* Ignore Checksum bit is set */
3358 (rx_desc->status & E1000_RXD_STAT_IXSM))
3359 return;
3360
3361 if ((rx_desc->status & (E1000_RXD_STAT_IPCS|E1000_RXD_ERR_IPE)) ==
3362 E1000_RXD_STAT_IPCS)
3363 mp->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK;
3364
3365 if ((rx_desc->status & (E1000_RXD_STAT_IPCS|E1000_RXD_ERR_IPE|
3366 E1000_RXD_STAT_TCPCS|E1000_RXD_ERR_TCPE)) ==
3367 (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_IPCS))
3368 mp->m_pkthdr.csum |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
3369 #endif /* __OpenBSD__ */
3370 }
3371
3372
3373 void
3374 em_enable_vlans(struct em_softc * sc)
3375 {
3376 uint32_t ctrl;
3377
3378 E1000_WRITE_REG(&sc->hw, VET, ETHERTYPE_8021Q);
3379
3380 ctrl = E1000_READ_REG(&sc->hw, CTRL);
3381 ctrl |= E1000_CTRL_VME;
3382 E1000_WRITE_REG(&sc->hw, CTRL, ctrl);
3383
3384 return;
3385 }
3386
3387 void
3388 em_enable_intr(struct em_softc* sc)
3389 {
3390 E1000_WRITE_REG(&sc->hw, IMS, (IMS_ENABLE_MASK));
3391 return;
3392 }
3393
3394 void
3395 em_disable_intr(struct em_softc *sc)
3396 {
3397 E1000_WRITE_REG(&sc->hw, IMC,
3398 (0xffffffff & ~E1000_IMC_RXSEQ));
3399 return;
3400 }
3401
3402 int
3403 em_is_valid_ether_addr(u_int8_t *addr)
3404 {
3405 const char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
3406
3407 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) {
3408 return (FALSE);
3409 }
3410
3411 return(TRUE);
3412 }
3413
3414 void
3415 em_write_pci_cfg(struct em_hw *hw,
3416 uint32_t reg,
3417 uint16_t *value)
3418 {
3419 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
3420 pci_chipset_tag_t pc = pa->pa_pc;
3421 /* Should we do read/mask/write...? 16 vs 32 bit!!! */
3422 pci_conf_write(pc, pa->pa_tag, reg, *value);
3423 }
3424
3425 void
3426 em_read_pci_cfg(struct em_hw *hw, uint32_t reg,
3427 uint16_t *value)
3428 {
3429 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
3430 pci_chipset_tag_t pc = pa->pa_pc;
3431 *value = pci_conf_read(pc, pa->pa_tag, reg);
3432 return;
3433 }
3434
3435 void
3436 em_pci_set_mwi(struct em_hw *hw)
3437 {
3438 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
3439 pci_chipset_tag_t pc = pa->pa_pc;
3440 /* Should we do read/mask/write...? 16 vs 32 bit!!! */
3441 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
3442 (hw->pci_cmd_word | CMD_MEM_WRT_INVALIDATE));
3443
3444 }
3445
3446 void
3447 em_pci_clear_mwi(struct em_hw *hw)
3448 {
3449 struct pci_attach_args *pa = &((struct em_osdep *)hw->back)->em_pa;
3450 pci_chipset_tag_t pc = pa->pa_pc;
3451 /* Should we do read/mask/write...? 16 vs 32 bit!!! */
3452 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
3453 (hw->pci_cmd_word & ~CMD_MEM_WRT_INVALIDATE));
3454
3455 }
3456
3457 #ifdef __FreeBSD__
3458 int32_t
3459 em_io_read(struct em_hw *hw, unsigned long port)
3460 {
3461 return(inl(port));
3462 }
3463
3464 void
3465 em_io_write(struct em_hw *hw, unsigned long port, uint32_t value)
3466 {
3467 outl(port, value);
3468 return;
3469 }
3470 #endif /* __FreeBSD__ */
3471
3472 /*********************************************************************
3473 * 82544 Coexistence issue workaround.
3474 * There are 2 issues.
3475 * 1. Transmit Hang issue.
3476 * To detect this issue, following equation can be used...
3477 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3478 * If SUM[3:0] is in between 1 to 4, we will have this issue.
3479 *
3480 * 2. DAC issue.
3481 * To detect this issue, following equation can be used...
3482 * SIZE[3:0] + ADDR[2:0] = SUM[3:0].
3483 * If SUM[3:0] is in between 9 to c, we will have this issue.
3484 *
3485 *
3486 * WORKAROUND:
3487 * Make sure we do not have ending address as 1,2,3,4(Hang) or 9,a,b,c (DAC)
3488 *
3489 *** *********************************************************************/
3490 u_int32_t
3491 em_fill_descriptors (u_int64_t address,
3492 u_int32_t length,
3493 PDESC_ARRAY desc_array)
3494 {
3495 /* Since issue is sensitive to length and address.*/
3496 /* Let us first check the address...*/
3497 u_int32_t safe_terminator;
3498 if (length <= 4) {
3499 desc_array->descriptor[0].address = address;
3500 desc_array->descriptor[0].length = length;
3501 desc_array->elements = 1;
3502 return desc_array->elements;
3503 }
3504 safe_terminator = (u_int32_t)((((u_int32_t)address & 0x7) + (length & 0xF)) & 0xF);
3505 /* if it does not fall between 0x1 to 0x4 and 0x9 to 0xC then return */
3506 if (safe_terminator == 0 ||
3507 (safe_terminator > 4 &&
3508 safe_terminator < 9) ||
3509 (safe_terminator > 0xC &&
3510 safe_terminator <= 0xF)) {
3511 desc_array->descriptor[0].address = address;
3512 desc_array->descriptor[0].length = length;
3513 desc_array->elements = 1;
3514 return desc_array->elements;
3515 }
3516
3517 desc_array->descriptor[0].address = address;
3518 desc_array->descriptor[0].length = length - 4;
3519 desc_array->descriptor[1].address = address + (length - 4);
3520 desc_array->descriptor[1].length = 4;
3521 desc_array->elements = 2;
3522 return desc_array->elements;
3523 }
3524
3525 /**********************************************************************
3526 *
3527 * Update the board statistics counters.
3528 *
3529 **********************************************************************/
3530 void
3531 em_update_stats_counters(struct em_softc *sc)
3532 {
3533 struct ifnet *ifp;
3534
3535 if(sc->hw.media_type == em_media_type_copper ||
3536 (E1000_READ_REG(&sc->hw, STATUS) & E1000_STATUS_LU)) {
3537 sc->stats.symerrs += E1000_READ_REG(&sc->hw, SYMERRS);
3538 sc->stats.sec += E1000_READ_REG(&sc->hw, SEC);
3539 }
3540 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, CRCERRS);
3541 sc->stats.mpc += E1000_READ_REG(&sc->hw, MPC);
3542 sc->stats.scc += E1000_READ_REG(&sc->hw, SCC);
3543 sc->stats.ecol += E1000_READ_REG(&sc->hw, ECOL);
3544
3545 sc->stats.mcc += E1000_READ_REG(&sc->hw, MCC);
3546 sc->stats.latecol += E1000_READ_REG(&sc->hw, LATECOL);
3547 sc->stats.colc += E1000_READ_REG(&sc->hw, COLC);
3548 sc->stats.dc += E1000_READ_REG(&sc->hw, DC);
3549 sc->stats.rlec += E1000_READ_REG(&sc->hw, RLEC);
3550 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, XONRXC);
3551 sc->stats.xontxc += E1000_READ_REG(&sc->hw, XONTXC);
3552 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, XOFFRXC);
3553 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, XOFFTXC);
3554 sc->stats.fcruc += E1000_READ_REG(&sc->hw, FCRUC);
3555 sc->stats.prc64 += E1000_READ_REG(&sc->hw, PRC64);
3556 sc->stats.prc127 += E1000_READ_REG(&sc->hw, PRC127);
3557 sc->stats.prc255 += E1000_READ_REG(&sc->hw, PRC255);
3558 sc->stats.prc511 += E1000_READ_REG(&sc->hw, PRC511);
3559 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, PRC1023);
3560 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, PRC1522);
3561 sc->stats.gprc += E1000_READ_REG(&sc->hw, GPRC);
3562 sc->stats.bprc += E1000_READ_REG(&sc->hw, BPRC);
3563 sc->stats.mprc += E1000_READ_REG(&sc->hw, MPRC);
3564 sc->stats.gptc += E1000_READ_REG(&sc->hw, GPTC);
3565
3566 /* For the 64-bit byte counters the low dword must be read first. */
3567 /* Both registers clear on the read of the high dword */
3568
3569 sc->stats.gorcl += E1000_READ_REG(&sc->hw, GORCL);
3570 sc->stats.gorch += E1000_READ_REG(&sc->hw, GORCH);
3571 sc->stats.gotcl += E1000_READ_REG(&sc->hw, GOTCL);
3572 sc->stats.gotch += E1000_READ_REG(&sc->hw, GOTCH);
3573
3574 sc->stats.rnbc += E1000_READ_REG(&sc->hw, RNBC);
3575 sc->stats.ruc += E1000_READ_REG(&sc->hw, RUC);
3576 sc->stats.rfc += E1000_READ_REG(&sc->hw, RFC);
3577 sc->stats.roc += E1000_READ_REG(&sc->hw, ROC);
3578 sc->stats.rjc += E1000_READ_REG(&sc->hw, RJC);
3579
3580 sc->stats.torl += E1000_READ_REG(&sc->hw, TORL);
3581 sc->stats.torh += E1000_READ_REG(&sc->hw, TORH);
3582 sc->stats.totl += E1000_READ_REG(&sc->hw, TOTL);
3583 sc->stats.toth += E1000_READ_REG(&sc->hw, TOTH);
3584
3585 sc->stats.tpr += E1000_READ_REG(&sc->hw, TPR);
3586 sc->stats.tpt += E1000_READ_REG(&sc->hw, TPT);
3587 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, PTC64);
3588 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, PTC127);
3589 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, PTC255);
3590 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, PTC511);
3591 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, PTC1023);
3592 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, PTC1522);
3593 sc->stats.mptc += E1000_READ_REG(&sc->hw, MPTC);
3594 sc->stats.bptc += E1000_READ_REG(&sc->hw, BPTC);
3595
3596 if (sc->hw.mac_type >= em_82543) {
3597 sc->stats.algnerrc +=
3598 E1000_READ_REG(&sc->hw, ALGNERRC);
3599 sc->stats.rxerrc +=
3600 E1000_READ_REG(&sc->hw, RXERRC);
3601 sc->stats.tncrs +=
3602 E1000_READ_REG(&sc->hw, TNCRS);
3603 sc->stats.cexterr +=
3604 E1000_READ_REG(&sc->hw, CEXTERR);
3605 sc->stats.tsctc +=
3606 E1000_READ_REG(&sc->hw, TSCTC);
3607 sc->stats.tsctfc +=
3608 E1000_READ_REG(&sc->hw, TSCTFC);
3609 }
3610 ifp = &sc->interface_data.ac_if;
3611
3612 /* Fill out the OS statistics structure */
3613 ifp->if_ibytes = sc->stats.gorcl;
3614 ifp->if_obytes = sc->stats.gotcl;
3615 ifp->if_imcasts = sc->stats.mprc;
3616 ifp->if_collisions = sc->stats.colc;
3617
3618 /* Rx Errors */
3619 ifp->if_ierrors =
3620 sc->dropped_pkts +
3621 sc->stats.rxerrc +
3622 sc->stats.crcerrs +
3623 sc->stats.algnerrc +
3624 sc->stats.rlec + sc->stats.rnbc +
3625 sc->stats.mpc + sc->stats.cexterr;
3626
3627 /* Tx Errors */
3628 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol;
3629
3630 }
3631
3632
3633 /**********************************************************************
3634 *
3635 * This routine is called only when em_display_debug_stats is enabled.
3636 * This routine provides a way to take a look at important statistics
3637 * maintained by the driver and hardware.
3638 *
3639 **********************************************************************/
3640 void
3641 em_print_debug_info(struct em_softc *sc)
3642 {
3643 const char * const unit = sc->sc_dv.dv_xname;
3644 uint8_t *hw_addr = sc->hw.hw_addr;
3645
3646 printf("%s: Adapter hardware address = %p \n", unit, hw_addr);
3647 printf("%s:tx_int_delay = %d, tx_abs_int_delay = %d\n", unit,
3648 E1000_READ_REG(&sc->hw, TIDV),
3649 E1000_READ_REG(&sc->hw, TADV));
3650 printf("%s:rx_int_delay = %d, rx_abs_int_delay = %d\n", unit,
3651 E1000_READ_REG(&sc->hw, RDTR),
3652 E1000_READ_REG(&sc->hw, RADV));
3653
3654 #ifdef DBG_STATS
3655 printf("%s: Packets not Avail = %ld\n", unit,
3656 sc->no_pkts_avail);
3657 printf("%s: CleanTxInterrupts = %ld\n", unit,
3658 sc->clean_tx_interrupts);
3659 #endif
3660 printf("%s: fifo workaround = %lld, fifo_reset = %lld\n", unit,
3661 (long long)sc->tx_fifo_wrk,
3662 (long long)sc->tx_fifo_reset);
3663 printf("%s: hw tdh = %d, hw tdt = %d\n", unit,
3664 E1000_READ_REG(&sc->hw, TDH),
3665 E1000_READ_REG(&sc->hw, TDT));
3666 printf("%s: Num Tx descriptors avail = %d\n", unit,
3667 sc->num_tx_desc_avail);
3668 printf("%s: Tx Descriptors not avail1 = %ld\n", unit,
3669 sc->no_tx_desc_avail1);
3670 printf("%s: Tx Descriptors not avail2 = %ld\n", unit,
3671 sc->no_tx_desc_avail2);
3672 printf("%s: Std mbuf failed = %ld\n", unit,
3673 sc->mbuf_alloc_failed);
3674 printf("%s: Std mbuf cluster failed = %ld\n", unit,
3675 sc->mbuf_cluster_failed);
3676 printf("%s: Driver dropped packets = %ld\n", unit,
3677 sc->dropped_pkts);
3678
3679 return;
3680 }
3681
3682 void
3683 em_print_hw_stats(struct em_softc *sc)
3684 {
3685 const char * const unit = sc->sc_dv.dv_xname;
3686
3687 printf("%s: Excessive collisions = %lld\n", unit,
3688 (long long)sc->stats.ecol);
3689 printf("%s: Symbol errors = %lld\n", unit,
3690 (long long)sc->stats.symerrs);
3691 printf("%s: Sequence errors = %lld\n", unit,
3692 (long long)sc->stats.sec);
3693 printf("%s: Defer count = %lld\n", unit,
3694 (long long)sc->stats.dc);
3695
3696 printf("%s: Missed Packets = %lld\n", unit,
3697 (long long)sc->stats.mpc);
3698 printf("%s: Receive No Buffers = %lld\n", unit,
3699 (long long)sc->stats.rnbc);
3700 printf("%s: Receive length errors = %lld\n", unit,
3701 (long long)sc->stats.rlec);
3702 printf("%s: Receive errors = %lld\n", unit,
3703 (long long)sc->stats.rxerrc);
3704 printf("%s: Crc errors = %lld\n", unit,
3705 (long long)sc->stats.crcerrs);
3706 printf("%s: Alignment errors = %lld\n", unit,
3707 (long long)sc->stats.algnerrc);
3708 printf("%s: Carrier extension errors = %lld\n", unit,
3709 (long long)sc->stats.cexterr);
3710
3711 printf("%s: XON Rcvd = %lld\n", unit,
3712 (long long)sc->stats.xonrxc);
3713 printf("%s: XON Xmtd = %lld\n", unit,
3714 (long long)sc->stats.xontxc);
3715 printf("%s: XOFF Rcvd = %lld\n", unit,
3716 (long long)sc->stats.xoffrxc);
3717 printf("%s: XOFF Xmtd = %lld\n", unit,
3718 (long long)sc->stats.xofftxc);
3719
3720 printf("%s: Good Packets Rcvd = %lld\n", unit,
3721 (long long)sc->stats.gprc);
3722 printf("%s: Good Packets Xmtd = %lld\n", unit,
3723 (long long)sc->stats.gptc);
3724
3725 return;
3726 }
3727
3728 #ifdef __FreeBSD__
3729 int
3730 em_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3731 {
3732 int error;
3733 int result;
3734 struct em_softc *sc;
3735
3736 result = -1;
3737 error = sysctl_handle_int(oidp, &result, 0, req);
3738
3739 if (error || !req->newptr)
3740 return (error);
3741
3742 if (result == 1) {
3743 sc = (struct em_softc *)arg1;
3744 em_print_debug_info(sc);
3745 }
3746
3747 return error;
3748 }
3749
3750
3751 int
3752 em_sysctl_stats(SYSCTL_HANDLER_ARGS)
3753 {
3754 int error;
3755 int result;
3756 struct em_softc *sc;
3757
3758 result = -1;
3759 error = sysctl_handle_int(oidp, &result, 0, req);
3760
3761 if (error || !req->newptr)
3762 return (error);
3763
3764 if (result == 1) {
3765 sc = (struct em_softc *)arg1;
3766 em_print_hw_stats(sc);
3767 }
3768
3769 return error;
3770 }
3771
3772 int
3773 em_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
3774 {
3775 struct em_int_delay_info *info;
3776 struct em_softc *sc;
3777 u_int32_t regval;
3778 int error;
3779 int usecs;
3780 int ticks;
3781 int s;
3782
3783 info = (struct em_int_delay_info *)arg1;
3784 sc = info->sc;
3785 usecs = info->value;
3786 error = sysctl_handle_int(oidp, &usecs, 0, req);
3787 if (error != 0 || req->newptr == NULL)
3788 return error;
3789 if (usecs < 0 || usecs > E1000_TICKS_TO_USECS(65535))
3790 return EINVAL;
3791 info->value = usecs;
3792 ticks = E1000_USECS_TO_TICKS(usecs);
3793
3794 s = splimp();
3795 regval = E1000_READ_OFFSET(&sc->hw, info->offset);
3796 regval = (regval & ~0xffff) | (ticks & 0xffff);
3797 /* Handle a few special cases. */
3798 switch (info->offset) {
3799 case E1000_RDTR:
3800 case E1000_82542_RDTR:
3801 regval |= E1000_RDT_FPDB;
3802 break;
3803 case E1000_TIDV:
3804 case E1000_82542_TIDV:
3805 if (ticks == 0) {
3806 sc->txd_cmd &= ~E1000_TXD_CMD_IDE;
3807 /* Don't write 0 into the TIDV register. */
3808 regval++;
3809 } else
3810 sc->txd_cmd |= E1000_TXD_CMD_IDE;
3811 break;
3812 }
3813 E1000_WRITE_OFFSET(&sc->hw, info->offset, regval);
3814 splx(s);
3815 return 0;
3816 }
3817
3818 void
3819 em_add_int_delay_sysctl(struct em_softc *sc, const char *name,
3820 const char *description, struct em_int_delay_info *info,
3821 int offset, int value)
3822 {
3823 info->sc = sc;
3824 info->offset = offset;
3825 info->value = value;
3826 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
3827 SYSCTL_CHILDREN(sc->sysctl_tree),
3828 OID_AUTO, name, CTLTYPE_INT|CTLFLAG_RW,
3829 info, 0, em_sysctl_int_delay, "I", description);
3830 }
3831 #endif /* __FreeBSD__ */
3832
3833