1 /** $MirOS: src/sys/dev/pci/cs4280.c,v 1.2 2005/03/06 21:27:47 tg Exp $ */
2 /* $OpenBSD: cs4280.c,v 1.20 2004/01/08 22:38:20 deraadt Exp $ */
3 /* $NetBSD: cs4280.c,v 1.5 2000/06/26 04:56:23 simonb Exp $ */
4
5 /*
6 * Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Tatoku Ogaito
19 * for the NetBSD Project.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * Cirrus Logic CS4280 (and maybe CS461x) driver.
37 * Data sheets can be found
38 * http://www.cirrus.com/ftp/pubs/4280.pdf
39 * http://www.cirrus.com/ftp/pubs/4297.pdf
40 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.pdf
41 * ftp://ftp.alsa-project.org/pub/manuals/cirrus/embedded_audio_spec.doc
42 */
43
44 /*
45 * TODO
46 * Implement MIDI
47 * Joystick support
48 */
49
50 #ifdef CS4280_DEBUG
51 #ifndef MIDI_READY
52 #define MIDI_READY
53 #endif /* ! MIDI_READY */
54 #endif
55
56 #ifdef MIDI_READY
57 #include "midi.h"
58 #endif
59
60 #if defined(CS4280_DEBUG)
61 #define DPRINTF(x) if (cs4280debug) printf x
62 #define DPRINTFN(n,x) if (cs4280debug>(n)) printf x
63 int cs4280debug = 0;
64 #else
65 #define DPRINTF(x)
66 #define DPRINTFN(n,x)
67 #endif
68
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/kernel.h>
72 #include <sys/fcntl.h>
73 #include <sys/malloc.h>
74 #include <sys/device.h>
75
76 #include <dev/pci/pcidevs.h>
77 #include <dev/pci/pcivar.h>
78 #include <dev/pci/cs4280reg.h>
79 #include <dev/microcode/cirruslogic/cs4280_image.h>
80
81 #include <sys/audioio.h>
82 #include <dev/audio_if.h>
83 #include <dev/midi_if.h>
84 #include <dev/mulaw.h>
85 #include <dev/auconv.h>
86
87 #include <dev/ic/ac97.h>
88
89 #include <machine/bus.h>
90
91 #define CSCC_PCI_BA0 0x10
92 #define CSCC_PCI_BA1 0x14
93
94 struct cs4280_dma {
95 bus_dmamap_t map;
96 caddr_t addr; /* real dma buffer */
97 caddr_t dum; /* dummy buffer for audio driver */
98 bus_dma_segment_t segs[1];
99 int nsegs;
100 size_t size;
101 struct cs4280_dma *next;
102 };
103 #define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
104 #define BUFADDR(p) ((void *)((p)->dum))
105 #define KERNADDR(p) ((void *)((p)->addr))
106
107 /*
108 * Software state
109 */
110 struct cs4280_softc {
111 struct device sc_dev;
112
113 pci_intr_handle_t * sc_ih;
114
115 /* I/O (BA0) */
116 bus_space_tag_t ba0t;
117 bus_space_handle_t ba0h;
118
119 /* BA1 */
120 bus_space_tag_t ba1t;
121 bus_space_handle_t ba1h;
122
123 /* DMA */
124 bus_dma_tag_t sc_dmatag;
125 struct cs4280_dma *sc_dmas;
126
127 void (*sc_pintr)(void *); /* dma completion intr handler */
128 void *sc_parg; /* arg for sc_intr() */
129 char *sc_ps, *sc_pe, *sc_pn;
130 int sc_pcount;
131 int sc_pi;
132 struct cs4280_dma *sc_pdma;
133 char *sc_pbuf;
134 #ifdef DIAGNOSTIC
135 char sc_prun;
136 #endif
137
138 void (*sc_rintr)(void *); /* dma completion intr handler */
139 void *sc_rarg; /* arg for sc_intr() */
140 char *sc_rs, *sc_re, *sc_rn;
141 int sc_rcount;
142 int sc_ri;
143 struct cs4280_dma *sc_rdma;
144 char *sc_rbuf;
145 int sc_rparam; /* record format */
146 #ifdef DIAGNOSTIC
147 char sc_rrun;
148 #endif
149
150 #if NMIDI > 0
151 void (*sc_iintr)(void *, int); /* midi input ready handler */
152 void (*sc_ointr)(void *); /* midi output ready handler */
153 void *sc_arg;
154 #endif
155
156 u_int32_t pctl;
157 u_int32_t cctl;
158
159 struct ac97_codec_if *codec_if;
160 struct ac97_host_if host_if;
161
162 char sc_suspend;
163 void *sc_powerhook; /* Power Hook */
164 u_int16_t ac97_reg[CS4280_SAVE_REG_MAX + 1]; /* Save ac97 registers */
165 };
166
167 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r))
168 #define BA0WRITE4(sc, r, x) bus_space_write_4((sc)->ba0t, (sc)->ba0h, (r), (x))
169 #define BA1READ4(sc, r) bus_space_read_4((sc)->ba1t, (sc)->ba1h, (r))
170 #define BA1WRITE4(sc, r, x) bus_space_write_4((sc)->ba1t, (sc)->ba1h, (r), (x))
171
172 int cs4280_match(struct device *, void *, void *);
173 void cs4280_attach(struct device *, struct device *, void *);
174 int cs4280_intr(void *);
175 void cs4280_reset(void *);
176 int cs4280_download_image(struct cs4280_softc *);
177
178 int cs4280_download(struct cs4280_softc *, const u_int32_t *, u_int32_t, u_int32_t);
179 int cs4280_allocmem(struct cs4280_softc *, size_t, size_t,
180 struct cs4280_dma *);
181 int cs4280_freemem(struct cs4280_softc *, struct cs4280_dma *);
182
183 #ifdef CS4280_DEBUG
184 int cs4280_check_images(struct cs4280_softc *);
185 int cs4280_checkimage(struct cs4280_softc *, u_int32_t *, u_int32_t,
186 u_int32_t);
187 #endif
188
189 struct cfdriver clcs_cd = {
190 NULL, "clcs", DV_DULL
191 };
192
193 struct cfattach clcs_ca = {
194 sizeof(struct cs4280_softc), cs4280_match, cs4280_attach
195 };
196
197 int cs4280_init(struct cs4280_softc *, int);
198 int cs4280_open(void *, int);
199 void cs4280_close(void *);
200
201 int cs4280_query_encoding(void *, struct audio_encoding *);
202 int cs4280_set_params(void *, int, int, struct audio_params *, struct audio_params *);
203 int cs4280_round_blocksize(void *, int);
204
205 int cs4280_halt_output(void *);
206 int cs4280_halt_input(void *);
207
208 int cs4280_getdev(void *, struct audio_device *);
209
210 int cs4280_mixer_set_port(void *, mixer_ctrl_t *);
211 int cs4280_mixer_get_port(void *, mixer_ctrl_t *);
212 int cs4280_query_devinfo(void *addr, mixer_devinfo_t *dip);
213 void *cs4280_malloc(void *, int, size_t, int, int);
214 void cs4280_free(void *, void *, int);
215 size_t cs4280_round_buffersize(void *, int, size_t);
216 paddr_t cs4280_mappage(void *, void *, off_t, int);
217 int cs4280_get_props(void *);
218 int cs4280_trigger_output(void *, void *, void *, int, void (*)(void *),
219 void *, struct audio_params *);
220 int cs4280_trigger_input(void *, void *, void *, int, void (*)(void *),
221 void *, struct audio_params *);
222
223
224 void cs4280_set_dac_rate(struct cs4280_softc *, int );
225 void cs4280_set_adc_rate(struct cs4280_softc *, int );
226 int cs4280_get_portnum_by_name(struct cs4280_softc *, char *, char *,
227 char *);
228 int cs4280_src_wait(struct cs4280_softc *);
229 int cs4280_attach_codec(void *sc, struct ac97_codec_if *);
230 int cs4280_read_codec(void *sc, u_int8_t a, u_int16_t *d);
231 int cs4280_write_codec(void *sc, u_int8_t a, u_int16_t d);
232 void cs4280_reset_codec(void *sc);
233
234 void cs4280_power(int, void *);
235
236 void cs4280_clear_fifos(struct cs4280_softc *);
237
238 #if NMIDI > 0
239 void cs4280_midi_close(void *);
240 void cs4280_midi_getinfo(void *, struct midi_info *);
241 int cs4280_midi_open(void *, int, void (*)(void *, int),
242 void (*)(void *), void *);
243 int cs4280_midi_output(void *, int);
244 #endif
245
246 struct audio_hw_if cs4280_hw_if = {
247 cs4280_open,
248 cs4280_close,
249 NULL,
250 cs4280_query_encoding,
251 cs4280_set_params,
252 cs4280_round_blocksize,
253 NULL,
254 NULL,
255 NULL,
256 NULL,
257 NULL,
258 cs4280_halt_output,
259 cs4280_halt_input,
260 NULL,
261 cs4280_getdev,
262 NULL,
263 cs4280_mixer_set_port,
264 cs4280_mixer_get_port,
265 cs4280_query_devinfo,
266 cs4280_malloc,
267 cs4280_free,
268 cs4280_round_buffersize,
269 0, /* cs4280_mappage, */
270 cs4280_get_props,
271 cs4280_trigger_output,
272 cs4280_trigger_input,
273 };
274
275 #if NMIDI > 0
276 struct midi_hw_if cs4280_midi_hw_if = {
277 cs4280_midi_open,
278 cs4280_midi_close,
279 cs4280_midi_output,
280 cs4280_midi_getinfo,
281 0,
282 };
283 #endif
284
285
286
287 struct audio_device cs4280_device = {
288 "CS4280",
289 "",
290 "cs4280"
291 };
292
293 const struct pci_matchid cs4280_devices[] = {
294 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4280 },
295 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4610 },
296 { PCI_VENDOR_CIRRUS, PCI_PRODUCT_CIRRUS_CS4615 },
297 };
298
299 int
cs4280_match(parent,ma,aux)300 cs4280_match(parent, ma, aux)
301 struct device *parent;
302 void *ma;
303 void *aux;
304 {
305 return (pci_matchbyid((struct pci_attach_args *)aux, cs4280_devices,
306 sizeof(cs4280_devices)/sizeof(cs4280_devices[0])));
307 }
308
309 int
cs4280_read_codec(sc_,add,data)310 cs4280_read_codec(sc_, add, data)
311 void *sc_;
312 u_int8_t add;
313 u_int16_t *data;
314 {
315 struct cs4280_softc *sc = sc_;
316 int n;
317
318 DPRINTFN(5,("read_codec: add=0x%02x ", add));
319 /*
320 * Make sure that there is not data sitting around from a preivous
321 * uncompleted access.
322 */
323 BA0READ4(sc, CS4280_ACSDA);
324
325 /* Set up AC97 control registers. */
326 BA0WRITE4(sc, CS4280_ACCAD, add);
327 BA0WRITE4(sc, CS4280_ACCDA, 0);
328 BA0WRITE4(sc, CS4280_ACCTL,
329 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_CRW | ACCTL_DCV );
330
331 if (cs4280_src_wait(sc) < 0) {
332 printf("%s: AC97 read prob. (DCV!=0) for add=0x%02x\n",
333 sc->sc_dev.dv_xname, add);
334 return (1);
335 }
336
337 /* wait for valid status bit is active */
338 n = 0;
339 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) {
340 delay(1);
341 while (++n > 1000) {
342 printf("%s: AC97 read fail (VSTS==0) for add=0x%02x\n",
343 sc->sc_dev.dv_xname, add);
344 return (1);
345 }
346 }
347 *data = BA0READ4(sc, CS4280_ACSDA);
348 DPRINTFN(5,("data=0x%04x\n", *data));
349 return (0);
350 }
351
352 int
cs4280_write_codec(sc_,add,data)353 cs4280_write_codec(sc_, add, data)
354 void *sc_;
355 u_int8_t add;
356 u_int16_t data;
357 {
358 struct cs4280_softc *sc = sc_;
359
360 DPRINTFN(5,("write_codec: add=0x%02x data=0x%04x\n", add, data));
361 BA0WRITE4(sc, CS4280_ACCAD, add);
362 BA0WRITE4(sc, CS4280_ACCDA, data);
363 BA0WRITE4(sc, CS4280_ACCTL,
364 ACCTL_RSTN | ACCTL_ESYN | ACCTL_VFRM | ACCTL_DCV );
365
366 if (cs4280_src_wait(sc) < 0) {
367 printf("%s: AC97 write fail (DCV!=0) for add=0x%02x data="
368 "0x%04x\n", sc->sc_dev.dv_xname, add, data);
369 return (1);
370 }
371 return (0);
372 }
373
374 int
cs4280_src_wait(sc)375 cs4280_src_wait(sc)
376 struct cs4280_softc *sc;
377 {
378 int n;
379 n = 0;
380 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) {
381 delay(1000);
382 while (++n > 1000)
383 return (-1);
384 }
385 return (0);
386 }
387
388
389 void
cs4280_set_adc_rate(sc,rate)390 cs4280_set_adc_rate(sc, rate)
391 struct cs4280_softc *sc;
392 int rate;
393 {
394 /* calculate capture rate:
395 *
396 * capture_coefficient_increment = -round(rate*128*65536/48000;
397 * capture_phase_increment = floor(48000*65536*1024/rate);
398 * cx = round(48000*65536*1024 - capture_phase_increment*rate);
399 * cy = floor(cx/200);
400 * capture_sample_rate_correction = cx - 200*cy;
401 * capture_delay = ceil(24*48000/rate);
402 * capture_num_triplets = floor(65536*rate/24000);
403 * capture_group_length = 24000/GCD(rate, 24000);
404 * where GCD means "Greatest Common Divisor".
405 *
406 * capture_coefficient_increment, capture_phase_increment and
407 * capture_num_triplets are 32-bit signed quantities.
408 * capture_sample_rate_correction and capture_group_length are
409 * 16-bit signed quantities.
410 * capture_delay is a 14-bit unsigned quantity.
411 */
412 u_int32_t cci,cpi,cnt,cx,cy, tmp1;
413 u_int16_t csrc, cgl, cdlay;
414
415 /* XXX
416 * Even though, embedded_audio_spec says capture rate range 11025 to
417 * 48000, dhwiface.cpp says,
418 *
419 * "We can only decimate by up to a factor of 1/9th the hardware rate.
420 * Return an error if an attempt is made to stray outside that limit."
421 *
422 * so assume range as 48000/9 to 48000
423 */
424
425 if (rate < 8000)
426 rate = 8000;
427 if (rate > 48000)
428 rate = 48000;
429
430 cx = rate << 16;
431 cci = cx / 48000;
432 cx -= cci * 48000;
433 cx <<= 7;
434 cci <<= 7;
435 cci += cx / 48000;
436 cci = - cci;
437
438 cx = 48000 << 16;
439 cpi = cx / rate;
440 cx -= cpi * rate;
441 cx <<= 10;
442 cpi <<= 10;
443 cy = cx / rate;
444 cpi += cy;
445 cx -= cy * rate;
446
447 cy = cx / 200;
448 csrc = cx - 200*cy;
449
450 cdlay = ((48000 * 24) + rate - 1) / rate;
451 #if 0
452 cdlay &= 0x3fff; /* make sure cdlay is 14-bit */
453 #endif
454
455 cnt = rate << 16;
456 cnt /= 24000;
457
458 cgl = 1;
459 for (tmp1 = 2; tmp1 <= 64; tmp1 *= 2) {
460 if (((rate / tmp1) * tmp1) != rate)
461 cgl *= 2;
462 }
463 if (((rate / 3) * 3) != rate)
464 cgl *= 3;
465 for (tmp1 = 5; tmp1 <= 125; tmp1 *= 5) {
466 if (((rate / tmp1) * tmp1) != rate)
467 cgl *= 5;
468 }
469 #if 0
470 /* XXX what manual says */
471 tmp1 = BA1READ4(sc, CS4280_CSRC) & ~CSRC_MASK;
472 tmp1 |= csrc<<16;
473 BA1WRITE4(sc, CS4280_CSRC, tmp1);
474 #else
475 /* suggested by cs461x.c (ALSA driver) */
476 BA1WRITE4(sc, CS4280_CSRC, CS4280_MK_CSRC(csrc, cy));
477 #endif
478
479 #if 0
480 /* I am confused. The sample rate calculation section says
481 * cci *is* 32-bit signed quantity but in the parameter description
482 * section, CCI only assigned 16bit.
483 * I believe size of the variable.
484 */
485 tmp1 = BA1READ4(sc, CS4280_CCI) & ~CCI_MASK;
486 tmp1 |= cci<<16;
487 BA1WRITE4(sc, CS4280_CCI, tmp1);
488 #else
489 BA1WRITE4(sc, CS4280_CCI, cci);
490 #endif
491
492 tmp1 = BA1READ4(sc, CS4280_CD) & ~CD_MASK;
493 tmp1 |= cdlay <<18;
494 BA1WRITE4(sc, CS4280_CD, tmp1);
495
496 BA1WRITE4(sc, CS4280_CPI, cpi);
497
498 tmp1 = BA1READ4(sc, CS4280_CGL) & ~CGL_MASK;
499 tmp1 |= cgl;
500 BA1WRITE4(sc, CS4280_CGL, tmp1);
501
502 BA1WRITE4(sc, CS4280_CNT, cnt);
503
504 tmp1 = BA1READ4(sc, CS4280_CGC) & ~CGC_MASK;
505 tmp1 |= cgl;
506 BA1WRITE4(sc, CS4280_CGC, tmp1);
507 }
508
509 void
cs4280_set_dac_rate(sc,rate)510 cs4280_set_dac_rate(sc, rate)
511 struct cs4280_softc *sc;
512 int rate;
513 {
514 /*
515 * playback rate may range from 8000Hz to 48000Hz
516 *
517 * play_phase_increment = floor(rate*65536*1024/48000)
518 * px = round(rate*65536*1024 - play_phase_incremnt*48000)
519 * py=floor(px/200)
520 * play_sample_rate_correction = px - 200*py
521 *
522 * play_phase_increment is a 32bit signed quantity.
523 * play_sample_rate_correction is a 16bit signed quantity.
524 */
525 int32_t ppi;
526 int16_t psrc;
527 u_int32_t px, py;
528
529 if (rate < 8000)
530 rate = 8000;
531 if (rate > 48000)
532 rate = 48000;
533 px = rate << 16;
534 ppi = px/48000;
535 px -= ppi*48000;
536 ppi <<= 10;
537 px <<= 10;
538 py = px / 48000;
539 ppi += py;
540 px -= py*48000;
541 py = px/200;
542 px -= py*200;
543 psrc = px;
544 #if 0
545 /* what manual says */
546 px = BA1READ4(sc, CS4280_PSRC) & ~PSRC_MASK;
547 BA1WRITE4(sc, CS4280_PSRC,
548 ( ((psrc<<16) & PSRC_MASK) | px ));
549 #else
550 /* suggested by cs461x.c (ALSA driver) */
551 BA1WRITE4(sc, CS4280_PSRC, CS4280_MK_PSRC(psrc,py));
552 #endif
553 BA1WRITE4(sc, CS4280_PPI, ppi);
554 }
555
556 void
cs4280_attach(parent,self,aux)557 cs4280_attach(parent, self, aux)
558 struct device *parent;
559 struct device *self;
560 void *aux;
561 {
562 struct cs4280_softc *sc = (struct cs4280_softc *) self;
563 struct pci_attach_args *pa = (struct pci_attach_args *) aux;
564 pci_chipset_tag_t pc = pa->pa_pc;
565 char const *intrstr;
566 pci_intr_handle_t ih;
567 mixer_ctrl_t ctl;
568 u_int32_t mem;
569
570 /* Map I/O register */
571 if (pci_mapreg_map(pa, CSCC_PCI_BA0,
572 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
573 &sc->ba0t, &sc->ba0h, NULL, NULL, 0)) {
574 printf(": can't map BA0 space\n");
575 return;
576 }
577 if (pci_mapreg_map(pa, CSCC_PCI_BA1,
578 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0,
579 &sc->ba1t, &sc->ba1h, NULL, NULL, 0)) {
580 printf(": can't map BA1 space\n");
581 return;
582 }
583
584 sc->sc_dmatag = pa->pa_dmat;
585
586 /* Enable the device (set bus master flag) */
587 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
588 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
589 PCI_COMMAND_MASTER_ENABLE);
590
591 /* LATENCY_TIMER setting */
592 mem = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG);
593 if ( PCI_LATTIMER(mem) < 32 ) {
594 mem &= 0xffff00ff;
595 mem |= 0x00002000;
596 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, mem);
597 }
598
599 /* Map and establish the interrupt. */
600 if (pci_intr_map(pa, &ih)) {
601 printf(": couldn't map interrupt\n");
602 return;
603 }
604 intrstr = pci_intr_string(pc, ih);
605
606 sc->sc_ih = pci_intr_establish(pc, ih, IPL_AUDIO, cs4280_intr, sc,
607 sc->sc_dev.dv_xname);
608 if (sc->sc_ih == NULL) {
609 printf(": couldn't establish interrupt");
610 if (intrstr != NULL)
611 printf(" at %s", intrstr);
612 printf("\n");
613 return;
614 }
615 printf(": %s\n", intrstr);
616
617 /* Initialization */
618 if(cs4280_init(sc, 1) != 0)
619 return;
620
621 /* AC 97 attachement */
622 sc->host_if.arg = sc;
623 sc->host_if.attach = cs4280_attach_codec;
624 sc->host_if.read = cs4280_read_codec;
625 sc->host_if.write = cs4280_write_codec;
626 sc->host_if.reset = cs4280_reset_codec;
627
628 if (ac97_attach(&sc->host_if) != 0) {
629 printf("%s: ac97_attach failed\n", sc->sc_dev.dv_xname);
630 return;
631 }
632
633 /* Turn mute off of DAC, CD and master volumes by default */
634 ctl.type = AUDIO_MIXER_ENUM;
635 ctl.un.ord = 0; /* off */
636
637 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCoutputs,
638 AudioNmaster, AudioNmute);
639 cs4280_mixer_set_port(sc, &ctl);
640
641 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs,
642 AudioNdac, AudioNmute);
643 cs4280_mixer_set_port(sc, &ctl);
644
645 ctl.dev = cs4280_get_portnum_by_name(sc, AudioCinputs,
646 AudioNcd, AudioNmute);
647 cs4280_mixer_set_port(sc, &ctl);
648
649 audio_attach_mi(&cs4280_hw_if, sc, &sc->sc_dev);
650
651 #if NMIDI > 0
652 midi_attach_mi(&cs4280_midi_hw_if, sc, &sc->sc_dev);
653 #endif
654 sc->sc_suspend = PWR_RESUME;
655 sc->sc_powerhook = powerhook_establish(cs4280_power, sc);
656 }
657
658 int
cs4280_intr(p)659 cs4280_intr(p)
660 void *p;
661 {
662 /*
663 * XXX
664 *
665 * Since CS4280 has only 4kB dma buffer and
666 * interrupt occurs every 2kB block, I create dummy buffer
667 * which returns to audio driver and actual dma buffer
668 * using in DMA transfer.
669 *
670 *
671 * ring buffer in audio.c is pointed by BUFADDR
672 * <------ ring buffer size == 64kB ------>
673 * <-----> blksize == 2048*(sc->sc_[pr]count) kB
674 * |= = = =|= = = =|= = = =|= = = =|= = = =|
675 * | | | | | | <- call audio_intp every
676 * sc->sc_[pr]_count time.
677 *
678 * actual dma buffer is pointed by KERNADDR
679 * <-> dma buffer size = 4kB
680 * |= =|
681 *
682 *
683 */
684 struct cs4280_softc *sc = p;
685 u_int32_t intr, mem;
686 char * empty_dma;
687 int handled = 0;
688
689 /* grab interrupt register then clear it */
690 intr = BA0READ4(sc, CS4280_HISR);
691 BA0WRITE4(sc, CS4280_HICR, HICR_CHGM | HICR_IEV);
692
693 /* Playback Interrupt */
694 if (intr & HISR_PINT) {
695 handled = 1;
696 mem = BA1READ4(sc, CS4280_PFIE);
697 BA1WRITE4(sc, CS4280_PFIE, (mem & ~PFIE_PI_MASK) | PFIE_PI_DISABLE);
698 if (sc->sc_pintr) {
699 if ((sc->sc_pi%sc->sc_pcount) == 0)
700 sc->sc_pintr(sc->sc_parg);
701 } else {
702 printf("unexpected play intr\n");
703 }
704 /* copy buffer */
705 ++sc->sc_pi;
706 empty_dma = sc->sc_pdma->addr;
707 if (sc->sc_pi&1)
708 empty_dma += CS4280_ICHUNK;
709 memcpy(empty_dma, sc->sc_pn, CS4280_ICHUNK);
710 sc->sc_pn += CS4280_ICHUNK;
711 if (sc->sc_pn >= sc->sc_pe)
712 sc->sc_pn = sc->sc_ps;
713 BA1WRITE4(sc, CS4280_PFIE, mem);
714 }
715 /* Capture Interrupt */
716 if (intr & HISR_CINT) {
717 int i;
718 int16_t rdata;
719
720 handled = 1;
721 mem = BA1READ4(sc, CS4280_CIE);
722 BA1WRITE4(sc, CS4280_CIE, (mem & ~CIE_CI_MASK) | CIE_CI_DISABLE);
723 ++sc->sc_ri;
724 empty_dma = sc->sc_rdma->addr;
725 if ((sc->sc_ri&1) == 0)
726 empty_dma += CS4280_ICHUNK;
727
728 /*
729 * XXX
730 * I think this audio data conversion should be
731 * happend in upper layer, but I put this here
732 * since there is no conversion function available.
733 */
734 switch(sc->sc_rparam) {
735 case CF_16BIT_STEREO:
736 /* just copy it */
737 memcpy(sc->sc_rn, empty_dma, CS4280_ICHUNK);
738 sc->sc_rn += CS4280_ICHUNK;
739 break;
740 case CF_16BIT_MONO:
741 {
742 int16_t *tmp1 = (int16_t *)sc->sc_rn;
743 int16_t *tmp2 = (int16_t *)empty_dma;
744
745 for (i = 0; i < 512; i++) {
746 rdata = *tmp2++ >> 1;
747 rdata += *tmp2++ >> 1;
748 *tmp1++ = rdata;
749 }
750 sc->sc_rn = (char *)tmp1;
751 empty_dma = (char *)tmp2;
752 }
753 break;
754 case CF_8BIT_STEREO:
755 {
756 int16_t *tmp2 = (int16_t *)empty_dma;
757
758 for (i = 0; i < 512; i++) {
759 rdata = *tmp2++;
760 *sc->sc_rn++ = rdata >> 8;
761 rdata = *tmp2++;
762 *sc->sc_rn++ = rdata >> 8;
763 }
764 empty_dma = (char *)tmp2;
765 }
766 break;
767 case CF_8BIT_MONO:
768 {
769 int16_t *tmp2 = (int16_t *)empty_dma;
770
771 for (i = 0; i < 512; i++) {
772 rdata = *tmp2++ >> 1;
773 rdata += *tmp2++ >> 1;
774 *sc->sc_rn++ = rdata >>8;
775 }
776 break;
777 empty_dma = (char *)tmp2;
778 }
779 default:
780 /* Should not reach here */
781 printf("unknown sc->sc_rparam: %d\n", sc->sc_rparam);
782 }
783 if (sc->sc_rn >= sc->sc_re)
784 sc->sc_rn = sc->sc_rs;
785 BA1WRITE4(sc, CS4280_CIE, mem);
786 if (sc->sc_rintr) {
787 if ((sc->sc_ri%(sc->sc_rcount)) == 0)
788 sc->sc_rintr(sc->sc_rarg);
789 } else {
790 printf("unexpected record intr\n");
791 }
792 }
793
794 #if NMIDI > 0
795 /* Midi port Interrupt */
796 if (intr & HISR_MIDI) {
797 int data;
798
799 handled = 1;
800 DPRINTF(("i: %d: ",
801 BA0READ4(sc, CS4280_MIDSR)));
802 /* Read the received data */
803 while ((sc->sc_iintr != NULL) &&
804 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) {
805 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK;
806 DPRINTF(("r:%x\n",data));
807 sc->sc_iintr(sc->sc_arg, data);
808 }
809
810 /* Write the data */
811 #if 1
812 /* XXX:
813 * It seems "Transmit Buffer Full" never activate until EOI
814 * is deliverd. Shall I throw EOI top of this routine ?
815 */
816 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
817 DPRINTF(("w: "));
818 if (sc->sc_ointr != NULL)
819 sc->sc_ointr(sc->sc_arg);
820 }
821 #else
822 while ((sc->sc_ointr != NULL) &&
823 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0)) {
824 DPRINTF(("w: "));
825 sc->sc_ointr(sc->sc_arg);
826 }
827 #endif
828 DPRINTF(("\n"));
829 }
830 #endif
831
832 return handled;
833 }
834
835
836 /* Download Proceessor Code and Data image */
837
838 int
cs4280_download(sc,src,offset,len)839 cs4280_download(sc, src, offset, len)
840 struct cs4280_softc *sc;
841 const u_int32_t *src;
842 u_int32_t offset, len;
843 {
844 u_int32_t ctr;
845
846 #ifdef CS4280_DEBUG
847 u_int32_t con, data;
848 u_int8_t c0,c1,c2,c3;
849 #endif
850 if ((offset&3) || (len&3))
851 return (-1);
852
853 len /= sizeof(u_int32_t);
854 for (ctr = 0; ctr < len; ctr++) {
855 /* XXX:
856 * I cannot confirm this is the right thing or not
857 * on BIG-ENDIAN machines.
858 */
859 BA1WRITE4(sc, offset+ctr*4, htole32(*(src+ctr)));
860 #ifdef CS4280_DEBUG
861 data = htole32(*(src+ctr));
862 c0 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+0);
863 c1 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+1);
864 c2 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+2);
865 c3 = bus_space_read_1(sc->ba1t, sc->ba1h, offset+ctr*4+3);
866 con = ( (c3<<24) | (c2<<16) | (c1<<8) | c0 );
867 if (data != con ) {
868 printf("0x%06x: write=0x%08x read=0x%08x\n",
869 offset+ctr*4, data, con);
870 return (-1);
871 }
872 #endif
873 }
874 return (0);
875 }
876
877 int
cs4280_download_image(sc)878 cs4280_download_image(sc)
879 struct cs4280_softc *sc;
880 {
881 int idx, err;
882 u_int32_t offset = 0;
883
884 err = 0;
885
886 for (idx = 0; idx < BA1_MEMORY_COUNT; ++idx) {
887 err = cs4280_download(sc, &BA1Struct.map[offset],
888 BA1Struct.memory[idx].offset,
889 BA1Struct.memory[idx].size);
890 if (err != 0) {
891 printf("%s: load_image failed at %d\n",
892 sc->sc_dev.dv_xname, idx);
893 return (-1);
894 }
895 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t);
896 }
897 return (err);
898 }
899
900 #ifdef CS4280_DEBUG
901 int
cs4280_checkimage(sc,src,offset,len)902 cs4280_checkimage(sc, src, offset, len)
903 struct cs4280_softc *sc;
904 u_int32_t *src;
905 u_int32_t offset, len;
906 {
907 u_int32_t ctr, data;
908 int err = 0;
909
910 if ((offset&3) || (len&3))
911 return -1;
912
913 len /= sizeof(u_int32_t);
914 for (ctr = 0; ctr < len; ctr++) {
915 /* I cannot confirm this is the right thing
916 * on BIG-ENDIAN machines
917 */
918 data = BA1READ4(sc, offset+ctr*4);
919 if (data != htole32(*(src+ctr))) {
920 printf("0x%06x: 0x%08x(0x%08x)\n",
921 offset+ctr*4, data, *(src+ctr));
922 *(src+ctr) = data;
923 ++err;
924 }
925 }
926 return (err);
927 }
928
929 int
cs4280_check_images(sc)930 cs4280_check_images(sc)
931 struct cs4280_softc *sc;
932 {
933 int idx, err;
934 u_int32_t offset = 0;
935
936 err = 0;
937 /*for (idx=0; idx < BA1_MEMORY_COUNT; ++idx) { */
938 for (idx = 0; idx < 1; ++idx) {
939 err = cs4280_checkimage(sc, &BA1Struct.map[offset],
940 BA1Struct.memory[idx].offset,
941 BA1Struct.memory[idx].size);
942 if (err != 0) {
943 printf("%s: check_image failed at %d\n",
944 sc->sc_dev.dv_xname, idx);
945 }
946 offset += BA1Struct.memory[idx].size / sizeof(u_int32_t);
947 }
948 return (err);
949 }
950
951 #endif
952
953 int
cs4280_attach_codec(sc_,codec_if)954 cs4280_attach_codec(sc_, codec_if)
955 void *sc_;
956 struct ac97_codec_if *codec_if;
957 {
958 struct cs4280_softc *sc = sc_;
959
960 sc->codec_if = codec_if;
961 return (0);
962 }
963
964 void
cs4280_reset_codec(sc_)965 cs4280_reset_codec(sc_)
966 void *sc_;
967 {
968 struct cs4280_softc *sc = sc_;
969 int n;
970
971 /* Reset codec */
972 BA0WRITE4(sc, CS4280_ACCTL, 0);
973 delay(100); /* delay 100us */
974 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN);
975
976 /*
977 * It looks like we do the following procedure, too
978 */
979
980 /* Enable AC-link sync generation */
981 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
982 delay(50*1000); /* XXX delay 50ms */
983
984 /* Assert valid frame signal */
985 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
986
987 /* Wait for valid AC97 input slot */
988 n = 0;
989 while (BA0READ4(sc, CS4280_ACISV) != (ACISV_ISV3 | ACISV_ISV4)) {
990 delay(1000);
991 if (++n > 1000) {
992 printf("reset_codec: AC97 inputs slot ready timeout\n");
993 return;
994 }
995 }
996 }
997
998
999 /* Processor Soft Reset */
1000 void
cs4280_reset(sc_)1001 cs4280_reset(sc_)
1002 void *sc_;
1003 {
1004 struct cs4280_softc *sc = sc_;
1005
1006 /* Set RSTSP bit in SPCR (also clear RUN, RUNFR, and DRQEN) */
1007 BA1WRITE4(sc, CS4280_SPCR, SPCR_RSTSP);
1008 delay(100);
1009 /* Clear RSTSP bit in SPCR */
1010 BA1WRITE4(sc, CS4280_SPCR, 0);
1011 /* enable DMA reqest */
1012 BA1WRITE4(sc, CS4280_SPCR, SPCR_DRQEN);
1013 }
1014
1015 int
cs4280_open(addr,flags)1016 cs4280_open(addr, flags)
1017 void *addr;
1018 int flags;
1019 {
1020 return (0);
1021 }
1022
1023 void
cs4280_close(addr)1024 cs4280_close(addr)
1025 void *addr;
1026 {
1027 struct cs4280_softc *sc = addr;
1028
1029 cs4280_halt_output(sc);
1030 cs4280_halt_input(sc);
1031
1032 sc->sc_pintr = 0;
1033 sc->sc_rintr = 0;
1034 }
1035
1036 int
cs4280_query_encoding(addr,fp)1037 cs4280_query_encoding(addr, fp)
1038 void *addr;
1039 struct audio_encoding *fp;
1040 {
1041 switch (fp->index) {
1042 case 0:
1043 strlcpy(fp->name, AudioEulinear, sizeof fp->name);
1044 fp->encoding = AUDIO_ENCODING_ULINEAR;
1045 fp->precision = 8;
1046 fp->flags = 0;
1047 break;
1048 case 1:
1049 strlcpy(fp->name, AudioEmulaw, sizeof fp->name);
1050 fp->encoding = AUDIO_ENCODING_ULAW;
1051 fp->precision = 8;
1052 fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
1053 break;
1054 case 2:
1055 strlcpy(fp->name, AudioEalaw, sizeof fp->name);
1056 fp->encoding = AUDIO_ENCODING_ALAW;
1057 fp->precision = 8;
1058 fp->flags = AUDIO_ENCODINGFLAG_EMULATED;
1059 break;
1060 case 3:
1061 strlcpy(fp->name, AudioEslinear, sizeof fp->name);
1062 fp->encoding = AUDIO_ENCODING_SLINEAR;
1063 fp->precision = 8;
1064 fp->flags = 0;
1065 break;
1066 case 4:
1067 strlcpy(fp->name, AudioEslinear_le, sizeof fp->name);
1068 fp->encoding = AUDIO_ENCODING_SLINEAR_LE;
1069 fp->precision = 16;
1070 fp->flags = 0;
1071 break;
1072 case 5:
1073 strlcpy(fp->name, AudioEulinear_le, sizeof fp->name);
1074 fp->encoding = AUDIO_ENCODING_ULINEAR_LE;
1075 fp->precision = 16;
1076 fp->flags = 0;
1077 break;
1078 case 6:
1079 strlcpy(fp->name, AudioEslinear_be, sizeof fp->name);
1080 fp->encoding = AUDIO_ENCODING_SLINEAR_BE;
1081 fp->precision = 16;
1082 fp->flags = 0;
1083 break;
1084 case 7:
1085 strlcpy(fp->name, AudioEulinear_be, sizeof fp->name);
1086 fp->encoding = AUDIO_ENCODING_ULINEAR_BE;
1087 fp->precision = 16;
1088 fp->flags = 0;
1089 break;
1090 default:
1091 return (EINVAL);
1092 }
1093 return (0);
1094 }
1095
1096 int
cs4280_set_params(addr,setmode,usemode,play,rec)1097 cs4280_set_params(addr, setmode, usemode, play, rec)
1098 void *addr;
1099 int setmode, usemode;
1100 struct audio_params *play, *rec;
1101 {
1102 struct cs4280_softc *sc = addr;
1103 struct audio_params *p;
1104 int mode;
1105
1106 for (mode = AUMODE_RECORD; mode != -1;
1107 mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1 ) {
1108 if ((setmode & mode) == 0)
1109 continue;
1110
1111 p = mode == AUMODE_PLAY ? play : rec;
1112
1113 if (p == play) {
1114 DPRINTFN(5,("play: sample=%ld precision=%d channels=%d\n",
1115 p->sample_rate, p->precision, p->channels));
1116 /* play back data format may be 8- or 16-bit and
1117 * either stereo or mono.
1118 * playback rate may range from 8000Hz to 48000Hz
1119 */
1120 if (p->sample_rate < 8000 || p->sample_rate > 48000 ||
1121 (p->precision != 8 && p->precision != 16) ||
1122 (p->channels != 1 && p->channels != 2) ) {
1123 return (EINVAL);
1124 }
1125 } else {
1126 DPRINTFN(5,("rec: sample=%ld precision=%d channels=%d\n",
1127 p->sample_rate, p->precision, p->channels));
1128 /* capture data format must be 16bit stereo
1129 * and sample rate range from 11025Hz to 48000Hz.
1130 *
1131 * XXX: it looks like to work with 8000Hz,
1132 * although data sheets say lower limit is
1133 * 11025 Hz.
1134 */
1135
1136 if (p->sample_rate < 8000 || p->sample_rate > 48000 ||
1137 (p->precision != 8 && p->precision != 16) ||
1138 (p->channels != 1 && p->channels != 2) ) {
1139 return (EINVAL);
1140 }
1141 }
1142 p->factor = 1;
1143 p->sw_code = 0;
1144
1145 /* capturing data is slinear */
1146 switch (p->encoding) {
1147 case AUDIO_ENCODING_SLINEAR_BE:
1148 if (mode == AUMODE_RECORD) {
1149 if (p->precision == 16)
1150 p->sw_code = swap_bytes;
1151 }
1152 break;
1153 case AUDIO_ENCODING_SLINEAR_LE:
1154 break;
1155 case AUDIO_ENCODING_ULINEAR_BE:
1156 if (mode == AUMODE_RECORD) {
1157 if (p->precision == 16)
1158 p->sw_code = change_sign16_swap_bytes;
1159 else
1160 p->sw_code = change_sign8;
1161 }
1162 break;
1163 case AUDIO_ENCODING_ULINEAR_LE:
1164 if (mode == AUMODE_RECORD) {
1165 if (p->precision == 16)
1166 p->sw_code = change_sign16;
1167 else
1168 p->sw_code = change_sign8;
1169 }
1170 break;
1171 case AUDIO_ENCODING_ULAW:
1172 if (mode == AUMODE_PLAY) {
1173 p->factor = 2;
1174 p->sw_code = mulaw_to_slinear16;
1175 } else {
1176 p->sw_code = slinear8_to_mulaw;
1177 }
1178 break;
1179 case AUDIO_ENCODING_ALAW:
1180 if (mode == AUMODE_PLAY) {
1181 p->factor = 2;
1182 p->sw_code = alaw_to_slinear16;
1183 } else {
1184 p->sw_code = slinear8_to_alaw;
1185 }
1186 break;
1187 default:
1188 return (EINVAL);
1189 }
1190 }
1191
1192 /* set sample rate */
1193 cs4280_set_dac_rate(sc, play->sample_rate);
1194 cs4280_set_adc_rate(sc, rec->sample_rate);
1195 return (0);
1196 }
1197
1198 int
cs4280_round_blocksize(hdl,blk)1199 cs4280_round_blocksize(hdl, blk)
1200 void *hdl;
1201 int blk;
1202 {
1203 return (blk < CS4280_ICHUNK ? CS4280_ICHUNK : blk & -CS4280_ICHUNK);
1204 }
1205
1206 size_t
cs4280_round_buffersize(addr,direction,size)1207 cs4280_round_buffersize(addr, direction, size)
1208 void *addr;
1209 int direction;
1210 size_t size;
1211 {
1212 /* although real dma buffer size is 4KB,
1213 * let the audio.c driver use a larger buffer.
1214 * ( suggested by Lennart Augustsson. )
1215 */
1216 return (size);
1217 }
1218
1219 int
cs4280_get_props(hdl)1220 cs4280_get_props(hdl)
1221 void *hdl;
1222 {
1223 return (AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX);
1224 #ifdef notyet
1225 /* XXX
1226 * How can I mmap ?
1227 */
1228 AUDIO_PROP_MMAP
1229 #endif
1230
1231 }
1232
1233 int
cs4280_mixer_get_port(addr,cp)1234 cs4280_mixer_get_port(addr, cp)
1235 void *addr;
1236 mixer_ctrl_t *cp;
1237 {
1238 struct cs4280_softc *sc = addr;
1239
1240 return (sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp));
1241 }
1242
1243 paddr_t
cs4280_mappage(addr,mem,off,prot)1244 cs4280_mappage(addr, mem, off, prot)
1245 void *addr;
1246 void *mem;
1247 off_t off;
1248 int prot;
1249 {
1250 struct cs4280_softc *sc = addr;
1251 struct cs4280_dma *p;
1252
1253 if (off < 0)
1254 return (-1);
1255 for (p = sc->sc_dmas; p && BUFADDR(p) != mem; p = p->next)
1256 ;
1257 if (!p) {
1258 DPRINTF(("cs4280_mappage: bad buffer address\n"));
1259 return (-1);
1260 }
1261 return (bus_dmamem_mmap(sc->sc_dmatag, p->segs, p->nsegs,
1262 off, prot, BUS_DMA_WAITOK));
1263 }
1264
1265
1266 int
cs4280_query_devinfo(addr,dip)1267 cs4280_query_devinfo(addr, dip)
1268 void *addr;
1269 mixer_devinfo_t *dip;
1270 {
1271 struct cs4280_softc *sc = addr;
1272
1273 return (sc->codec_if->vtbl->query_devinfo(sc->codec_if, dip));
1274 }
1275
1276 int
cs4280_get_portnum_by_name(sc,class,device,qualifier)1277 cs4280_get_portnum_by_name(sc, class, device, qualifier)
1278 struct cs4280_softc *sc;
1279 char *class, *device, *qualifier;
1280 {
1281 return (sc->codec_if->vtbl->get_portnum_by_name(sc->codec_if, class,
1282 device, qualifier));
1283 }
1284
1285 int
cs4280_halt_output(addr)1286 cs4280_halt_output(addr)
1287 void *addr;
1288 {
1289 struct cs4280_softc *sc = addr;
1290 u_int32_t mem;
1291
1292 mem = BA1READ4(sc, CS4280_PCTL);
1293 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1294 #ifdef DIAGNOSTIC
1295 sc->sc_prun = 0;
1296 #endif
1297 return (0);
1298 }
1299
1300 int
cs4280_halt_input(addr)1301 cs4280_halt_input(addr)
1302 void *addr;
1303 {
1304 struct cs4280_softc *sc = addr;
1305 u_int32_t mem;
1306
1307 mem = BA1READ4(sc, CS4280_CCTL);
1308 BA1WRITE4(sc, CS4280_CCTL, mem & ~CCTL_MASK);
1309 #ifdef DIAGNOSTIC
1310 sc->sc_rrun = 0;
1311 #endif
1312 return (0);
1313 }
1314
1315 int
cs4280_getdev(addr,retp)1316 cs4280_getdev(addr, retp)
1317 void *addr;
1318 struct audio_device *retp;
1319 {
1320 *retp = cs4280_device;
1321 return (0);
1322 }
1323
1324 int
cs4280_mixer_set_port(addr,cp)1325 cs4280_mixer_set_port(addr, cp)
1326 void *addr;
1327 mixer_ctrl_t *cp;
1328 {
1329 struct cs4280_softc *sc = addr;
1330 int val;
1331
1332 val = sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
1333 DPRINTFN(3,("mixer_set_port: val=%d\n", val));
1334 return (val);
1335 }
1336
1337
1338 int
cs4280_freemem(sc,p)1339 cs4280_freemem(sc, p)
1340 struct cs4280_softc *sc;
1341 struct cs4280_dma *p;
1342 {
1343 bus_dmamap_unload(sc->sc_dmatag, p->map);
1344 bus_dmamap_destroy(sc->sc_dmatag, p->map);
1345 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size);
1346 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs);
1347 return (0);
1348 }
1349
1350 int
cs4280_allocmem(sc,size,align,p)1351 cs4280_allocmem(sc, size, align, p)
1352 struct cs4280_softc *sc;
1353 size_t size;
1354 size_t align;
1355 struct cs4280_dma *p;
1356 {
1357 int error;
1358
1359 /* XXX */
1360 p->size = size;
1361 error = bus_dmamem_alloc(sc->sc_dmatag, p->size, align, 0,
1362 p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
1363 &p->nsegs, BUS_DMA_NOWAIT);
1364 if (error) {
1365 printf("%s: unable to allocate dma, error=%d\n",
1366 sc->sc_dev.dv_xname, error);
1367 return (error);
1368 }
1369
1370 error = bus_dmamem_map(sc->sc_dmatag, p->segs, p->nsegs, p->size,
1371 &p->addr, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
1372 if (error) {
1373 printf("%s: unable to map dma, error=%d\n",
1374 sc->sc_dev.dv_xname, error);
1375 goto free;
1376 }
1377
1378 error = bus_dmamap_create(sc->sc_dmatag, p->size, 1, p->size,
1379 0, BUS_DMA_NOWAIT, &p->map);
1380 if (error) {
1381 printf("%s: unable to create dma map, error=%d\n",
1382 sc->sc_dev.dv_xname, error);
1383 goto unmap;
1384 }
1385
1386 error = bus_dmamap_load(sc->sc_dmatag, p->map, p->addr, p->size, NULL,
1387 BUS_DMA_NOWAIT);
1388 if (error) {
1389 printf("%s: unable to load dma map, error=%d\n",
1390 sc->sc_dev.dv_xname, error);
1391 goto destroy;
1392 }
1393 return (0);
1394
1395 destroy:
1396 bus_dmamap_destroy(sc->sc_dmatag, p->map);
1397 unmap:
1398 bus_dmamem_unmap(sc->sc_dmatag, p->addr, p->size);
1399 free:
1400 bus_dmamem_free(sc->sc_dmatag, p->segs, p->nsegs);
1401 return (error);
1402 }
1403
1404
1405 void *
cs4280_malloc(addr,direction,size,pool,flags)1406 cs4280_malloc(addr, direction, size, pool, flags)
1407 void *addr;
1408 int direction;
1409 size_t size;
1410 int pool, flags;
1411 {
1412 struct cs4280_softc *sc = addr;
1413 struct cs4280_dma *p;
1414 caddr_t q;
1415 int error;
1416
1417 DPRINTFN(5,("cs4280_malloc: size=%d pool=%d flags=%d\n", size, pool, flags));
1418 q = malloc(size, pool, flags);
1419 if (!q)
1420 return (0);
1421 p = malloc(sizeof(*p), pool, flags);
1422 if (!p) {
1423 free(q,pool);
1424 return (0);
1425 }
1426 /*
1427 * cs4280 has fixed 4kB buffer
1428 */
1429 error = cs4280_allocmem(sc, CS4280_DCHUNK, CS4280_DALIGN, p);
1430
1431 if (error) {
1432 free(q, pool);
1433 free(p, pool);
1434 return (0);
1435 }
1436
1437 p->next = sc->sc_dmas;
1438 sc->sc_dmas = p;
1439 p->dum = q; /* return to audio driver */
1440
1441 return (p->dum);
1442 }
1443
1444 void
cs4280_free(addr,ptr,pool)1445 cs4280_free(addr, ptr, pool)
1446 void *addr;
1447 void *ptr;
1448 int pool;
1449 {
1450 struct cs4280_softc *sc = addr;
1451 struct cs4280_dma **pp, *p;
1452
1453 for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
1454 if (BUFADDR(p) == ptr) {
1455 cs4280_freemem(sc, p);
1456 *pp = p->next;
1457 free(p->dum, pool);
1458 free(p, pool);
1459 return;
1460 }
1461 }
1462 }
1463
1464 int
cs4280_trigger_output(addr,start,end,blksize,intr,arg,param)1465 cs4280_trigger_output(addr, start, end, blksize, intr, arg, param)
1466 void *addr;
1467 void *start, *end;
1468 int blksize;
1469 void (*intr)(void *);
1470 void *arg;
1471 struct audio_params *param;
1472 {
1473 struct cs4280_softc *sc = addr;
1474 u_int32_t pfie, pctl, mem, pdtc;
1475 struct cs4280_dma *p;
1476
1477 #ifdef DIAGNOSTIC
1478 if (sc->sc_prun)
1479 printf("cs4280_trigger_output: already running\n");
1480 sc->sc_prun = 1;
1481 #endif
1482
1483 DPRINTF(("cs4280_trigger_output: sc=%p start=%p end=%p "
1484 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
1485 sc->sc_pintr = intr;
1486 sc->sc_parg = arg;
1487
1488 /* stop playback DMA */
1489 mem = BA1READ4(sc, CS4280_PCTL);
1490 BA1WRITE4(sc, CS4280_PCTL, mem & ~PCTL_MASK);
1491
1492 /* setup PDTC */
1493 pdtc = BA1READ4(sc, CS4280_PDTC);
1494 pdtc &= ~PDTC_MASK;
1495 pdtc |= CS4280_MK_PDTC(param->precision * param->channels);
1496 BA1WRITE4(sc, CS4280_PDTC, pdtc);
1497
1498 DPRINTF(("param: precision=%d factor=%d channels=%d encoding=%d\n",
1499 param->precision, param->factor, param->channels,
1500 param->encoding));
1501 for (p = sc->sc_dmas; p != NULL && BUFADDR(p) != start; p = p->next)
1502 ;
1503 if (p == NULL) {
1504 printf("cs4280_trigger_output: bad addr %p\n", start);
1505 return (EINVAL);
1506 }
1507 if (DMAADDR(p) % CS4280_DALIGN != 0 ) {
1508 printf("cs4280_trigger_output: DMAADDR(p)=0x%lx does not start"
1509 "4kB align\n", DMAADDR(p));
1510 return (EINVAL);
1511 }
1512
1513 sc->sc_pcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/
1514 sc->sc_ps = (char *)start;
1515 sc->sc_pe = (char *)end;
1516 sc->sc_pdma = p;
1517 sc->sc_pbuf = KERNADDR(p);
1518 sc->sc_pi = 0;
1519 sc->sc_pn = sc->sc_ps;
1520 if (blksize >= CS4280_DCHUNK) {
1521 sc->sc_pn = sc->sc_ps + CS4280_DCHUNK;
1522 memcpy(sc->sc_pbuf, start, CS4280_DCHUNK);
1523 ++sc->sc_pi;
1524 } else {
1525 sc->sc_pn = sc->sc_ps + CS4280_ICHUNK;
1526 memcpy(sc->sc_pbuf, start, CS4280_ICHUNK);
1527 }
1528
1529 /* initiate playback dma */
1530 BA1WRITE4(sc, CS4280_PBA, DMAADDR(p));
1531
1532 /* set PFIE */
1533 pfie = BA1READ4(sc, CS4280_PFIE) & ~PFIE_MASK;
1534
1535 if (param->precision * param->factor == 8)
1536 pfie |= PFIE_8BIT;
1537 if (param->channels == 1)
1538 pfie |= PFIE_MONO;
1539
1540 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
1541 param->encoding == AUDIO_ENCODING_SLINEAR_BE)
1542 pfie |= PFIE_SWAPPED;
1543 if (param->encoding == AUDIO_ENCODING_ULINEAR_BE ||
1544 param->encoding == AUDIO_ENCODING_ULINEAR_LE)
1545 pfie |= PFIE_UNSIGNED;
1546
1547 BA1WRITE4(sc, CS4280_PFIE, pfie | PFIE_PI_ENABLE);
1548
1549 cs4280_set_dac_rate(sc, param->sample_rate);
1550
1551 pctl = BA1READ4(sc, CS4280_PCTL) & ~PCTL_MASK;
1552 pctl |= sc->pctl;
1553 BA1WRITE4(sc, CS4280_PCTL, pctl);
1554 return (0);
1555 }
1556
1557 int
cs4280_trigger_input(addr,start,end,blksize,intr,arg,param)1558 cs4280_trigger_input(addr, start, end, blksize, intr, arg, param)
1559 void *addr;
1560 void *start, *end;
1561 int blksize;
1562 void (*intr)(void *);
1563 void *arg;
1564 struct audio_params *param;
1565 {
1566 struct cs4280_softc *sc = addr;
1567 u_int32_t cctl, cie;
1568 struct cs4280_dma *p;
1569
1570 #ifdef DIAGNOSTIC
1571 if (sc->sc_rrun)
1572 printf("cs4280_trigger_input: already running\n");
1573 sc->sc_rrun = 1;
1574 #endif
1575 DPRINTF(("cs4280_trigger_input: sc=%p start=%p end=%p "
1576 "blksize=%d intr=%p(%p)\n", addr, start, end, blksize, intr, arg));
1577 sc->sc_rintr = intr;
1578 sc->sc_rarg = arg;
1579
1580 sc->sc_ri = 0;
1581 sc->sc_rcount = blksize / CS4280_ICHUNK; /* CS4280_ICHUNK is fixed hardware blksize*/
1582 sc->sc_rs = (char *)start;
1583 sc->sc_re = (char *)end;
1584 sc->sc_rn = sc->sc_rs;
1585
1586 /* setup format information for internal converter */
1587 sc->sc_rparam = 0;
1588 if (param->precision == 8) {
1589 sc->sc_rparam += CF_8BIT;
1590 sc->sc_rcount <<= 1;
1591 }
1592 if (param->channels == 1) {
1593 sc->sc_rparam += CF_MONO;
1594 sc->sc_rcount <<= 1;
1595 }
1596
1597 /* stop capture DMA */
1598 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK;
1599 BA1WRITE4(sc, CS4280_CCTL, cctl);
1600
1601 for (p = sc->sc_dmas; p && BUFADDR(p) != start; p = p->next)
1602 ;
1603 if (!p) {
1604 printf("cs4280_trigger_input: bad addr %p\n", start);
1605 return (EINVAL);
1606 }
1607 if (DMAADDR(p) % CS4280_DALIGN != 0) {
1608 printf("cs4280_trigger_input: DMAADDR(p)=0x%lx does not start"
1609 "4kB align\n", DMAADDR(p));
1610 return (EINVAL);
1611 }
1612 sc->sc_rdma = p;
1613 sc->sc_rbuf = KERNADDR(p);
1614
1615 /* initiate capture dma */
1616 BA1WRITE4(sc, CS4280_CBA, DMAADDR(p));
1617
1618 /* set CIE */
1619 cie = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
1620 BA1WRITE4(sc, CS4280_CIE, cie | CIE_CI_ENABLE);
1621
1622 cs4280_set_adc_rate(sc, param->sample_rate);
1623
1624 cctl = BA1READ4(sc, CS4280_CCTL) & ~CCTL_MASK;
1625 cctl |= sc->cctl;
1626 BA1WRITE4(sc, CS4280_CCTL, cctl);
1627 return (0);
1628 }
1629
1630
1631 int
cs4280_init(sc,init)1632 cs4280_init(sc, init)
1633 struct cs4280_softc *sc;
1634 int init;
1635 {
1636 int n;
1637 u_int32_t mem;
1638
1639 /* Start PLL out in known state */
1640 BA0WRITE4(sc, CS4280_CLKCR1, 0);
1641 /* Start serial ports out in known state */
1642 BA0WRITE4(sc, CS4280_SERMC1, 0);
1643
1644 /* Specify type of CODEC */
1645 /* XXX should no be here */
1646 #define SERACC_CODEC_TYPE_1_03
1647 #ifdef SERACC_CODEC_TYPE_1_03
1648 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_1_03); /* AC 97 1.03 */
1649 #else
1650 BA0WRITE4(sc, CS4280_SERACC, SERACC_HSP | SERACC_CTYPE_2_0); /* AC 97 2.0 */
1651 #endif
1652
1653 /* Reset codec */
1654 BA0WRITE4(sc, CS4280_ACCTL, 0);
1655 delay(100); /* delay 100us */
1656 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_RSTN);
1657
1658 /* Enable AC-link sync generation */
1659 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
1660 delay(50*1000); /* delay 50ms */
1661
1662 /* Set the serial port timing configuration */
1663 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_PTC_AC97);
1664
1665 /* Setup clock control */
1666 BA0WRITE4(sc, CS4280_PLLCC, PLLCC_CDR_STATE|PLLCC_LPF_STATE);
1667 BA0WRITE4(sc, CS4280_PLLM, PLLM_STATE);
1668 BA0WRITE4(sc, CS4280_CLKCR2, CLKCR2_PDIVS_8);
1669
1670 /* Power up the PLL */
1671 BA0WRITE4(sc, CS4280_CLKCR1, CLKCR1_PLLP);
1672 delay(50*1000); /* delay 50ms */
1673
1674 /* Turn on clock */
1675 mem = BA0READ4(sc, CS4280_CLKCR1) | CLKCR1_SWCE;
1676 BA0WRITE4(sc, CS4280_CLKCR1, mem);
1677
1678 /* Set the serial port FIFO pointer to the
1679 * first sample in FIFO. (not documented) */
1680 cs4280_clear_fifos(sc);
1681
1682 #if 0
1683 /* Set the serial port FIFO pointer to the first sample in the FIFO */
1684 BA0WRITE4(sc, CS4280_SERBSP, 0);
1685 #endif
1686
1687 /* Configure the serial port */
1688 BA0WRITE4(sc, CS4280_SERC1, SERC1_SO1EN | SERC1_SO1F_AC97);
1689 BA0WRITE4(sc, CS4280_SERC2, SERC2_SI1EN | SERC2_SI1F_AC97);
1690 BA0WRITE4(sc, CS4280_SERMC1, SERMC1_MSPE | SERMC1_PTC_AC97);
1691
1692 /* Wait for CODEC ready */
1693 n = 0;
1694 while ((BA0READ4(sc, CS4280_ACSTS) & ACSTS_CRDY) == 0) {
1695 delay(125);
1696 if (++n > 1000) {
1697 printf("%s: codec ready timeout\n",
1698 sc->sc_dev.dv_xname);
1699 return(1);
1700 }
1701 }
1702
1703 /* Assert valid frame signal */
1704 BA0WRITE4(sc, CS4280_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
1705
1706 /* Wait for valid AC97 input slot */
1707 n = 0;
1708 while ((BA0READ4(sc, CS4280_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) !=
1709 (ACISV_ISV3 | ACISV_ISV4)) {
1710 delay(1000);
1711 if (++n > 1000) {
1712 printf("AC97 inputs slot ready timeout\n");
1713 return(1);
1714 }
1715 }
1716
1717 /* Set AC97 output slot valid signals */
1718 BA0WRITE4(sc, CS4280_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
1719
1720 /* reset the processor */
1721 cs4280_reset(sc);
1722
1723 /* Download the image to the processor */
1724 if (cs4280_download_image(sc) != 0) {
1725 printf("%s: image download error\n", sc->sc_dev.dv_xname);
1726 return(1);
1727 }
1728
1729 /* Save playback parameter and then write zero.
1730 * this ensures that DMA doesn't immediately occur upon
1731 * starting the processor core
1732 */
1733 mem = BA1READ4(sc, CS4280_PCTL);
1734 sc->pctl = mem & PCTL_MASK; /* save startup value */
1735 cs4280_halt_output(sc);
1736
1737 /* Save capture parameter and then write zero.
1738 * this ensures that DMA doesn't immediately occur upon
1739 * starting the processor core
1740 */
1741 mem = BA1READ4(sc, CS4280_CCTL);
1742 sc->cctl = mem & CCTL_MASK; /* save startup value */
1743 cs4280_halt_input(sc);
1744
1745 /* MSH: need to power up ADC and DAC? */
1746
1747 /* Processor Startup Procedure */
1748 BA1WRITE4(sc, CS4280_FRMT, FRMT_FTV);
1749 BA1WRITE4(sc, CS4280_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
1750
1751 /* Monitor RUNFR bit in SPCR for 1 to 0 transition */
1752 n = 0;
1753 while (BA1READ4(sc, CS4280_SPCR) & SPCR_RUNFR) {
1754 delay(10);
1755 if (++n > 1000) {
1756 printf("SPCR 1->0 transition timeout\n");
1757 return(1);
1758 }
1759 }
1760
1761 n = 0;
1762 while (!(BA1READ4(sc, CS4280_SPCS) & SPCS_SPRUN)) {
1763 delay(10);
1764 if (++n > 1000) {
1765 printf("SPCS 0->1 transition timeout\n");
1766 return(1);
1767 }
1768 }
1769 /* Processor is now running !!! */
1770
1771 /* Setup volume */
1772 BA1WRITE4(sc, CS4280_PVOL, 0x80008000);
1773 BA1WRITE4(sc, CS4280_CVOL, 0x80008000);
1774
1775 /* Interrupt enable */
1776 BA0WRITE4(sc, CS4280_HICR, HICR_IEV|HICR_CHGM);
1777
1778 /* playback interrupt enable */
1779 mem = BA1READ4(sc, CS4280_PFIE) & ~PFIE_PI_MASK;
1780 mem |= PFIE_PI_ENABLE;
1781 BA1WRITE4(sc, CS4280_PFIE, mem);
1782 /* capture interrupt enable */
1783 mem = BA1READ4(sc, CS4280_CIE) & ~CIE_CI_MASK;
1784 mem |= CIE_CI_ENABLE;
1785 BA1WRITE4(sc, CS4280_CIE, mem);
1786
1787 #if NMIDI > 0
1788 /* Reset midi port */
1789 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
1790 BA0WRITE4(sc, CS4280_MIDCR, mem | MIDCR_MRST);
1791 DPRINTF(("midi reset: 0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
1792 /* midi interrupt enable */
1793 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE;
1794 BA0WRITE4(sc, CS4280_MIDCR, mem);
1795 #endif
1796 return(0);
1797 }
1798
1799 void
cs4280_power(why,v)1800 cs4280_power(why, v)
1801 int why;
1802 void *v;
1803 {
1804 struct cs4280_softc *sc = (struct cs4280_softc *)v;
1805 int i;
1806
1807 DPRINTF(("%s: cs4280_power why=%d\n",
1808 sc->sc_dev.dv_xname, why));
1809 if (why != PWR_RESUME) {
1810 sc->sc_suspend = why;
1811
1812 cs4280_halt_output(sc);
1813 cs4280_halt_input(sc);
1814 /* Save AC97 registers */
1815 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) {
1816 if(i == 0x04) /* AC97_REG_MASTER_TONE */
1817 continue;
1818 cs4280_read_codec(sc, 2*i, &sc->ac97_reg[i]);
1819 }
1820 /* should I powerdown here ? */
1821 cs4280_write_codec(sc, AC97_REG_POWER, CS4280_POWER_DOWN_ALL);
1822 } else {
1823 if (sc->sc_suspend == PWR_RESUME) {
1824 printf("cs4280_power: odd, resume without suspend.\n");
1825 sc->sc_suspend = why;
1826 return;
1827 }
1828 sc->sc_suspend = why;
1829 cs4280_init(sc, 0);
1830 cs4280_reset_codec(sc);
1831
1832 /* restore ac97 registers */
1833 for(i = 1; i <= CS4280_SAVE_REG_MAX; i++) {
1834 if(i == 0x04) /* AC97_REG_MASTER_TONE */
1835 continue;
1836 cs4280_write_codec(sc, 2*i, sc->ac97_reg[i]);
1837 }
1838 }
1839 }
1840
1841 void
cs4280_clear_fifos(sc)1842 cs4280_clear_fifos(sc)
1843 struct cs4280_softc *sc;
1844 {
1845 int pd = 0, cnt, n;
1846 u_int32_t mem;
1847
1848 /*
1849 * If device power down, power up the device and keep power down
1850 * state.
1851 */
1852 mem = BA0READ4(sc, CS4280_CLKCR1);
1853 if (!(mem & CLKCR1_SWCE)) {
1854 printf("cs4280_clear_fifo: power down found.\n");
1855 BA0WRITE4(sc, CS4280_CLKCR1, mem | CLKCR1_SWCE);
1856 pd = 1;
1857 }
1858 BA0WRITE4(sc, CS4280_SERBWP, 0);
1859 for (cnt = 0; cnt < 256; cnt++) {
1860 n = 0;
1861 while (BA0READ4(sc, CS4280_SERBST) & SERBST_WBSY) {
1862 delay(1000);
1863 if (++n > 1000) {
1864 printf("clear_fifo: fist timeout cnt=%d\n", cnt);
1865 break;
1866 }
1867 }
1868 BA0WRITE4(sc, CS4280_SERBAD, cnt);
1869 BA0WRITE4(sc, CS4280_SERBCM, SERBCM_WRC);
1870 }
1871 if (pd)
1872 BA0WRITE4(sc, CS4280_CLKCR1, mem);
1873 }
1874
1875 #if NMIDI > 0
1876 int
cs4280_midi_open(addr,flags,iintr,ointr,arg)1877 cs4280_midi_open(addr, flags, iintr, ointr, arg)
1878 void *addr;
1879 int flags;
1880 void (*iintr)(void *, int);
1881 void (*ointr)(void *);
1882 void *arg;
1883 {
1884 struct cs4280_softc *sc = addr;
1885 u_int32_t mem;
1886
1887 DPRINTF(("midi_open\n"));
1888 sc->sc_iintr = iintr;
1889 sc->sc_ointr = ointr;
1890 sc->sc_arg = arg;
1891
1892 /* midi interrupt enable */
1893 mem = BA0READ4(sc, CS4280_MIDCR) & ~MIDCR_MASK;
1894 mem |= MIDCR_TXE | MIDCR_RXE | MIDCR_RIE | MIDCR_TIE | MIDCR_MLB;
1895 BA0WRITE4(sc, CS4280_MIDCR, mem);
1896 #ifdef CS4280_DEBUG
1897 if (mem != BA0READ4(sc, CS4280_MIDCR)) {
1898 DPRINTF(("midi_open: MIDCR=%d\n", BA0READ4(sc, CS4280_MIDCR)));
1899 return(EINVAL);
1900 }
1901 DPRINTF(("MIDCR=0x%x\n", BA0READ4(sc, CS4280_MIDCR)));
1902 #endif
1903 return (0);
1904 }
1905
1906 void
cs4280_midi_close(addr)1907 cs4280_midi_close(addr)
1908 void *addr;
1909 {
1910 struct cs4280_softc *sc = addr;
1911 u_int32_t mem;
1912
1913 DPRINTF(("midi_close\n"));
1914 mem = BA0READ4(sc, CS4280_MIDCR);
1915 mem &= ~MIDCR_MASK;
1916 BA0WRITE4(sc, CS4280_MIDCR, mem);
1917
1918 sc->sc_iintr = 0;
1919 sc->sc_ointr = 0;
1920 }
1921
1922 int
cs4280_midi_output(addr,d)1923 cs4280_midi_output(addr, d)
1924 void *addr;
1925 int d;
1926 {
1927 struct cs4280_softc *sc = addr;
1928 u_int32_t mem;
1929 int x;
1930
1931 for (x = 0; x != MIDI_BUSY_WAIT; x++) {
1932 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
1933 mem = BA0READ4(sc, CS4280_MIDWP) & ~MIDWP_MASK;
1934 mem |= d & MIDWP_MASK;
1935 DPRINTFN(5,("midi_output d=0x%08x",d));
1936 BA0WRITE4(sc, CS4280_MIDWP, mem);
1937 if (mem != BA0READ4(sc, CS4280_MIDWP)) {
1938 DPRINTF(("Bad write data: %d %d",
1939 mem, BA0READ4(sc, CS4280_MIDWP)));
1940 return(EIO);
1941 }
1942 return (0);
1943 }
1944 delay(MIDI_BUSY_DELAY);
1945 }
1946 return (EIO);
1947 }
1948
1949 void
cs4280_midi_getinfo(addr,mi)1950 cs4280_midi_getinfo(addr, mi)
1951 void *addr;
1952 struct midi_info *mi;
1953 {
1954 mi->name = "CS4280 MIDI UART";
1955 mi->props = MIDI_PROP_CAN_INPUT | MIDI_PROP_OUT_INTR;
1956 }
1957
1958 #endif
1959