1 /* $OpenBSD: txphyreg.h,v 1.3 2003/10/22 09:39:29 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 1999 Jason L. Wright (jason@thought.net) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_MII_TXPHYREG_H_ 30 #define _DEV_MII_TXPHYREG_H_ 31 32 /* 33 * Texas Instruments TNETE2101 registers. 34 */ 35 #define MII_TXPHY_ID 0x10 /* PHY identifier */ 36 37 #define MII_TXPHY_CTL 0x11 /* PHY control */ 38 #define TXCTL_IGLINK 0x8000 /* ignore link */ 39 #define TXCTL_SWAPOL 0x4000 /* swap polarity */ 40 #define TXCTL_MANCONF 0x2000 /* manual configuration */ 41 #define TXCTL_SQEEN 0x1000 /* SQE enable */ 42 #define TXCTL_MTEST 0x0800 /* manufacturing test */ 43 #define TXCTL_FIBER 0x0400 /* 100BaseFX mode */ 44 #define TXCTL_FEFEN 0x0200 /* far-end fault indication enable */ 45 #define TXCTL_NOENDEC 0x0100 /* no encode/decode */ 46 #define TXCTL_NOALIGN 0x0080 /* no symbol alignment */ 47 #define TXCTL_DUPONLY 0x0040 /* duplex LED only */ 48 #define TXCTL_REPEATER 0x0020 /* repeater mode enable */ 49 #define TXCTL_RXRESET 0x0010 /* 100baseTX rx reset */ 50 #define TXCTL_NOLINKP 0x0008 /* disable link pulse tx */ 51 #define TXCTL_NFEW 0x0004 /* no far end wrap */ 52 #define TXCTL_INTEN 0x0002 /* interrupt enable */ 53 #define TXCTL_TINT 0x0001 /* test interrupt */ 54 55 #define MII_TXPHY_STS 0x12 /* PHY status */ 56 #define TXSTS_MINT 0x8000 /* mii interrupt */ 57 #define TXSTS_PHOK 0x4000 /* power high ok */ 58 #define TXSTS_PLOK 0x2000 /* polarity ok */ 59 #define TXSTS_TPENERGY 0x1000 /* TP energy detect */ 60 #define TXSTS_SYNCLOSS 0x0800 /* 100btx rx descrambler sync loss */ 61 #define TXSTS_FEFI 0x0400 /* Far-end fault indication */ 62 63 #endif /* _DEV_MII_MTDPHYREG_H_ */ 64