1 /* $OpenBSD: nsphyterreg.h,v 1.1 1999/12/07 22:33:43 jason Exp $ */ 2 /* $NetBSD: nsphyterreg.h,v 1.1 1999/12/07 19:36:37 thorpej Exp $ */ 3 4 /*- 5 * Copyright (c) 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 10 * NASA Ames Research Center. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 #ifndef _DEV_MII_NSPHYTERREG_H_ 42 #define _DEV_MII_NSPHYTERREG_H_ 43 44 /* 45 * DP83843 registers. 46 */ 47 48 #define MII_NSPHYTER_PHYSTS 0x10 /* PHY status */ 49 #define PHYSTS_REL 0x8000 /* receive error latch */ 50 #define PHYSTS_CIML 0x4000 /* CIM latch */ 51 #define PHYSTS_FCSL 0x2000 /* false carrier sense latch */ 52 #define PHYSTS_DEVRDY 0x0800 /* device ready */ 53 #define PHYSTS_PGRX 0x0400 /* page received */ 54 #define PHYSTS_ANEGEN 0x0200 /* autoneg. enabled */ 55 #define PHYSTS_MIIINTR 0x0100 /* MII interrupt */ 56 #define PHYSTS_REMFAULT 0x0080 /* remote fault */ 57 #define PHYSTS_JABBER 0x0040 /* jabber detect */ 58 #define PHYSTS_NWAYCOMP 0x0020 /* NWAY complete */ 59 #define PHYSTS_RESETSTAT 0x0010 /* reset status */ 60 #define PHYSTS_LOOPBACK 0x0008 /* loopback status */ 61 #define PHYSTS_DUPLEX 0x0004 /* full duplex */ 62 #define PHYSTS_SPEED10 0x0002 /* speed == 10Mb/s */ 63 #define PHYSTS_LINK 0x0001 /* link up */ 64 65 66 #define MII_NSPHYTER_MIPSCR 0x11 /* MII interrupt PHY specific 67 control */ 68 69 #define MIPSCR_INTEN 0x0002 /* interrupt enable */ 70 #define MIPSCR_TINT 0x0001 /* test interrupt */ 71 72 73 #define MII_NSPHYTER_MIPGSR 0x12 /* MII interrupt PHY generic 74 status */ 75 #define MIPGSR_MINT 0x8000 /* MII interrupt pending */ 76 77 #define MII_NSPHYTER_DCR 0x13 /* Disconnect counter */ 78 79 #define MII_NSPHYTER_FCSCR 0x14 /* False carrier sense counter */ 80 81 #define MII_NSPHYTER_RECR 0x15 /* Receive error counter */ 82 83 84 #define MII_NSPHYTER_PCSR 0x16 /* PCS configuration and status */ 85 #define PCSR_SINGLE_SD 0x8000 /* single-ended SD mode */ 86 #define PCSR_FEFI_EN 0x4000 /* far end fault indication mode */ 87 #define PCSR_DESCR_TO_RST 0x2000 /* reset descrambler timeout counter */ 88 #define PCSR_DESCR_TO_SEL 0x1000 /* descrambler timer mode */ 89 #define PCSR_DESCR_TO_DIS 0x0800 /* descrambler timer disable */ 90 #define PCSR_LD_SCR_SD 0x0400 /* load scrambler seed */ 91 #define PCSR_TX_QUIET 0x0200 /* 100Mb/s transmit true quiet mode */ 92 #define PCSR_TX_PATTERN 0x0180 /* 100Mb/s transmit test pattern */ 93 #define PCSR_F_LINK_100 0x0040 /* force good link in 100Mb/s */ 94 #define PCSR_CIM_DIS 0x0020 /* carrier integrity monitor disable */ 95 #define PCSR_CIM_STATUS 0x0010 /* carrier integrity monitor status */ 96 #define PCSR_CODE_ERR 0x0008 /* code errors */ 97 #define PCSR_PME_ERR 0x0004 /* premature end errors */ 98 #define PCSR_LINK_ERR 0x0002 /* link errors */ 99 #define PCSR_PKT_ERR 0x0001 /* packet errors */ 100 101 102 #define MII_NSPHYTER_LBR 0x17 /* loopback and bypass */ 103 #define LBR_BP_STRETCH 0x4000 /* bypass LED stretching */ 104 #define LBR_BP_4B5B 0x2000 /* bypass encoding/decoding */ 105 #define LBR_BP_SCR 0x1000 /* bypass scrambler/descrambler */ 106 #define LBR_BP_RX 0x0800 /* bypass receive function */ 107 #define LBR_BP_TX 0x0400 /* bypass transmit function */ 108 #define LBR_100_DP_CTL 0x0380 /* 100Mb/s data patch control */ 109 #define LBR_TW_LBEN 0x0020 /* TWISTER loopback enable */ 110 #define LBR_10_ENDEC_LB 0x0010 /* 10Mb/s ENDEC loopback */ 111 112 113 #define MII_NSPHYTER_10BTSCR 0x18 /* 10baseT status and control */ 114 #define BTSCR_AUI_TPI 0x2000 /* TREX operating mode */ 115 #define BTSCR_RX_SERIAL 0x1000 /* 10baseT RX serial mode */ 116 #define BTSCR_TX_SERIAL 0x0800 /* 10baseT TX serial mode */ 117 #define BTSCR_POL_DS 0x0400 /* polarity detection and correction 118 disable */ 119 #define BTSCR_AUTOSW_EN 0x0200 /* AUI/TPI autoswitch */ 120 #define BTSCR_LP_DS 0x0100 /* link pulse disable */ 121 #define BTSCR_HB_DS 0x0080 /* heartbeat disabled */ 122 #define BTSCR_LS_SEL 0x0040 /* low squelch select */ 123 #define BTSCR_AUI_SEL 0x0020 /* AUI select */ 124 #define BTSCR_JAB_DS 0x0010 /* jabber disable */ 125 #define BTSCR_THIN_SEL 0x0008 /* thin ethernet select */ 126 #define BTSCR_TX_FILT_DS 0x0004 /* TPI receive filter disable */ 127 128 129 #define MII_NSPHYTER_PHYCTRL 0x19 /* PHY control */ 130 #define PHYCTRL_TW_EQSEL 0x3000 /* TWISTER e.q. select */ 131 #define PHYCTRL_BLW_DS 0x0800 /* TWISTER base line wander disable */ 132 #define PHYCTRL_REPEATER 0x0200 /* repeater mode */ 133 #define PHYCTRL_LED_TXRX_MODE 0x0180 /* LED TX/RX mode */ 134 #define PHYCTRL_LED_DUP_MODE 0x0040 /* LED DUP mode */ 135 #define PHYCTRL_FX_EN 0x0020 /* Fiber mode enable */ 136 #define PHYCTRL_PHYADDR 0x001f /* PHY address */ 137 138 #endif /* _DEV_MII_NSPHYTERREG_H_ */ 139