1 /* $OpenBSD: mii_bitbang.c,v 1.4 2005/07/01 02:50:34 brad Exp $ */
2 /* $NetBSD: mii_bitbang.c,v 1.6 2004/08/23 06:18:39 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1999 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the NetBSD
23 * Foundation, Inc. and its contributors.
24 * 4. Neither the name of The NetBSD Foundation nor the names of its
25 * contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 */
40
41 /*
42 * Common module for bit-bang'ing the MII.
43 */
44
45 #include <sys/param.h>
46 #include <sys/device.h>
47
48 #include <dev/mii/mii.h>
49 #include <dev/mii/mii_bitbang.h>
50
51 void mii_bitbang_sync(struct device *, mii_bitbang_ops_t);
52 void mii_bitbang_sendbits(struct device *, mii_bitbang_ops_t,
53 u_int32_t, int);
54
55 #define WRITE(x) \
56 do { \
57 ops->mbo_write(sc, (x)); \
58 delay(1); \
59 } while (0)
60
61 #define READ ops->mbo_read(sc)
62
63 #define MDO ops->mbo_bits[MII_BIT_MDO]
64 #define MDI ops->mbo_bits[MII_BIT_MDI]
65 #define MDC ops->mbo_bits[MII_BIT_MDC]
66 #define MDIRPHY ops->mbo_bits[MII_BIT_DIR_HOST_PHY]
67 #define MDIRHOST ops->mbo_bits[MII_BIT_DIR_PHY_HOST]
68
69 /*
70 * mii_bitbang_sync:
71 *
72 * Synchronize the MII.
73 */
74 void
mii_bitbang_sync(struct device * sc,mii_bitbang_ops_t ops)75 mii_bitbang_sync(struct device *sc, mii_bitbang_ops_t ops)
76 {
77 int i;
78 u_int32_t v;
79
80 v = MDIRPHY | MDO;
81
82 WRITE(v);
83 for (i = 0; i < 32; i++) {
84 WRITE(v | MDC);
85 WRITE(v);
86 }
87 }
88
89 /*
90 * mii_bitbang_sendbits:
91 *
92 * Send a series of bits to the MII.
93 */
94 void
mii_bitbang_sendbits(struct device * sc,mii_bitbang_ops_t ops,u_int32_t data,int nbits)95 mii_bitbang_sendbits(struct device *sc, mii_bitbang_ops_t ops,
96 u_int32_t data, int nbits)
97 {
98 int i;
99 u_int32_t v;
100
101 v = MDIRPHY;
102 WRITE(v);
103
104 for (i = 1 << (nbits - 1); i != 0; i >>= 1) {
105 if (data & i)
106 v |= MDO;
107 else
108 v &= ~MDO;
109 WRITE(v);
110 WRITE(v | MDC);
111 WRITE(v);
112 }
113 }
114
115 /*
116 * mii_bitbang_readreg:
117 *
118 * Read a PHY register by bit-bang'ing the MII.
119 */
120 int
mii_bitbang_readreg(struct device * sc,mii_bitbang_ops_t ops,int phy,int reg)121 mii_bitbang_readreg(struct device *sc, mii_bitbang_ops_t ops, int phy,
122 int reg)
123 {
124 int val = 0, err = 0, i;
125
126 mii_bitbang_sync(sc, ops);
127
128 mii_bitbang_sendbits(sc, ops, MII_COMMAND_START, 2);
129 mii_bitbang_sendbits(sc, ops, MII_COMMAND_READ, 2);
130 mii_bitbang_sendbits(sc, ops, phy, 5);
131 mii_bitbang_sendbits(sc, ops, reg, 5);
132
133 /* Switch direction to PHY->host, without a clock transition. */
134 WRITE(MDIRHOST);
135
136 /* Turnaround clock. */
137 WRITE(MDIRHOST | MDC);
138 WRITE(MDIRHOST);
139
140 /* Check for error. */
141 err = READ & MDI;
142
143 /* Idle clock. */
144 WRITE(MDIRHOST | MDC);
145 WRITE(MDIRHOST);
146
147 for (i = 0; i < 16; i++) {
148 val <<= 1;
149 /* Read data prior to clock low-high transition. */
150 if (err == 0 && (READ & MDI) != 0)
151 val |= 1;
152
153 WRITE(MDIRHOST | MDC);
154 WRITE(MDIRHOST);
155 }
156
157 /* Set direction to host->PHY, without a clock transition. */
158 WRITE(MDIRPHY);
159
160 return (err ? 0 : val);
161 }
162
163 /*
164 * mii_bitbang_writereg:
165 *
166 * Write a PHY register by bit-bang'ing the MII.
167 */
168 void
mii_bitbang_writereg(struct device * sc,mii_bitbang_ops_t ops,int phy,int reg,int val)169 mii_bitbang_writereg(struct device *sc, mii_bitbang_ops_t ops,
170 int phy, int reg, int val)
171 {
172
173 mii_bitbang_sync(sc, ops);
174
175 mii_bitbang_sendbits(sc, ops, MII_COMMAND_START, 2);
176 mii_bitbang_sendbits(sc, ops, MII_COMMAND_WRITE, 2);
177 mii_bitbang_sendbits(sc, ops, phy, 5);
178 mii_bitbang_sendbits(sc, ops, reg, 5);
179 mii_bitbang_sendbits(sc, ops, MII_COMMAND_ACK, 2);
180 mii_bitbang_sendbits(sc, ops, val, 16);
181
182 WRITE(MDIRPHY);
183 }
184