1 /* $OpenBSD: brgphy.c,v 1.26 2005/06/29 04:37:07 brad Exp $ */
2
3 /*
4 * Copyright (c) 2000
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: brgphy.c,v 1.8 2002/03/22 06:38:52 wpaul Exp $
35 */
36
37 /*
38 * Driver for the Broadcom BCR5400 1000baseTX PHY. Speed is always
39 * 1000mbps; all we need to negotiate here is full or half duplex.
40 */
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/device.h>
46 #include <sys/socket.h>
47 #include <sys/errno.h>
48
49 #include <machine/bus.h>
50
51 #include <net/if.h>
52 #include <net/if_media.h>
53
54 #ifdef INET
55 #include <netinet/in.h>
56 #include <netinet/if_ether.h>
57 #endif
58
59 #include <dev/pci/pcivar.h>
60
61 #include <dev/mii/mii.h>
62 #include <dev/mii/miivar.h>
63 #include <dev/mii/miidevs.h>
64
65 #include <dev/mii/brgphyreg.h>
66
67 #include <dev/pci/if_bgereg.h>
68
69 int brgphy_probe(struct device *, void *, void *);
70 void brgphy_attach(struct device *, struct device *, void *);
71
72 struct cfattach brgphy_ca = {
73 sizeof(struct mii_softc), brgphy_probe, brgphy_attach, mii_phy_detach,
74 mii_phy_activate
75 };
76
77 struct cfdriver brgphy_cd = {
78 NULL, "brgphy", DV_DULL
79 };
80
81 int brgphy_service(struct mii_softc *, struct mii_data *, int);
82 void brgphy_status(struct mii_softc *);
83 int brgphy_mii_phy_auto(struct mii_softc *);
84 void brgphy_loop(struct mii_softc *);
85 void brgphy_reset(struct mii_softc *);
86 void brgphy_load_dspcode(struct mii_softc *);
87
88 const struct mii_phy_funcs brgphy_funcs = {
89 brgphy_service, brgphy_status, brgphy_reset,
90 };
91
92 static const struct mii_phydesc brgphys[] = {
93 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5400,
94 MII_STR_xxBROADCOM_BCM5400 },
95 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5401,
96 MII_STR_xxBROADCOM_BCM5401 },
97 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5411,
98 MII_STR_xxBROADCOM_BCM5411 },
99 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5421,
100 MII_STR_xxBROADCOM_BCM5421 },
101 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5701,
102 MII_STR_xxBROADCOM_BCM5701 },
103 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5703,
104 MII_STR_xxBROADCOM_BCM5703 },
105 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5704,
106 MII_STR_xxBROADCOM_BCM5704 },
107 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5705,
108 MII_STR_xxBROADCOM_BCM5705 },
109 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5714,
110 MII_STR_xxBROADCOM_BCM5714 },
111 { MII_OUI_xxBROADCOM, MII_MODEL_xxBROADCOM_BCM5750,
112 MII_STR_xxBROADCOM_BCM5750 },
113
114 { 0, 0,
115 NULL },
116 };
117
118 int
brgphy_probe(struct device * parent,void * match,void * aux)119 brgphy_probe(struct device *parent, void *match, void *aux)
120 {
121 struct mii_attach_args *ma = aux;
122
123 if (mii_phy_match(ma, brgphys) != NULL)
124 return(10);
125
126 return(0);
127 }
128
129 void
brgphy_attach(struct device * parent,struct device * self,void * aux)130 brgphy_attach(struct device *parent, struct device *self, void *aux)
131 {
132 struct mii_softc *sc = (struct mii_softc *)self;
133 struct mii_attach_args *ma = aux;
134 struct mii_data *mii = ma->mii_data;
135 const struct mii_phydesc *mpd;
136
137 mpd = mii_phy_match(ma, brgphys);
138 printf(": %s, rev. %d\n", mpd->mpd_name, MII_REV(ma->mii_id2));
139
140 sc->mii_inst = mii->mii_instance;
141 sc->mii_phy = ma->mii_phyno;
142 sc->mii_funcs = &brgphy_funcs;
143 sc->mii_model = MII_MODEL(ma->mii_id2);
144 sc->mii_rev = MII_REV(ma->mii_id2);
145 sc->mii_pdata = mii;
146 sc->mii_flags = ma->mii_flags | MIIF_NOISOLATE;
147 sc->mii_anegticks = MII_ANEGTICKS;
148
149 PHY_RESET(sc);
150
151 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
152 if (sc->mii_capabilities & BMSR_EXTSTAT)
153 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
154 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
155 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
156 mii_phy_add_media(sc);
157 }
158
159 int
brgphy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)160 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
161 {
162 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
163 int reg, speed, gig;
164
165 if ((sc->mii_dev.dv_flags & DVF_ACTIVE) == 0)
166 return (ENXIO);
167
168 switch (cmd) {
169 case MII_POLLSTAT:
170 /*
171 * If we're not polling our PHY instance, just return.
172 */
173 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
174 return (0);
175 break;
176
177 case MII_MEDIACHG:
178 /*
179 * If the media indicates a different PHY instance,
180 * isolate ourselves.
181 */
182 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
183 reg = PHY_READ(sc, MII_BMCR);
184 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
185 return (0);
186 }
187
188 /*
189 * If the interface is not up, don't do anything.
190 */
191 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
192 break;
193
194 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
195 PHY_RESET(sc); /* XXX hardware bug work-around */
196
197 switch (IFM_SUBTYPE(ife->ifm_media)) {
198 case IFM_AUTO:
199 #ifdef foo
200 /*
201 * If we're already in auto mode, just return.
202 */
203 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
204 return (0);
205 #endif
206 (void) brgphy_mii_phy_auto(sc);
207 break;
208 case IFM_1000_T:
209 speed = BRGPHY_S1000;
210 goto setit;
211 case IFM_100_T4:
212 speed = BRGPHY_S100;
213 goto setit;
214 case IFM_100_TX:
215 speed = BRGPHY_S100;
216 goto setit;
217 case IFM_10_T:
218 speed = BRGPHY_S10;
219 setit:
220 brgphy_loop(sc);
221 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
222 speed |= BRGPHY_BMCR_FDX;
223 gig = BRGPHY_1000CTL_AFD;
224 } else {
225 gig = BRGPHY_1000CTL_AHD;
226 }
227
228 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
229 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
230 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
231
232 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
233 break;
234
235 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
236 PHY_WRITE(sc, BRGPHY_MII_BMCR,
237 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
238
239 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
240 break;
241 break;
242 default:
243 return (EINVAL);
244 }
245 break;
246
247 case MII_TICK:
248 /*
249 * If we're not currently selected, just return.
250 */
251 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
252 return (0);
253
254 /*
255 * Is the interface even up?
256 */
257 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
258 return (0);
259
260 /*
261 * Only used for autonegotiation.
262 */
263 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
264 break;
265
266 /*
267 * Check to see if we have link. If we do, we don't
268 * need to restart the autonegotiation process. Read
269 * the BMSR twice in case it's latched.
270 */
271 reg = PHY_READ(sc, BRGPHY_MII_AUXSTS);
272 if (reg & BRGPHY_AUXSTS_LINK)
273 break;
274
275 /*
276 * Only retry autonegotiation every mii_anegticks seconds.
277 */
278 if (++sc->mii_ticks <= sc->mii_anegticks)
279 return (0);
280
281 sc->mii_ticks = 0;
282 brgphy_mii_phy_auto(sc);
283 return (0);
284 }
285
286 /* Update the media status. */
287 brgphy_status(sc);
288
289 /*
290 * Callback if something changed. Note that we need to poke the DSP on
291 * the Broadcom PHYs if the media changes.
292 */
293 if (sc->mii_media_active != mii->mii_media_active ||
294 sc->mii_media_status != mii->mii_media_status ||
295 cmd == MII_MEDIACHG) {
296 mii_phy_update(sc, cmd);
297 switch (sc->mii_model) {
298 case MII_MODEL_BROADCOM_BCM5400:
299 case MII_MODEL_xxBROADCOM_BCM5401:
300 case MII_MODEL_xxBROADCOM_BCM5411:
301 brgphy_load_dspcode(sc);
302 break;
303 }
304 }
305
306 return (0);
307 }
308
309 void
brgphy_status(struct mii_softc * sc)310 brgphy_status(struct mii_softc *sc)
311 {
312 struct mii_data *mii = sc->mii_pdata;
313 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
314 int bmsr, bmcr;
315
316 mii->mii_media_status = IFM_AVALID;
317 mii->mii_media_active = IFM_ETHER;
318
319 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
320 if (PHY_READ(sc, BRGPHY_MII_AUXSTS) & BRGPHY_AUXSTS_LINK)
321 mii->mii_media_status |= IFM_ACTIVE;
322
323 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
324
325 if (bmcr & BRGPHY_BMCR_LOOP)
326 mii->mii_media_active |= IFM_LOOP;
327
328 if (bmcr & BRGPHY_BMCR_AUTOEN) {
329 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
330 /* Erg, still trying, I guess... */
331 mii->mii_media_active |= IFM_NONE;
332 return;
333 }
334
335 switch (PHY_READ(sc, BRGPHY_MII_AUXSTS) &
336 BRGPHY_AUXSTS_AN_RES) {
337 case BRGPHY_RES_1000FD:
338 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
339 break;
340 case BRGPHY_RES_1000HD:
341 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
342 break;
343 case BRGPHY_RES_100FD:
344 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
345 break;
346 case BRGPHY_RES_100T4:
347 mii->mii_media_active |= IFM_100_T4;
348 break;
349 case BRGPHY_RES_100HD:
350 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
351 break;
352 case BRGPHY_RES_10FD:
353 mii->mii_media_active |= IFM_10_T | IFM_FDX;
354 break;
355 case BRGPHY_RES_10HD:
356 mii->mii_media_active |= IFM_10_T | IFM_HDX;
357 break;
358 default:
359 mii->mii_media_active |= IFM_NONE;
360 break;
361 }
362 return;
363 }
364
365 mii->mii_media_active = ife->ifm_media;
366 }
367
368
369 int
brgphy_mii_phy_auto(struct mii_softc * sc)370 brgphy_mii_phy_auto(struct mii_softc *sc)
371 {
372 int ktcr = 0;
373
374 brgphy_loop(sc);
375 /* XXX need 'PHY_RESET(sc);'? Was done before getting here ... */
376 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
377 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
378 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
379 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
380 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
381 DELAY(1000);
382 PHY_WRITE(sc, BRGPHY_MII_ANAR,
383 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
384 DELAY(1000);
385 PHY_WRITE(sc, BRGPHY_MII_BMCR,
386 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
387 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
388
389 return (EJUSTRETURN);
390 }
391
392 void
brgphy_loop(struct mii_softc * sc)393 brgphy_loop(struct mii_softc *sc)
394 {
395 u_int32_t bmsr;
396 int i;
397
398 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
399 for (i = 0; i < 15000; i++) {
400 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
401 if (!(bmsr & BRGPHY_BMSR_LINK)) {
402 break;
403 }
404 DELAY(10);
405 }
406 }
407
408 void
brgphy_reset(struct mii_softc * sc)409 brgphy_reset(struct mii_softc *sc)
410 {
411 struct bge_softc *bge_sc;
412 struct ifnet *ifp;
413 u_int32_t val;
414
415 mii_phy_reset(sc);
416
417 ifp = sc->mii_pdata->mii_ifp;
418 bge_sc = ifp->if_softc;
419
420 brgphy_load_dspcode(sc);
421
422 /*
423 * Don't enable Ethernet@WireSpeed for the 5700 or the
424 * 5705 A1 and A2 chips. Make sure we only do this test
425 * on "bge" NICs, since other drivers may use this same
426 * PHY subdriver.
427 */
428 if (strncmp(ifp->if_xname, "bge", 3) == 0 &&
429 (BGE_ASICREV(bge_sc->bge_chipid) == BGE_ASICREV_BCM5700 ||
430 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A1 ||
431 bge_sc->bge_chipid == BGE_CHIPID_BCM5705_A2))
432 return;
433
434 /* Enable Ethernet@WireSpeed. */
435 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
436 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
437 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, val | (1 << 15) | (1 << 4));
438
439 /* Enable Link LED on Dell boxes */
440 if (bge_sc->bge_no_3_led) {
441 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
442 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL)
443 & ~BRGPHY_PHY_EXTCTL_3_LED);
444 }
445 }
446
447 struct bcm_dspcode {
448 int reg;
449 u_int16_t val;
450 };
451
452 static const struct bcm_dspcode bcm5401_dspcode[] = {
453 { BRGPHY_MII_AUXCTL, 0x0c20 },
454 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
455 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
456 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
457 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
458 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
459 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
460 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
461 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
462 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
463 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
464 { 0, 0 },
465 };
466
467 static const struct bcm_dspcode bcm5411_dspcode[] = {
468 { 0x1c, 0x8c23 },
469 { 0x1c, 0x8ca3 },
470 { 0x1c, 0x8c23 },
471 { 0, 0 },
472 };
473
474 static const struct bcm_dspcode bcm5703_dspcode[] = {
475 { BRGPHY_MII_AUXCTL, 0x0c00 },
476 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
477 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
478 { 0, 0 },
479 };
480
481 static const struct bcm_dspcode bcm5704_dspcode[] = {
482 { 0x1c, 0x8d68 },
483 { 0x1c, 0x8d68 },
484 { 0, 0 },
485 };
486
487 static const struct bcm_dspcode bcm5750_dspcode[] = {
488 { BRGPHY_MII_AUXCTL, 0x0c00 },
489 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
490 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
491 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
492 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
493 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
494 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
495 { BRGPHY_MII_AUXCTL, 0x0400 },
496 { 0, 0 },
497 };
498
499 void
brgphy_load_dspcode(struct mii_softc * sc)500 brgphy_load_dspcode(struct mii_softc *sc)
501 {
502 const struct bcm_dspcode *dsp = NULL;
503 int wait=0, i;
504
505 switch (sc->mii_model) {
506 case MII_MODEL_BROADCOM_BCM5400:
507 dsp = bcm5401_dspcode;
508 wait=40;
509 break;
510 case MII_MODEL_BROADCOM_BCM5401:
511 if (sc->mii_rev == 1 || sc->mii_rev == 3) {
512 dsp = bcm5401_dspcode;
513 wait=40;
514 }
515 break;
516 case MII_MODEL_BROADCOM_BCM5411:
517 dsp = bcm5411_dspcode;
518 break;
519 case MII_MODEL_xxBROADCOM_BCM5703:
520 dsp = bcm5703_dspcode;
521 break;
522 case MII_MODEL_xxBROADCOM_BCM5704:
523 dsp = bcm5704_dspcode;
524 break;
525 case MII_MODEL_xxBROADCOM_BCM5714:
526 case MII_MODEL_xxBROADCOM_BCM5750:
527 dsp = bcm5750_dspcode;
528 break;
529 }
530
531 if (dsp == NULL)
532 return;
533
534 for (i = 0; dsp[i].reg != 0; i++)
535 PHY_WRITE(sc, dsp[i].reg, dsp[i].val);
536
537 if (wait > 0)
538 DELAY(wait);
539 }
540