1 /* $OpenBSD: if_edreg.h,v 1.6 2002/06/03 20:01:37 deraadt Exp $ */ 2 /* $NetBSD: if_edreg.h,v 1.15 1996/01/10 16:49:22 chuck Exp $ */ 3 4 /* 5 * National Semiconductor DS8390 NIC register definitions. 6 * 7 * Copyright (C) 1993, David Greenman. This software may be used, modified, 8 * copied, distributed, and sold, in both source and binary form provided that 9 * the above copyright and these terms are retained. Under no circumstances is 10 * the author responsible for the proper functioning of this software, nor does 11 * the author assume any responsibility for damages incurred with its use. 12 */ 13 14 /* 15 * Vendor types 16 */ 17 #define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ 18 #define ED_VENDOR_3COM 0x01 /* 3Com */ 19 #define ED_VENDOR_NOVELL 0x02 /* Novell */ 20 21 /* 22 * Compile-time config flags 23 */ 24 /* 25 * This sets the default for enabling/disablng the transceiver. 26 */ 27 #define ED_FLAGS_DISABLE_TRANSCEIVER 0x0001 28 29 /* 30 * This forces the board to be used in 8/16-bit mode even if it autoconfigs 31 * differently. 32 */ 33 #define ED_FLAGS_FORCE_8BIT_MODE 0x0002 34 #define ED_FLAGS_FORCE_16BIT_MODE 0x0004 35 36 /* 37 * This disables the use of double transmit buffers. 38 */ 39 #define ED_FLAGS_NO_MULTI_BUFFERING 0x0008 40 41 /* 42 * This forces all operations with the NIC memory to use Programmed I/O (i.e. 43 * not via shared memory). 44 */ 45 #define ED_FLAGS_FORCE_PIO 0x0010 46 47 /* 48 * Definitions for Western digital/SMC WD80x3 series ASIC 49 */ 50 /* 51 * Memory Select Register (MSR) 52 */ 53 #define ED_WD_MSR 0 54 55 /* next three definitions for Toshiba */ 56 #define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */ 57 #define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */ 58 #define ED_WD_MSR_LEN 0x20 /* 0 = 16-bit, 1 = 8-bit (R/W) */ 59 60 #define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ 61 #define ED_WD_MSR_MENB 0x40 /* Memory enable */ 62 #define ED_WD_MSR_RST 0x80 /* Reset board */ 63 64 /* 65 * Interface Configuration Register (ICR) 66 */ 67 #define ED_WD_ICR 1 68 69 #define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ 70 #define ED_WD_ICR_OAR 0x02 /* select register (0=BIO 1=EAR) */ 71 #define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ 72 #define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ 73 #define ED_WD_ICR_RLA 0x10 /* recall LAN address */ 74 #define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ 75 #define ED_WD_ICR_RIO 0x40 /* recall i/o address */ 76 #define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ 77 #ifdef TOSH_ETHER 78 #define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */ 79 #define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K, 80 0x02 = 16K, 0x01 = 8K */ 81 /* 64K can only be used if mem address 82 above 1MB */ 83 /* IAR holds address A23-A16 (R/W) */ 84 #endif 85 86 /* 87 * IO Address Register (IAR) 88 */ 89 #define ED_WD_IAR 2 90 91 /* 92 * EEROM Address Register 93 */ 94 #define ED_WD_EAR 3 95 96 /* 97 * Interrupt Request Register (IRR) 98 */ 99 #define ED_WD_IRR 4 100 101 #define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ 102 #define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ 103 #define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ 104 #define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ 105 #define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ 106 107 /* 108 * The three bits of the encoded IRQ are decoded as follows: 109 * 110 * IR2 IR1 IR0 IRQ 111 * 0 0 0 2/9 112 * 0 0 1 3 113 * 0 1 0 5 114 * 0 1 1 7 115 * 1 0 0 10 116 * 1 0 1 11 117 * 1 1 0 15 118 * 1 1 1 4 119 */ 120 #define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ 121 #define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ 122 #define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ 123 124 /* 125 * LA Address Register (LAAR) 126 */ 127 #define ED_WD_LAAR 5 128 129 #define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ 130 #define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ 131 #define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ 132 #define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ 133 134 /* i/o base offset to station address/card-ID PROM */ 135 #define ED_WD_PROM 8 136 137 /* 138 * 83C790 specific registers 139 */ 140 /* 141 * Hardware Support Register (HWR) ('790) 142 */ 143 #define ED_WD790_HWR 4 144 145 #define ED_WD790_HWR_RST 0x10 /* hardware reset */ 146 #define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */ 147 #define ED_WD790_HWR_SWH 0x80 /* switch register set */ 148 149 /* 150 * ICR790 Interrupt Control Register for the 83C790 151 */ 152 #define ED_WD790_ICR 6 153 154 #define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ 155 156 /* 157 * REV/IOPA Revision / I/O Pipe register for the 83C79X 158 */ 159 #define ED_WD790_REV 7 160 161 #define ED_WD790 0x20 /* and 0x21... */ 162 #define ED_WD795 0x40 /* and 0x41... */ 163 164 /* 165 * PIO mode register for the 83C795 166 */ 167 #define ED_WD795_PIO 8 168 169 /* 170 * 79X RAM Address Register (RAR) 171 * Enabled with SWH bit=1 in HWR register 172 */ 173 174 #define ED_WD790_RAR 0x0b 175 176 #define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ 177 #define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ 178 #define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ 179 #define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ 180 181 /* 182 * General Control Register (GCR) 183 * Eanbled with SWH bit == 1 in HWR register 184 */ 185 #define ED_WD790_GCR 0x0d 186 187 #define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */ 188 #define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */ 189 #define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */ 190 #define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */ 191 /* 192 * The three bits of the encoded IRQ are decoded as follows: 193 * 194 * IR2 IR1 IR0 IRQ 195 * 0 0 0 none 196 * 0 0 1 9 197 * 0 1 0 3 198 * 0 1 1 5 199 * 1 0 0 7 200 * 1 0 1 10 201 * 1 1 0 11 202 * 1 1 1 15 203 */ 204 205 /* i/o base offset to CARD ID */ 206 #define ED_WD_CARD_ID ED_WD_PROM+6 207 208 /* Board type codes in card ID */ 209 #define ED_TYPE_WD8003S 0x02 210 #define ED_TYPE_WD8003E 0x03 211 #define ED_TYPE_WD8013EBT 0x05 212 #define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */ 213 #define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */ 214 #define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */ 215 #define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */ 216 #define ED_TYPE_WD8003W 0x24 217 #define ED_TYPE_WD8003EB 0x25 218 #define ED_TYPE_WD8013W 0x26 219 #define ED_TYPE_WD8013EP 0x27 220 #define ED_TYPE_WD8013WC 0x28 221 #define ED_TYPE_WD8013EPC 0x29 222 #define ED_TYPE_SMC8216T 0x2a 223 #define ED_TYPE_SMC8216C 0x2b 224 #define ED_TYPE_WD8013EBP 0x2c 225 226 /* Bit definitions in card ID */ 227 #define ED_WD_REV_MASK 0x1f /* Revision mask */ 228 #define ED_WD_SOFTCONFIG 0x20 /* Soft config */ 229 #define ED_WD_LARGERAM 0x40 /* Large RAM */ 230 #define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ 231 232 /* 233 * Checksum total. All 8 bytes in station address PROM will add up to this. 234 */ 235 #ifdef TOSH_ETHER 236 #define ED_WD_ROM_CHECKSUM_TOTAL 0xA5 237 #else 238 #define ED_WD_ROM_CHECKSUM_TOTAL 0xFF 239 #endif 240 241 #define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ 242 #define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ 243 #define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ 244 245 #define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ 246 247 /* 248 * Definitions for 3Com 3c503 249 */ 250 #define ED_3COM_NIC_OFFSET 0 251 #define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ 252 253 /* 254 * XXX - The I/O address range is fragmented in the 3c503; this is the 255 * number of regs at iobase. 256 */ 257 #define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ 258 259 /* tx memory starts in second bank on 8bit cards */ 260 #define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20 261 262 /* tx memory starts in first bank on 16bit cards */ 263 #define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0 264 265 /* ...and rx memory starts in second bank */ 266 #define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20 267 268 269 /* 270 * Page Start Register. Must match PSTART in NIC. 271 */ 272 #define ED_3COM_PSTR 0 273 274 /* 275 * Page Stop Register. Must match PSTOP in NIC. 276 */ 277 #define ED_3COM_PSPR 1 278 279 /* 280 * DrQ Timer Register. Determines number of bytes to be transferred during a 281 * DMA burst. 282 */ 283 #define ED_3COM_DQTR 2 284 285 /* 286 * Base Configuration Register. Read-only register which contains the 287 * board-configured I/O base address of the adapter. Bit encoded. 288 */ 289 #define ED_3COM_BCFR 3 290 291 /* 292 * EPROM Configuration Register. Read-only register which contains the 293 * board-configured memory base address. Bit encoded. 294 */ 295 #define ED_3COM_PCFR 4 296 297 /* 298 * GA Configuration Register. Gate-Array Configuration Register. 299 * 300 * mbs2 mbs1 mbs0 start address 301 * 0 0 0 0x0000 302 * 0 0 1 0x2000 303 * 0 1 0 0x4000 304 * 0 1 1 0x6000 305 * 306 * Note that with adapters with only 8K, the setting for 0x2000 must always be 307 * used. 308 */ 309 #define ED_3COM_GACFR 5 310 311 #define ED_3COM_GACFR_MBS0 0x01 312 #define ED_3COM_GACFR_MBS1 0x02 313 #define ED_3COM_GACFR_MBS2 0x04 314 315 #define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ 316 #define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ 317 #define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ 318 #define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ 319 #define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ 320 321 /* 322 * Control Register. Miscellaneous control functions. 323 */ 324 #define ED_3COM_CR 6 325 326 #define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ 327 #define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ 328 #define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ 329 #define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ 330 #define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ 331 #define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ 332 #define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ 333 #define ED_3COM_CR_START 0x80 /* Start DMA controller */ 334 335 /* 336 * Status Register. Miscellaneous status information. 337 */ 338 #define ED_3COM_STREG 7 339 340 #define ED_3COM_STREG_REV 0x07 /* GA revision */ 341 #define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ 342 #define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ 343 #define ED_3COM_STREG_OFLW 0x20 /* Overflow */ 344 #define ED_3COM_STREG_UFLW 0x40 /* Underflow */ 345 #define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ 346 347 /* 348 * Interrupt/DMA Configuration Register 349 */ 350 #define ED_3COM_IDCFR 8 351 352 #define ED_3COM_IDCFR_DRQ 0x07 /* DMA request */ 353 #define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ 354 #if 0 355 #define ED_3COM_IDCFR_IRQ 0xF0 /* Interrupt request */ 356 #else 357 #define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ 358 #define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ 359 #define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ 360 #define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ 361 #endif 362 363 /* 364 * DMA Address Register MSB 365 */ 366 #define ED_3COM_DAMSB 9 367 368 /* 369 * DMA Address Register LSB 370 */ 371 #define ED_3COM_DALSB 0x0a 372 373 /* 374 * Vector Pointer Register 2 375 */ 376 #define ED_3COM_VPTR2 0x0b 377 378 /* 379 * Vector Pointer Register 1 380 */ 381 #define ED_3COM_VPTR1 0x0c 382 383 /* 384 * Vector Pointer Register 0 385 */ 386 #define ED_3COM_VPTR0 0x0d 387 388 /* 389 * Register File Access MSB 390 */ 391 #define ED_3COM_RFMSB 0x0e 392 393 /* 394 * Register File Access LSB 395 */ 396 #define ED_3COM_RFLSB 0x0f 397 398 /* 399 * Definitions for Novell NE1000/2000 boards 400 */ 401 402 /* 403 * Board type codes 404 */ 405 #define ED_TYPE_NE1000 0x01 406 #define ED_TYPE_NE2000 0x02 407 408 /* 409 * Register offsets/total 410 */ 411 #define ED_NOVELL_NIC_OFFSET 0x00 412 #define ED_NOVELL_ASIC_OFFSET 0x10 413 #define ED_NOVELL_IO_PORTS 32 414 415 /* 416 * Remote DMA data register; for reading or writing to the NIC mem via 417 * programmed I/O (offset from ASIC base). 418 */ 419 #define ED_NOVELL_DATA 0x00 420 421 /* 422 * Reset register; reading from this register causes a board reset. 423 */ 424 #define ED_NOVELL_RESET 0x0f 425