1 /* $OpenBSD: xlreg.h,v 1.17 2003/10/21 18:58:50 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD: if_xlreg.h,v 1.26 2000/08/28 20:40:03 wpaul Exp $ 35 */ 36 37 #define XL_EE_READ 0x0080 /* read, 5 bit address */ 38 #define XL_EE_8BIT_READ 0x0200 /* read, 8 bit address */ 39 #define XL_EE_WRITE 0x0040 /* write, 5 bit address */ 40 #define XL_EE_ERASE 0x00c0 /* erase, 5 bit address */ 41 #define XL_EE_EWEN 0x0030 /* erase, no data needed */ 42 #define XL_EE_BUSY 0x8000 43 44 #define XL_EE_EADDR0 0x00 /* station address, first word */ 45 #define XL_EE_EADDR1 0x01 /* station address, next word, */ 46 #define XL_EE_EADDR2 0x02 /* station address, last word */ 47 #define XL_EE_PRODID 0x03 /* product ID code */ 48 #define XL_EE_MDATA_DATE 0x04 /* manufacturing data, date */ 49 #define XL_EE_MDATA_DIV 0x05 /* manufacturing data, division */ 50 #define XL_EE_MDATA_PCODE 0x06 /* manufacturing data, product code */ 51 #define XL_EE_MFG_ID 0x07 52 #define XL_EE_PCI_PARM 0x08 53 #define XL_EE_ROM_ONFO 0x09 54 #define XL_EE_OEM_ADR0 0x0A 55 #define XL_EE_OEM_ADR1 0x0B 56 #define XL_EE_OEM_ADR2 0x0C 57 #define XL_EE_SOFTINFO1 0x0D 58 #define XL_EE_COMPAT 0x0E 59 #define XL_EE_SOFTINFO2 0x0F 60 #define XL_EE_CAPS 0x10 /* capabilities word */ 61 #define XL_EE_RSVD0 0x11 62 #define XL_EE_ICFG_0 0x12 63 #define XL_EE_ICFG_1 0x13 64 #define XL_EE_RSVD1 0x14 65 #define XL_EE_SOFTINFO3 0x15 66 #define XL_EE_RSVD_2 0x16 67 68 /* 69 * Bits in the capabilities word 70 */ 71 #define XL_CAPS_PNP 0x0001 72 #define XL_CAPS_FULL_DUPLEX 0x0002 73 #define XL_CAPS_LARGE_PKTS 0x0004 74 #define XL_CAPS_SLAVE_DMA 0x0008 75 #define XL_CAPS_SECOND_DMA 0x0010 76 #define XL_CAPS_FULL_BM 0x0020 77 #define XL_CAPS_FRAG_BM 0x0040 78 #define XL_CAPS_CRC_PASSTHRU 0x0080 79 #define XL_CAPS_TXDONE 0x0100 80 #define XL_CAPS_NO_TXLENGTH 0x0200 81 #define XL_CAPS_RX_REPEAT 0x0400 82 #define XL_CAPS_SNOOPING 0x0800 83 #define XL_CAPS_100MBPS 0x1000 84 #define XL_CAPS_PWRMGMT 0x2000 85 86 #define XL_PACKET_SIZE 1536 87 88 /* 89 * Register layouts. 90 */ 91 #define XL_COMMAND 0x0E 92 #define XL_STATUS 0x0E 93 94 #define XL_TX_STATUS 0x1B 95 #define XL_TX_FREE 0x1C 96 #define XL_DMACTL 0x20 97 #define XL_DOWNLIST_PTR 0x24 98 #define XL_DOWN_POLL 0x2D /* 3c90xB only */ 99 #define XL_TX_FREETHRESH 0x2F 100 #define XL_UPLIST_PTR 0x38 101 #define XL_UPLIST_STATUS 0x30 102 #define XL_UP_POLL 0x3D /* 3c90xB only */ 103 104 #define XL_PKTSTAT_UP_STALLED 0x00002000 105 #define XL_PKTSTAT_UP_ERROR 0x00004000 106 #define XL_PKTSTAT_UP_CMPLT 0x00008000 107 108 #define XL_DMACTL_DN_CMPLT_REQ 0x00000002 109 #define XL_DMACTL_DOWN_STALLED 0x00000004 110 #define XL_DMACTL_UP_CMPLT 0x00000008 111 #define XL_DMACTL_DOWN_CMPLT 0x00000010 112 #define XL_DMACTL_UP_RX_EARLY 0x00000020 113 #define XL_DMACTL_ARM_COUNTDOWN 0x00000040 114 #define XL_DMACTL_DOWN_INPROG 0x00000080 115 #define XL_DMACTL_COUNTER_SPEED 0x00000100 116 #define XL_DMACTL_DOWNDOWN_MODE 0x00000200 117 #define XL_DMACTL_TARGET_ABORT 0x40000000 118 #define XL_DMACTL_MASTER_ABORT 0x80000000 119 120 /* 121 * Command codes. Some command codes require that we wait for 122 * the CMD_BUSY flag to clear. Those codes are marked as 'mustwait.' 123 */ 124 #define XL_CMD_RESET 0x0000 /* mustwait */ 125 #define XL_CMD_WINSEL 0x0800 126 #define XL_CMD_COAX_START 0x1000 127 #define XL_CMD_RX_DISABLE 0x1800 128 #define XL_CMD_RX_ENABLE 0x2000 129 #define XL_CMD_RX_RESET 0x2800 /* mustwait */ 130 #define XL_CMD_UP_STALL 0x3000 /* mustwait */ 131 #define XL_CMD_UP_UNSTALL 0x3001 132 #define XL_CMD_DOWN_STALL 0x3002 /* mustwait */ 133 #define XL_CMD_DOWN_UNSTALL 0x3003 134 #define XL_CMD_RX_DISCARD 0x4000 135 #define XL_CMD_TX_ENABLE 0x4800 136 #define XL_CMD_TX_DISABLE 0x5000 137 #define XL_CMD_TX_RESET 0x5800 /* mustwait */ 138 #define XL_CMD_INTR_FAKE 0x6000 139 #define XL_CMD_INTR_ACK 0x6800 140 #define XL_CMD_INTR_ENB 0x7000 141 #define XL_CMD_STAT_ENB 0x7800 142 #define XL_CMD_RX_SET_FILT 0x8000 143 #define XL_CMD_RX_SET_THRESH 0x8800 144 #define XL_CMD_TX_SET_THRESH 0x9000 145 #define XL_CMD_TX_SET_START 0x9800 146 #define XL_CMD_DMA_UP 0xA000 147 #define XL_CMD_DMA_STOP 0xA001 148 #define XL_CMD_STATS_ENABLE 0xA800 149 #define XL_CMD_STATS_DISABLE 0xB000 150 #define XL_CMD_COAX_STOP 0xB800 151 152 #define XL_CMD_SET_TX_RECLAIM 0xC000 /* 3c905B only */ 153 #define XL_CMD_RX_SET_HASH 0xC800 /* 3c905B only */ 154 155 #define XL_HASH_SET 0x0400 156 #define XL_HASHFILT_SIZE 256 157 158 /* 159 * status codes 160 * Note that bits 15 to 13 indicate the currently visible register window 161 * which may be anything from 0 to 7. 162 */ 163 #define XL_STAT_INTLATCH 0x0001 /* 0 */ 164 #define XL_STAT_ADFAIL 0x0002 /* 1 */ 165 #define XL_STAT_TX_COMPLETE 0x0004 /* 2 */ 166 #define XL_STAT_TX_AVAIL 0x0008 /* 3 first generation */ 167 #define XL_STAT_RX_COMPLETE 0x0010 /* 4 */ 168 #define XL_STAT_RX_EARLY 0x0020 /* 5 */ 169 #define XL_STAT_INTREQ 0x0040 /* 6 */ 170 #define XL_STAT_STATSOFLOW 0x0080 /* 7 */ 171 #define XL_STAT_DMADONE 0x0100 /* 8 first generation */ 172 #define XL_STAT_LINKSTAT 0x0100 /* 8 3c509B */ 173 #define XL_STAT_DOWN_COMPLETE 0x0200 /* 9 */ 174 #define XL_STAT_UP_COMPLETE 0x0400 /* 10 */ 175 #define XL_STAT_DMABUSY 0x0800 /* 11 first generation */ 176 #define XL_STAT_CMDBUSY 0x1000 /* 12 */ 177 178 /* 179 * Interrupts we normally want enabled. 180 */ 181 #define XL_INTRS \ 182 (XL_STAT_UP_COMPLETE|XL_STAT_STATSOFLOW|XL_STAT_ADFAIL| \ 183 XL_STAT_DOWN_COMPLETE|XL_STAT_TX_COMPLETE|XL_STAT_INTLATCH) 184 185 /* 186 * Window 0 registers 187 */ 188 #define XL_W0_EE_DATA 0x0C 189 #define XL_W0_EE_CMD 0x0A 190 #define XL_W0_RSRC_CFG 0x08 191 #define XL_W0_ADDR_CFG 0x06 192 #define XL_W0_CFG_CTRL 0x04 193 194 #define XL_W0_PROD_ID 0x02 195 #define XL_W0_MFG_ID 0x00 196 197 /* 198 * Window 1 199 */ 200 201 #define XL_W1_TX_FIFO 0x10 202 203 #define XL_W1_FREE_TX 0x0C 204 #define XL_W1_TX_STATUS 0x0B 205 #define XL_W1_TX_TIMER 0x0A 206 #define XL_W1_RX_STATUS 0x08 207 #define XL_W1_RX_FIFO 0x00 208 209 /* 210 * RX status codes 211 */ 212 #define XL_RXSTATUS_OVERRUN 0x01 213 #define XL_RXSTATUS_RUNT 0x02 214 #define XL_RXSTATUS_ALIGN 0x04 215 #define XL_RXSTATUS_CRC 0x08 216 #define XL_RXSTATUS_OVERSIZE 0x10 217 #define XL_RXSTATUS_DRIBBLE 0x20 218 219 /* 220 * TX status codes 221 */ 222 #define XL_TXSTATUS_RECLAIM 0x02 /* 3c905B only */ 223 #define XL_TXSTATUS_OVERFLOW 0x04 224 #define XL_TXSTATUS_MAXCOLS 0x08 225 #define XL_TXSTATUS_UNDERRUN 0x10 226 #define XL_TXSTATUS_JABBER 0x20 227 #define XL_TXSTATUS_INTREQ 0x40 228 #define XL_TXSTATUS_COMPLETE 0x80 229 230 /* 231 * Window 2 232 */ 233 #define XL_W2_RESET_OPTIONS 0x0C /* 3c905B only */ 234 #define XL_W2_STATION_MASK_HI 0x0A 235 #define XL_W2_STATION_MASK_MID 0x08 236 #define XL_W2_STATION_MASK_LO 0x06 237 #define XL_W2_STATION_ADDR_HI 0x04 238 #define XL_W2_STATION_ADDR_MID 0x02 239 #define XL_W2_STATION_ADDR_LO 0x00 240 241 #define XL_RESETOPT_FEATUREMASK 0x0001|0x0002|0x004 242 #define XL_RESETOPT_D3RESETDIS 0x0008 243 #define XL_RESETOPT_DISADVFD 0x0010 244 #define XL_RESETOPT_DISADV100 0x0020 245 #define XL_RESETOPT_DISAUTONEG 0x0040 246 #define XL_RESETOPT_DEBUGMODE 0x0080 247 #define XL_RESETOPT_FASTAUTO 0x0100 248 #define XL_RESETOPT_FASTEE 0x0200 249 #define XL_RESETOPT_FORCEDCONF 0x0400 250 #define XL_RESETOPT_TESTPDTPDR 0x0800 251 #define XL_RESETOPT_TEST100TX 0x1000 252 #define XL_RESETOPT_TEST100RX 0x2000 253 #define XL_RESETOPT_INVMIIPWR 0x4000 /* some 3c905Bs only */ 254 /* 255 * Window 3 (fifo management) 256 */ 257 #define XL_W3_INTERNAL_CFG 0x00 258 #define XL_W3_MAX_PKT_SIZE 0x04 /* 3C905B only */ 259 #define XL_W3_RESET_OPT 0x08 260 #define XL_W3_FREE_TX 0x0C 261 #define XL_W3_FREE_RX 0x0A 262 #define XL_W3_MAC_CTRL 0x06 263 264 #define XL_ICFG_CONNECTOR_MASK 0x00F00000 265 #define XL_ICFG_CONNECTOR_BITS 20 266 267 #define XL_ICFG_RAMSIZE_MASK 0x00000007 268 #define XL_ICFG_RAMWIDTH 0x00000008 269 #define XL_ICFG_ROMSIZE_MASK (0x00000040|0x00000080) 270 #define XL_ICFG_DISABLE_BASSD 0x00000100 271 #define XL_ICFG_RAMLOC 0x00000200 272 #define XL_ICFG_RAMPART (0x00010000|0x00020000) 273 #define XL_ICFG_XCVRSEL (0x00100000|0x00200000|0x00400000) 274 #define XL_ICFG_AUTOSEL 0x01000000 275 276 #define XL_XCVR_10BT 0x00 277 #define XL_XCVR_AUI 0x01 278 #define XL_XCVR_RSVD_0 0x02 279 #define XL_XCVR_COAX 0x03 280 #define XL_XCVR_100BTX 0x04 281 #define XL_XCVR_100BFX 0x05 282 #define XL_XCVR_MII 0x06 283 #define XL_XCVR_RSVD_1 0x07 284 #define XL_XCVR_AUTO 0x08 /* 3c905B only */ 285 #define XL_XCVR_NWAY 0x09 /* 3CCFE575CT CardBus */ 286 287 #define XL_MACCTRL_DEFER_EXT_END 0x0001 288 #define XL_MACCTRL_DEFER_0 0x0002 289 #define XL_MACCTRL_DEFER_1 0x0004 290 #define XL_MACCTRL_DEFER_2 0x0008 291 #define XL_MACCTRL_DEFER_3 0x0010 292 #define XL_MACCTRL_DUPLEX 0x0020 293 #define XL_MACCTRL_ALLOW_LARGE_PACK 0x0040 294 #define XL_MACCTRL_EXTEND_AFTER_COL 0x0080 (3c905B only) 295 #define XL_MACCTRL_FLOW_CONTROL_ENB 0x0100 (3c905B only) 296 #define XL_MACCTRL_VLT_END 0x0200 (3c905B only) 297 298 /* 299 * The 'reset options' register contains power-on reset values 300 * loaded from the EEPROM. This includes the supported media 301 * types on the card. It is also known as the media options register. 302 */ 303 #define XL_W3_MEDIA_OPT 0x08 304 305 #define XL_MEDIAOPT_BT4 0x0001 /* MII */ 306 #define XL_MEDIAOPT_BTX 0x0002 /* on-chip */ 307 #define XL_MEDIAOPT_BFX 0x0004 /* on-chip */ 308 #define XL_MEDIAOPT_BT 0x0008 /* on-chip */ 309 #define XL_MEDIAOPT_BNC 0x0010 /* on-chip */ 310 #define XL_MEDIAOPT_AUI 0x0020 /* on-chip */ 311 #define XL_MEDIAOPT_MII 0x0040 /* MII */ 312 #define XL_MEDIAOPT_VCO 0x0100 /* 1st gen chip only */ 313 314 #define XL_MEDIAOPT_10FL 0x0100 /* 3x905B only, on-chip */ 315 #define XL_MEDIAOPT_MASK 0x01FF 316 317 /* 318 * Window 4 (diagnostics) 319 */ 320 #define XL_W4_UPPERBYTESOK 0x0D 321 #define XL_W4_BADSSD 0x0C 322 #define XL_W4_MEDIA_STATUS 0x0A 323 #define XL_W4_PHY_MGMT 0x08 324 #define XL_W4_NET_DIAG 0x06 325 #define XL_W4_FIFO_DIAG 0x04 326 #define XL_W4_VCO_DIAG 0x02 327 328 #define XL_W4_CTRLR_STAT 0x08 329 #define XL_W4_TX_DIAG 0x00 330 331 #define XL_MII_CLK 0x01 332 #define XL_MII_DATA 0x02 333 #define XL_MII_DIR 0x04 334 335 #define XL_MEDIA_SQE 0x0008 336 #define XL_MEDIA_10TP 0x00C0 337 #define XL_MEDIA_LNK 0x0080 338 #define XL_MEDIA_LNKBEAT 0x0800 339 340 #define XL_MEDIASTAT_CRCSTRIP 0x0004 341 #define XL_MEDIASTAT_SQEENB 0x0008 342 #define XL_MEDIASTAT_COLDET 0x0010 343 #define XL_MEDIASTAT_CARRIER 0x0020 344 #define XL_MEDIASTAT_JABGUARD 0x0040 345 #define XL_MEDIASTAT_LINKBEAT 0x0080 346 #define XL_MEDIASTAT_JABDETECT 0x0200 347 #define XL_MEDIASTAT_POLREVERS 0x0400 348 #define XL_MEDIASTAT_LINKDETECT 0x0800 349 #define XL_MEDIASTAT_TXINPROG 0x1000 350 #define XL_MEDIASTAT_DCENB 0x4000 351 #define XL_MEDIASTAT_AUIDIS 0x8000 352 353 #define XL_NETDIAG_TEST_LOWVOLT 0x0001 354 #define XL_NETDIAG_ASIC_REVMASK (0x0002|0x0004|0x0008|0x0010|0x0020) 355 #define XL_NETDIAG_UPPER_BYTES_ENABLE 0x0040 356 #define XL_NETDIAG_STATS_ENABLED 0x0080 357 #define XL_NETDIAG_TX_FATALERR 0x0100 358 #define XL_NETDIAG_TRANSMITTING 0x0200 359 #define XL_NETDIAG_RX_ENABLED 0x0400 360 #define XL_NETDIAG_TX_ENABLED 0x0800 361 #define XL_NETDIAG_FIFO_LOOPBACK 0x1000 362 #define XL_NETDIAG_MAC_LOOPBACK 0x2000 363 #define XL_NETDIAG_ENDEC_LOOPBACK 0x4000 364 #define XL_NETDIAG_EXTERNAL_LOOP 0x8000 365 366 /* 367 * Window 5 368 */ 369 #define XL_W5_STAT_ENB 0x0C 370 #define XL_W5_INTR_ENB 0x0A 371 #define XL_W5_RECLAIM_THRESH 0x09 /* 3c905B only */ 372 #define XL_W5_RX_FILTER 0x08 373 #define XL_W5_RX_EARLYTHRESH 0x06 374 #define XL_W5_TX_AVAILTHRESH 0x02 375 #define XL_W5_TX_STARTTHRESH 0x00 376 377 /* 378 * RX filter bits 379 */ 380 #define XL_RXFILTER_INDIVIDUAL 0x01 381 #define XL_RXFILTER_ALLMULTI 0x02 382 #define XL_RXFILTER_BROADCAST 0x04 383 #define XL_RXFILTER_ALLFRAMES 0x08 384 #define XL_RXFILTER_MULTIHASH 0x10 /* 3c905B only */ 385 386 /* 387 * Window 6 (stats) 388 */ 389 #define XL_W6_TX_BYTES_OK 0x0C 390 #define XL_W6_RX_BYTES_OK 0x0A 391 #define XL_W6_UPPER_FRAMES_OK 0x09 392 #define XL_W6_DEFERRED 0x08 393 #define XL_W6_RX_OK 0x07 394 #define XL_W6_TX_OK 0x06 395 #define XL_W6_RX_OVERRUN 0x05 396 #define XL_W6_COL_LATE 0x04 397 #define XL_W6_COL_SINGLE 0x03 398 #define XL_W6_COL_MULTIPLE 0x02 399 #define XL_W6_SQE_ERRORS 0x01 400 #define XL_W6_CARRIER_LOST 0x00 401 402 /* 403 * Window 7 (bus master control) 404 */ 405 #define XL_W7_BM_ADDR 0x00 406 #define XL_W7_BM_LEN 0x06 407 #define XL_W7_BM_STATUS 0x0B 408 #define XL_W7_BM_TIMEr 0x0A 409 410 /* 411 * bus master control registers 412 */ 413 #define XL_BM_PKTSTAT 0x20 414 #define XL_BM_DOWNLISTPTR 0x24 415 #define XL_BM_FRAGADDR 0x28 416 #define XL_BM_FRAGLEN 0x2C 417 #define XL_BM_TXFREETHRESH 0x2F 418 #define XL_BM_UPPKTSTAT 0x30 419 #define XL_BM_UPLISTPTR 0x38 420 421 #define XL_LAST_FRAG 0x80000000 422 423 /* 424 * Boomerang/Cyclone TX/RX list structure. 425 * For the TX lists, bits 0 to 12 of the status word indicate 426 * length. 427 * This looks suspiciously like the ThunderLAN, doesn't it. 428 */ 429 struct xl_frag { 430 u_int32_t xl_addr; /* 63 addr/len pairs */ 431 u_int32_t xl_len; 432 }; 433 434 struct xl_list { 435 u_int32_t xl_next; /* final entry has 0 nextptr */ 436 u_int32_t xl_status; 437 struct xl_frag xl_frag[63]; 438 }; 439 440 struct xl_list_onefrag { 441 u_int32_t xl_next; /* final entry has 0 nextptr */ 442 u_int32_t xl_status; 443 struct xl_frag xl_frag; 444 }; 445 446 #define XL_MAXFRAGS 63 447 #define XL_RX_LIST_CNT 32 448 #define XL_TX_LIST_CNT 32 449 #define XL_MIN_FRAMELEN 60 450 #define XL_INC(x, y) (x) = (x + 1) % (y) 451 452 struct xl_list_data { 453 struct xl_list_onefrag xl_rx_list[XL_RX_LIST_CNT]; 454 struct xl_list xl_tx_list[XL_TX_LIST_CNT]; 455 unsigned char xl_pad[XL_MIN_FRAMELEN]; 456 }; 457 458 struct xl_chain { 459 struct xl_list *xl_ptr; 460 struct mbuf *xl_mbuf; 461 struct xl_chain *xl_next; 462 struct xl_chain *xl_prev; 463 u_int32_t xl_phys; 464 bus_dmamap_t map; 465 }; 466 467 struct xl_chain_onefrag { 468 struct xl_list_onefrag *xl_ptr; 469 struct mbuf *xl_mbuf; 470 struct xl_chain_onefrag *xl_next; 471 bus_dmamap_t map; 472 }; 473 474 struct xl_chain_data { 475 struct xl_chain_onefrag xl_rx_chain[XL_RX_LIST_CNT]; 476 struct xl_chain xl_tx_chain[XL_TX_LIST_CNT]; 477 478 struct xl_chain_onefrag *xl_rx_head; 479 480 /* 3c90x "boomerang" queuing stuff */ 481 struct xl_chain *xl_tx_head; 482 struct xl_chain *xl_tx_tail; 483 struct xl_chain *xl_tx_free; 484 485 /* 3c90xB "cyclone/hurricane/tornado" stuff */ 486 int xl_tx_prod; 487 int xl_tx_cons; 488 int xl_tx_cnt; 489 }; 490 491 #define XL_RXSTAT_LENMASK 0x00001FFF 492 #define XL_RXSTAT_UP_ERROR 0x00004000 493 #define XL_RXSTAT_UP_CMPLT 0x00008000 494 #define XL_RXSTAT_UP_OVERRUN 0x00010000 495 #define XL_RXSTAT_RUNT 0x00020000 496 #define XL_RXSTAT_ALIGN 0x00040000 497 #define XL_RXSTAT_CRC 0x00080000 498 #define XL_RXSTAT_OVERSIZE 0x00100000 499 #define XL_RXSTAT_DRIBBLE 0x00800000 500 #define XL_RXSTAT_UP_OFLOW 0x01000000 501 #define XL_RXSTAT_IPCKERR 0x02000000 /* 3c905B only */ 502 #define XL_RXSTAT_TCPCKERR 0x04000000 /* 3c905B only */ 503 #define XL_RXSTAT_UDPCKERR 0x08000000 /* 3c905B only */ 504 #define XL_RXSTAT_BUFEN 0x10000000 /* 3c905B only */ 505 #define XL_RXSTAT_IPCKOK 0x20000000 /* 3c905B only */ 506 #define XL_RXSTAT_TCPCKOK 0x40000000 /* 3c905B only */ 507 #define XL_RXSTAT_UDPCKOK 0x80000000 /* 3c905B only */ 508 509 #define XL_TXSTAT_LENMASK 0x00001FFF 510 #define XL_TXSTAT_CRCDIS 0x00002000 511 #define XL_TXSTAT_TX_INTR 0x00008000 512 #define XL_TXSTAT_DL_COMPLETE 0x00010000 513 #define XL_TXSTAT_IPCKSUM 0x02000000 /* 3c905B only */ 514 #define XL_TXSTAT_TCPCKSUM 0x04000000 /* 3c905B only */ 515 #define XL_TXSTAT_UDPCKSUM 0x08000000 /* 3c905B only */ 516 #define XL_TXSTAT_RND_DEFEAT 0x10000000 /* 3c905B only */ 517 #define XL_TXSTAT_EMPTY 0x20000000 /* 3c905B only */ 518 #define XL_TXSTAT_DL_INTR 0x80000000 519 520 #define XL_CAPABILITY_BM 0x20 521 522 struct xl_type { 523 u_int16_t xl_vid; 524 u_int16_t xl_did; 525 char *xl_name; 526 }; 527 528 struct xl_mii_frame { 529 u_int8_t mii_stdelim; 530 u_int8_t mii_opcode; 531 u_int8_t mii_phyaddr; 532 u_int8_t mii_regaddr; 533 u_int8_t mii_turnaround; 534 u_int16_t mii_data; 535 }; 536 537 /* 538 * MII constants 539 */ 540 #define XL_MII_STARTDELIM 0x01 541 #define XL_MII_READOP 0x02 542 #define XL_MII_WRITEOP 0x01 543 #define XL_MII_TURNAROUND 0x02 544 545 /* 546 * The 3C905B adapters implement a few features that we want to 547 * take advantage of, namely the multicast hash filter. With older 548 * chips, you only have the option of turning on reception of all 549 * multicast frames, which is kind of lame. 550 * 551 * We also use this to decide on a transmit strategy. For the 3c90xB 552 * cards, we can use polled descriptor mode, which reduces CPU overhead. 553 */ 554 #define XL_TYPE_905B 1 555 #define XL_TYPE_90X 2 556 557 #define XL_FLAG_FUNCREG 0x0001 558 #define XL_FLAG_PHYOK 0x0002 559 #define XL_FLAG_EEPROM_OFFSET_30 0x0004 560 #define XL_FLAG_WEIRDRESET 0x0008 561 #define XL_FLAG_8BITROM 0x0010 562 #define XL_FLAG_INVERT_LED_PWR 0x0020 563 #define XL_FLAG_INVERT_MII_PWR 0x0040 564 565 struct xl_softc { 566 struct device sc_dev; /* generic device structure */ 567 void * xl_intrhand; /* interrupt handler cookie */ 568 struct timeout xl_stsup_tmo; /* stats update timeout */ 569 struct arpcom sc_arpcom; /* interface info */ 570 struct ifmedia ifmedia; /* media info */ 571 mii_data_t sc_mii; /* mii bus */ 572 bus_space_handle_t xl_bhandle; 573 bus_space_tag_t xl_btag; 574 bus_space_handle_t xl_funch; 575 bus_space_tag_t xl_funct; 576 struct xl_type *xl_info; /* 3Com adapter info */ 577 u_int8_t xl_hasmii; /* whether we have mii or not */ 578 u_int8_t xl_type; 579 u_int32_t xl_xcvr; 580 u_int16_t xl_media; 581 u_int16_t xl_caps; 582 u_int8_t xl_stats_no_timeout; 583 u_int16_t xl_tx_thresh; 584 int xl_if_flags; 585 struct xl_list_data *xl_ldata; 586 struct xl_chain_data xl_cdata; 587 int xl_flags; 588 void (*intr_ack)(struct xl_softc *); 589 void * sc_sdhook, *sc_pwrhook; 590 bus_dma_tag_t sc_dmat; 591 bus_dmamap_t sc_listmap; 592 bus_dma_segment_t sc_listseg[1]; 593 int sc_listnseg; 594 caddr_t sc_listkva; 595 bus_dmamap_t sc_rx_sparemap; 596 bus_dmamap_t sc_tx_sparemap; 597 }; 598 599 #define xl_rx_goodframes(x) \ 600 ((x.xl_upper_frames_ok & 0x03) << 8) | x.xl_rx_frames_ok 601 602 #define xl_tx_goodframes(x) \ 603 ((x.xl_upper_frames_ok & 0x30) << 4) | x.xl_tx_frames_ok 604 605 struct xl_stats { 606 u_int8_t xl_carrier_lost; 607 u_int8_t xl_sqe_errs; 608 u_int8_t xl_tx_multi_collision; 609 u_int8_t xl_tx_single_collision; 610 u_int8_t xl_tx_late_collision; 611 u_int8_t xl_rx_overrun; 612 u_int8_t xl_tx_frames_ok; 613 u_int8_t xl_rx_frames_ok; 614 u_int8_t xl_tx_deferred; 615 u_int8_t xl_upper_frames_ok; 616 u_int16_t xl_rx_bytes_ok; 617 u_int16_t xl_tx_bytes_ok; 618 u_int16_t status; 619 }; 620 621 /* 622 * register space access macros 623 */ 624 #define CSR_WRITE_4(sc, reg, val) \ 625 bus_space_write_4(sc->xl_btag, sc->xl_bhandle, reg, val) 626 #define CSR_WRITE_2(sc, reg, val) \ 627 bus_space_write_2(sc->xl_btag, sc->xl_bhandle, reg, val) 628 #define CSR_WRITE_1(sc, reg, val) \ 629 bus_space_write_1(sc->xl_btag, sc->xl_bhandle, reg, val) 630 631 #define CSR_READ_4(sc, reg) \ 632 bus_space_read_4(sc->xl_btag, sc->xl_bhandle, reg) 633 #define CSR_READ_2(sc, reg) \ 634 bus_space_read_2(sc->xl_btag, sc->xl_bhandle, reg) 635 #define CSR_READ_1(sc, reg) \ 636 bus_space_read_1(sc->xl_btag, sc->xl_bhandle, reg) 637 638 #define XL_SEL_WIN(x) \ 639 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x) 640 #define XL_TIMEOUT 2000 641 642 /* 643 * General constants that are fun to know. 644 * 645 * 3Com PCI vendor ID 646 */ 647 #define TC_VENDORID 0x10B7 648 649 /* 650 * 3Com PCI chip device IDs. 651 */ 652 #define TC_DEVICEID_TORNADO_HOMECONNECT 0x4500 653 #define TC_DEVICEID_HURRICANE_555 0x5055 654 #define TC_DEVICEID_HURRICANE_556 0x6055 655 #define TC_DEVICEID_HURRICANE_556B 0x6056 656 #define TC_DEVICEID_BOOMERANG_10BT 0x9000 657 #define TC_DEVICEID_BOOMERANG_10BT_COMBO 0x9001 658 #define TC_DEVICEID_BOOMERANG_10_100BT 0x9050 659 #define TC_DEVICEID_BOOMERANG_100BT4 0x9051 660 #define TC_DEVICEID_KRAKATOA_10BT 0x9004 661 #define TC_DEVICEID_KRAKATOA_10BT_COMBO 0x9005 662 #define TC_DEVICEID_KRAKATOA_10BT_TPC 0x9006 663 #define TC_DEVICEID_CYCLONE_10FL 0x900A 664 #define TC_DEVICEID_HURRICANE_10_100BT 0x9055 665 #define TC_DEVICEID_CYCLONE_10_100BT4 0x9056 666 #define TC_DEVICEID_CYCLONE_10_100_COMBO 0x9058 667 #define TC_DEVICEID_CYCLONE_10_100FX 0x905A 668 #define TC_DEVICEID_TORNADO_10_100BT 0x9200 669 #define TC_DEVICEID_HURRICANE_10_100BT_SERV 0x9800 670 #define TC_DEVICEID_TORNADO_10_100BT_SERV 0x9805 671 #define TC_DEVICEID_HURRICANE_SOHO100TX 0x7646 672 673 /* 674 * 3Com CardBus chip device IDs. 675 * 676 * The third character of the model number indicates either a dongle ('C') 677 * or X-Jack ('X') connector. Presumably, "FE" means "Fast Ethernet", and 678 * the 'M' indicates a NIC/modem combo card. 679 */ 680 #define TC_DEVICEID_3C575_CARDBUS 0x5057 681 #define TC_DEVICEID_3CCFE575BT_CARDBUS 0x5157 /* also 3CXFE575BT */ 682 #define TC_DEVICEID_3CCFE575CT_CARDBUS 0x5257 /* also 3CXFE575CT */ 683 #define TC_DEVICEID_3CCFEM656_CARDBUS 0x6560 /* also 3CXFEM656 */ 684 #define TC_DEVICEID_3CCFEM656B_CARDBUS 0x6562 685 #define TC_DEVICEID_3CCFEM656C_CARDBUS 0x6564 /* also 3CXFEM656C */ 686 687 #define XL_CARDBUS_INTR 0x0004 688 #define XL_CARDBUS_INTR_ACK 0x8000 689 690 /* 691 * PCI low memory base and low I/O base register, and 692 * other PCI registers. Note: some are only available on 693 * the 3c905B, in particular those that related to power management. 694 */ 695 696 #define XL_PCI_VENDOR_ID 0x00 697 #define XL_PCI_DEVICE_ID 0x02 698 #define XL_PCI_COMMAND 0x04 699 #define XL_PCI_STATUS 0x06 700 #define XL_PCI_CLASSCODE 0x09 701 #define XL_PCI_LATENCY_TIMER 0x0D 702 #define XL_PCI_HEADER_TYPE 0x0E 703 #define XL_PCI_LOIO 0x10 704 #define XL_PCI_LOMEM 0x14 705 #define XL_PCI_BIOSROM 0x30 706 #define XL_PCI_INTLINE 0x3C 707 #define XL_PCI_INTPIN 0x3D 708 #define XL_PCI_MINGNT 0x3E 709 #define XL_PCI_MINLAT 0x0F 710 #define XL_PCI_RESETOPT 0x48 711 #define XL_PCI_EEPROM_DATA 0x4C 712 713 /* 3c905B-only registers */ 714 #define XL_PCI_CAPID 0xDC /* 8 bits */ 715 #define XL_PCI_NEXTPTR 0xDD /* 8 bits */ 716 #define XL_PCI_PWRMGMTCAP 0xDE /* 16 bits */ 717 #define XL_PCI_PWRMGMTCTRL 0xE0 /* 16 bits */ 718 719 #define XL_PSTATE_MASK 0x0003 720 #define XL_PSTATE_D0 0x0000 721 #define XL_PSTATE_D1 0x0002 722 #define XL_PSTATE_D2 0x0002 723 #define XL_PSTATE_D3 0x0003 724 #define XL_PME_EN 0x0010 725 #define XL_PME_STATUS 0x8000 726 727 #ifndef ETHER_ALIGN 728 #define ETHER_ALIGN 2 729 #endif 730 731 extern int xl_intr(void *); 732 extern void xl_attach(struct xl_softc *); 733 extern int xl_detach(struct xl_softc *); 734