1 /* $OpenBSD: wdc.c,v 1.86 2004/10/17 17:50:48 grange Exp $ */
2 /* $NetBSD: wdc.c,v 1.68 1999/06/23 19:00:17 bouyer Exp $ */
3
4
5 /*
6 * Copyright (c) 1998, 2001 Manuel Bouyer. All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Manuel Bouyer.
19 * 4. The name of the author may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 /*-
35 * Copyright (c) 1998 The NetBSD Foundation, Inc.
36 * All rights reserved.
37 *
38 * This code is derived from software contributed to The NetBSD Foundation
39 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed by the NetBSD
52 * Foundation, Inc. and its contributors.
53 * 4. Neither the name of The NetBSD Foundation nor the names of its
54 * contributors may be used to endorse or promote products derived
55 * from this software without specific prior written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67 * POSSIBILITY OF SUCH DAMAGE.
68 */
69
70 #include <sys/param.h>
71 #include <sys/systm.h>
72 #include <sys/kernel.h>
73 #include <sys/conf.h>
74 #include <sys/buf.h>
75 #include <sys/device.h>
76 #include <sys/malloc.h>
77 #include <sys/syslog.h>
78 #include <sys/proc.h>
79 #include <sys/pool.h>
80 #include <uvm/uvm_extern.h>
81
82 #include <machine/intr.h>
83 #include <machine/bus.h>
84
85 #include <dev/ata/atavar.h>
86 #include <dev/ata/atareg.h>
87 #include <dev/ic/wdcreg.h>
88 #include <dev/ic/wdcvar.h>
89 #include <dev/ic/wdcevent.h>
90
91 #include "atapiscsi.h"
92
93 #define WDCDELAY 100 /* 100 microseconds */
94 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY)
95 #if 0
96 /* If you enable this, it will report any delays more than WDCDELAY * N long. */
97 #define WDCNDELAY_DEBUG 50
98 #endif /* 0 */
99
100 struct pool wdc_xfer_pool;
101
102 void __wdcerror(struct channel_softc *, char *);
103 void __wdcdo_reset(struct channel_softc *);
104 int __wdcwait_reset(struct channel_softc *, int);
105 void __wdccommand_done(struct channel_softc *, struct wdc_xfer *);
106 void __wdccommand_start(struct channel_softc *, struct wdc_xfer *);
107 int __wdccommand_intr(struct channel_softc *, struct wdc_xfer *, int);
108 int wdprint(void *, const char *);
109 void wdc_kill_pending(struct channel_softc *);
110
111 #define DEBUG_INTR 0x01
112 #define DEBUG_XFERS 0x02
113 #define DEBUG_STATUS 0x04
114 #define DEBUG_FUNCS 0x08
115 #define DEBUG_PROBE 0x10
116 #define DEBUG_STATUSX 0x20
117 #define DEBUG_SDRIVE 0x40
118 #define DEBUG_DETACH 0x80
119
120 #ifdef WDCDEBUG
121 #ifndef WDCDEBUG_MASK
122 #define WDCDEBUG_MASK 0x00
123 #endif
124 int wdcdebug_mask = WDCDEBUG_MASK;
125 int wdc_nxfer = 0;
126 #define WDCDEBUG_PRINT(args, level) do { \
127 if ((wdcdebug_mask & (level)) != 0) \
128 printf args; \
129 } while (0)
130 #else
131 #define WDCDEBUG_PRINT(args, level)
132 #endif /* WDCDEBUG */
133
134 int at_poll = AT_POLL;
135
136 int wdc_floating_bus(struct channel_softc *, int);
137 int wdc_preata_drive(struct channel_softc *, int);
138 int wdc_ata_present(struct channel_softc *, int);
139
140 struct channel_softc_vtbl wdc_default_vtbl = {
141 wdc_default_read_reg,
142 wdc_default_write_reg,
143 wdc_default_read_raw_multi_2,
144 wdc_default_write_raw_multi_2,
145 wdc_default_read_raw_multi_4,
146 wdc_default_write_raw_multi_4
147 };
148
149 static char *wdc_log_buf = NULL;
150 static unsigned int wdc_tail = 0;
151 static unsigned int wdc_head = 0;
152 static unsigned int wdc_log_cap = 16 * 1024;
153 static int chp_idx = 1;
154
155 void
wdc_log(struct channel_softc * chp,enum wdcevent_type type,unsigned int size,char val[])156 wdc_log(struct channel_softc *chp, enum wdcevent_type type,
157 unsigned int size, char val[])
158 {
159 unsigned int request_size;
160 char *ptr;
161 int log_size;
162 unsigned int head = wdc_head;
163 unsigned int tail = wdc_tail;
164
165 #ifdef DIAGNOSTIC
166 if (head < 0 || head > wdc_log_cap ||
167 tail < 0 || tail > wdc_log_cap) {
168 printf ("wdc_log: head %x wdc_tail %x\n", head,
169 tail);
170 return;
171 }
172
173 if (size > wdc_log_cap / 2) {
174 printf ("wdc_log: type %d size %x\n", type, size);
175 return;
176 }
177 #endif
178
179 if (wdc_log_buf == NULL) {
180 wdc_log_buf = malloc(wdc_log_cap, M_DEVBUF, M_NOWAIT);
181 if (wdc_log_buf == NULL)
182 return;
183 }
184 if (chp->ch_log_idx == 0)
185 chp->ch_log_idx = chp_idx++;
186
187 request_size = size + 2;
188
189 /* Check how many bytes are left */
190 log_size = head - tail;
191 if (log_size < 0) log_size += wdc_log_cap;
192
193 if (log_size + request_size >= wdc_log_cap) {
194 int nb = 0;
195 int rec_size;
196
197 while (nb <= (request_size * 2)) {
198 if (wdc_log_buf[tail] == 0)
199 rec_size = 1;
200 else
201 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2;
202 tail = (tail + rec_size) % wdc_log_cap;
203 nb += rec_size;
204 }
205 }
206
207 /* Avoid wrapping in the middle of a request */
208 if (head + request_size >= wdc_log_cap) {
209 memset(&wdc_log_buf[head], 0, wdc_log_cap - head);
210 head = 0;
211 }
212
213 ptr = &wdc_log_buf[head];
214 *ptr++ = type & 0xff;
215 *ptr++ = ((chp->ch_log_idx & 0x7) << 5) | (size & 0x1f);
216 memcpy(ptr, val, size);
217
218 wdc_head = (head + request_size) % wdc_log_cap;
219 wdc_tail = tail;
220 }
221
222 char *wdc_get_log(unsigned int *, unsigned int *);
223
224 char *
wdc_get_log(unsigned int * size,unsigned int * left)225 wdc_get_log(unsigned int * size, unsigned int *left)
226 {
227 int log_size;
228 char *retbuf = NULL;
229 int nb, tocopy;
230 int s;
231 unsigned int head = wdc_head;
232 unsigned int tail = wdc_tail;
233
234 s = splbio();
235
236 log_size = (head - tail);
237 if (left != NULL)
238 *left = 0;
239
240 if (log_size < 0)
241 log_size += wdc_log_cap;
242
243 tocopy = log_size;
244 if ((u_int)tocopy > *size)
245 tocopy = *size;
246
247 if (wdc_log_buf == NULL) {
248 *size = 0;
249 *left = 0;
250 goto out;
251 }
252
253 #ifdef DIAGNOSTIC
254 if (head < 0 || head > wdc_log_cap ||
255 tail < 0 || tail > wdc_log_cap) {
256 printf ("wdc_log: head %x tail %x\n", head,
257 tail);
258 *size = 0;
259 *left = 0;
260 goto out;
261 }
262 #endif
263
264 retbuf = malloc(tocopy, M_TEMP, M_NOWAIT);
265 if (retbuf == NULL) {
266 *size = 0;
267 *left = log_size;
268 goto out;
269 }
270
271 nb = 0;
272 for (;;) {
273 int rec_size;
274
275 if (wdc_log_buf[tail] == 0)
276 rec_size = 1;
277 else
278 rec_size = (wdc_log_buf[tail + 1] & 0x1f) + 2;
279
280 if ((nb + rec_size) >= tocopy)
281 break;
282
283 memcpy(&retbuf[nb], &wdc_log_buf[tail], rec_size);
284 tail = (tail + rec_size) % wdc_log_cap;
285 nb += rec_size;
286 }
287
288 wdc_tail = tail;
289 *size = nb;
290 *left = log_size - nb;
291
292 out:
293 splx(s);
294 return (retbuf);
295 }
296
297
298 u_int8_t
wdc_default_read_reg(chp,reg)299 wdc_default_read_reg(chp, reg)
300 struct channel_softc *chp;
301 enum wdc_regs reg;
302 {
303 #ifdef DIAGNOSTIC
304 if (reg & _WDC_WRONLY) {
305 printf ("wdc_default_read_reg: reading from a write-only register %d\n", reg);
306 }
307 #endif /* DIAGNOSTIC */
308
309 if (reg & _WDC_AUX)
310 return (bus_space_read_1(chp->ctl_iot, chp->ctl_ioh,
311 reg & _WDC_REGMASK));
312 else
313 return (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
314 reg & _WDC_REGMASK));
315 }
316
317 void
wdc_default_write_reg(chp,reg,val)318 wdc_default_write_reg(chp, reg, val)
319 struct channel_softc *chp;
320 enum wdc_regs reg;
321 u_int8_t val;
322 {
323 #ifdef DIAGNOSTIC
324 if (reg & _WDC_RDONLY) {
325 printf ("wdc_default_write_reg: writing to a read-only register %d\n", reg);
326 }
327 #endif /* DIAGNOSTIC */
328
329 if (reg & _WDC_AUX)
330 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh,
331 reg & _WDC_REGMASK, val);
332 else
333 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh,
334 reg & _WDC_REGMASK, val);
335 }
336
337
338 void
wdc_default_read_raw_multi_2(chp,data,nbytes)339 wdc_default_read_raw_multi_2(chp, data, nbytes)
340 struct channel_softc *chp;
341 void *data;
342 unsigned int nbytes;
343 {
344 if (data == NULL) {
345 unsigned int i;
346
347 for (i = 0; i < nbytes; i += 2) {
348 bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, 0);
349 }
350
351 return;
352 }
353
354 bus_space_read_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0,
355 data, nbytes);
356 return;
357 }
358
359
360 void
wdc_default_write_raw_multi_2(chp,data,nbytes)361 wdc_default_write_raw_multi_2(chp, data, nbytes)
362 struct channel_softc *chp;
363 void *data;
364 unsigned int nbytes;
365 {
366 if (data == NULL) {
367 unsigned int i;
368
369 for (i = 0; i < nbytes; i += 2) {
370 bus_space_write_2(chp->cmd_iot, chp->cmd_ioh, 0, 0);
371 }
372
373 return;
374 }
375
376 bus_space_write_raw_multi_2(chp->cmd_iot, chp->cmd_ioh, 0,
377 data, nbytes);
378 return;
379 }
380
381
382 void
wdc_default_write_raw_multi_4(chp,data,nbytes)383 wdc_default_write_raw_multi_4(chp, data, nbytes)
384 struct channel_softc *chp;
385 void *data;
386 unsigned int nbytes;
387 {
388 if (data == NULL) {
389 unsigned int i;
390
391 for (i = 0; i < nbytes; i += 4) {
392 bus_space_write_4(chp->cmd_iot, chp->cmd_ioh, 0, 0);
393 }
394
395 return;
396 }
397
398 bus_space_write_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0,
399 data, nbytes);
400 return;
401 }
402
403
404 void
wdc_default_read_raw_multi_4(chp,data,nbytes)405 wdc_default_read_raw_multi_4(chp, data, nbytes)
406 struct channel_softc *chp;
407 void *data;
408 unsigned int nbytes;
409 {
410 if (data == NULL) {
411 unsigned int i;
412
413 for (i = 0; i < nbytes; i += 4) {
414 bus_space_read_4(chp->cmd_iot, chp->cmd_ioh, 0);
415 }
416
417 return;
418 }
419
420 bus_space_read_raw_multi_4(chp->cmd_iot, chp->cmd_ioh, 0,
421 data, nbytes);
422 return;
423 }
424
425
426 int
wdprint(aux,pnp)427 wdprint(aux, pnp)
428 void *aux;
429 const char *pnp;
430 {
431 struct ata_atapi_attach *aa_link = aux;
432 if (pnp)
433 printf("drive at %s", pnp);
434 printf(" channel %d drive %d", aa_link->aa_channel,
435 aa_link->aa_drv_data->drive);
436 return (UNCONF);
437 }
438
439 int
atapi_print(aux,pnp)440 atapi_print(aux, pnp)
441 void *aux;
442 const char *pnp;
443 {
444 struct ata_atapi_attach *aa_link = aux;
445 if (pnp)
446 printf("atapiscsi at %s", pnp);
447 printf(" channel %d", aa_link->aa_channel);
448 return (UNCONF);
449 }
450
451 void
wdc_disable_intr(chp)452 wdc_disable_intr(chp)
453 struct channel_softc *chp;
454 {
455 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_IDS);
456 }
457
458 void
wdc_enable_intr(chp)459 wdc_enable_intr(chp)
460 struct channel_softc *chp;
461 {
462 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT);
463 }
464
465 void
wdc_set_drive(struct channel_softc * chp,int drive)466 wdc_set_drive(struct channel_softc *chp, int drive)
467 {
468 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_IBM);
469 WDC_LOG_SET_DRIVE(chp, drive);
470 }
471
472 int
wdc_floating_bus(chp,drive)473 wdc_floating_bus(chp, drive)
474 struct channel_softc *chp;
475 int drive;
476
477 {
478 u_int8_t cumulative_status, status;
479 int iter;
480
481 wdc_set_drive(chp, drive);
482 delay(10);
483
484 /* Stolen from Phoenix BIOS Drive Autotyping document */
485 cumulative_status = 0;
486 for (iter = 0; iter < 100; iter++) {
487 CHP_WRITE_REG(chp, wdr_seccnt, 0x7f);
488 delay (1);
489
490 status = CHP_READ_REG(chp, wdr_status);
491
492 /* The other bits are meaningless if BSY is set */
493 if (status & WDCS_BSY)
494 continue;
495
496 cumulative_status |= status;
497
498 #define BAD_BIT_COMBO (WDCS_DRDY | WDCS_DSC | WDCS_DRQ | WDCS_ERR)
499 if ((cumulative_status & BAD_BIT_COMBO) == BAD_BIT_COMBO)
500 return 1;
501 }
502
503
504 return 0;
505 }
506
507
508 int
wdc_preata_drive(chp,drive)509 wdc_preata_drive(chp, drive)
510 struct channel_softc *chp;
511 int drive;
512
513 {
514 if (wdc_floating_bus(chp, drive)) {
515 WDCDEBUG_PRINT(("%s:%d:%d: floating bus detected\n",
516 chp->wdc->sc_dev.dv_xname,
517 chp->channel, drive), DEBUG_PROBE);
518 return 0;
519 }
520
521 wdc_set_drive(chp, drive);
522 delay(100);
523 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) {
524 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n",
525 chp->wdc->sc_dev.dv_xname,
526 chp->channel, drive), DEBUG_PROBE);
527 return 0;
528 }
529
530 CHP_WRITE_REG(chp, wdr_command, WDCC_RECAL);
531 WDC_LOG_ATA_CMDSHORT(chp, WDCC_RECAL);
532 if (wdcwait(chp, WDCS_DRDY | WDCS_DRQ, WDCS_DRDY, 10000) != 0) {
533 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n",
534 chp->wdc->sc_dev.dv_xname,
535 chp->channel, drive), DEBUG_PROBE);
536 return 0;
537 }
538
539 return 1;
540 }
541
542 int
wdc_ata_present(chp,drive)543 wdc_ata_present(chp, drive)
544 struct channel_softc *chp;
545 int drive;
546 {
547 int time_to_done;
548 int retry_cnt = 0;
549
550 wdc_set_drive(chp, drive);
551 delay(10);
552
553 retry:
554 /*
555 You're actually supposed to wait up to 10 seconds
556 for DRDY. However, as a practical matter, most
557 drives assert DRDY very quickly after dropping BSY.
558
559 The 10 seconds wait is sub-optimal because, according
560 to the ATA standard, the master should reply with 00
561 for any reads to a non-existent slave.
562 */
563 time_to_done = wdc_wait_for_status(chp,
564 (WDCS_DRDY | WDCS_DSC | WDCS_DRQ),
565 (WDCS_DRDY | WDCS_DSC), 1000);
566 if (time_to_done == -1) {
567 if (retry_cnt == 0 && chp->ch_status == 0x00) {
568 /* At least one flash card needs to be kicked */
569 wdccommandshort(chp, drive, WDCC_CHECK_PWR);
570 retry_cnt++;
571 goto retry;
572 }
573 WDCDEBUG_PRINT(("%s:%d:%d: DRDY test timed out with status"
574 " %02x\n",
575 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
576 chp->channel, drive, chp->ch_status),
577 DEBUG_PROBE);
578 return 0;
579 }
580
581 if ((chp->ch_status & 0xfc) != (WDCS_DRDY | WDCS_DSC)) {
582 WDCDEBUG_PRINT(("%s:%d:%d: status test for 0x50 failed with"
583 " %02x\n",
584 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
585 chp->channel, drive, chp->ch_status),
586 DEBUG_PROBE);
587
588 return 0;
589 }
590
591 WDCDEBUG_PRINT(("%s:%d:%d: waiting for ready %d msec\n",
592 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
593 chp->channel, drive, time_to_done), DEBUG_PROBE);
594
595 /*
596 * Test register writability
597 */
598 CHP_WRITE_REG(chp, wdr_cyl_lo, 0xaa);
599 CHP_WRITE_REG(chp, wdr_cyl_hi, 0x55);
600 CHP_WRITE_REG(chp, wdr_seccnt, 0xff);
601 DELAY(10);
602
603 if (CHP_READ_REG(chp, wdr_cyl_lo) != 0xaa &&
604 CHP_READ_REG(chp, wdr_cyl_hi) != 0x55) {
605 WDCDEBUG_PRINT(("%s:%d:%d: register writability failed\n",
606 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
607 chp->channel, drive), DEBUG_PROBE);
608 return 0;
609 }
610
611 return 1;
612 }
613
614
615 /*
616 * Test to see controller with at least one attached drive is there.
617 * Returns a bit for each possible drive found (0x01 for drive 0,
618 * 0x02 for drive 1).
619 * Logic:
620 * - If a status register is at 0x7f or 0xff, assume there is no drive here
621 * (ISA has pull-up resistors). Similarly if the status register has
622 * the value we last wrote to the bus (for IDE interfaces without pullups).
623 * If no drive at all -> return.
624 * - reset the controller, wait for it to complete (may take up to 31s !).
625 * If timeout -> return.
626 * - test ATA/ATAPI signatures. If at last one drive found -> return.
627 * - try an ATA command on the master.
628 */
629
630 int
wdcprobe(chp)631 wdcprobe(chp)
632 struct channel_softc *chp;
633 {
634 u_int8_t st0, st1, sc, sn, cl, ch;
635 u_int8_t ret_value = 0x03;
636 u_int8_t drive;
637 #ifdef WDCDEBUG
638 int savedmask = wdcdebug_mask;
639 #endif
640
641 if (chp->_vtbl == 0) {
642 int s = splbio();
643 chp->_vtbl = &wdc_default_vtbl;
644 splx(s);
645 }
646
647 #ifdef WDCDEBUG
648 if ((chp->ch_flags & WDCF_VERBOSE_PROBE) ||
649 (chp->wdc &&
650 (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE)))
651 wdcdebug_mask |= DEBUG_PROBE;
652 #endif /* WDCDEBUG */
653
654 if (chp->wdc == NULL ||
655 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) {
656 /* Sample the statuses of drive 0 and 1 into st0 and st1 */
657 wdc_set_drive(chp, 0);
658 delay(10);
659 st0 = CHP_READ_REG(chp, wdr_status);
660 WDC_LOG_STATUS(chp, st0);
661 wdc_set_drive(chp, 1);
662 delay(10);
663 st1 = CHP_READ_REG(chp, wdr_status);
664 WDC_LOG_STATUS(chp, st1);
665
666 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%b, st1=0x%b\n",
667 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
668 chp->channel, st0, WDCS_BITS, st1, WDCS_BITS),
669 DEBUG_PROBE);
670
671 if ((st0 & 0x7f) == 0x7f || st0 == WDSD_IBM)
672 ret_value &= ~0x01;
673 if ((st1 & 0x7f) == 0x7f || st1 == (WDSD_IBM | 0x10))
674 ret_value &= ~0x02;
675 if (ret_value == 0)
676 return 0;
677 }
678
679 /* reset the channel */
680 __wdcdo_reset(chp);
681
682 ret_value = __wdcwait_reset(chp, ret_value);
683 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n",
684 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
685 ret_value), DEBUG_PROBE);
686
687 if (ret_value == 0)
688 return 0;
689
690 /*
691 * Use signatures to find potential ATAPI drives
692 */
693 for (drive = 0; drive < 2; drive++) {
694 if ((ret_value & (0x01 << drive)) == 0)
695 continue;
696 wdc_set_drive(chp, drive);
697 delay(10);
698 /* Save registers contents */
699 st0 = CHP_READ_REG(chp, wdr_status);
700 sc = CHP_READ_REG(chp, wdr_seccnt);
701 sn = CHP_READ_REG(chp, wdr_sector);
702 cl = CHP_READ_REG(chp, wdr_cyl_lo);
703 ch = CHP_READ_REG(chp, wdr_cyl_hi);
704 WDC_LOG_REG(chp, wdr_cyl_lo, (ch << 8) | cl);
705
706 WDCDEBUG_PRINT(("%s:%d:%d: after reset, st=0x%b, sc=0x%x"
707 " sn=0x%x cl=0x%x ch=0x%x\n",
708 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe",
709 chp->channel, drive, st0, WDCS_BITS, sc, sn, cl, ch),
710 DEBUG_PROBE);
711 /*
712 * This is a simplification of the test in the ATAPI
713 * spec since not all drives seem to set the other regs
714 * correctly.
715 */
716 if (cl == 0x14 && ch == 0xeb)
717 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI;
718 }
719
720 /*
721 * Detect ATA drives by poking around the registers
722 */
723 for (drive = 0; drive < 2; drive++) {
724 if ((ret_value & (0x01 << drive)) == 0)
725 continue;
726 if (chp->ch_drive[drive].drive_flags & DRIVE_ATAPI)
727 continue;
728
729 wdc_disable_intr(chp);
730 /* ATA detect */
731 if (wdc_ata_present(chp, drive)) {
732 chp->ch_drive[drive].drive_flags |= DRIVE_ATA;
733 if (chp->wdc == NULL ||
734 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0)
735 chp->ch_drive[drive].drive_flags |= DRIVE_OLD;
736 } else {
737 ret_value &= ~(1 << drive);
738 }
739 wdc_enable_intr(chp);
740 }
741
742 #ifdef WDCDEBUG
743 wdcdebug_mask = savedmask;
744 #endif
745 return (ret_value);
746 }
747
748 /*
749 * Call activate routine of underlying devices.
750 */
751 int
wdcactivate(self,act)752 wdcactivate(self, act)
753 struct device *self;
754 enum devact act;
755 {
756 int error = 0;
757 int s;
758
759 s = splbio();
760 config_activate_children(self, act);
761 splx(s);
762
763 return (error);
764 }
765
766 void
wdcattach(chp)767 wdcattach(chp)
768 struct channel_softc *chp;
769 {
770 int channel_flags, ctrl_flags, i;
771 #ifndef __OpenBSD__
772 int error;
773 #endif
774 struct ata_atapi_attach aa_link;
775 static int inited = 0;
776 #ifdef WDCDEBUG
777 int savedmask = wdcdebug_mask;
778 #endif
779
780 if (!cold)
781 at_poll = AT_WAIT;
782
783 timeout_set(&chp->ch_timo, wdctimeout, chp);
784
785 #ifndef __OpenBSD__
786 if ((error = wdc_addref(chp)) != 0) {
787 printf("%s: unable to enable controller\n",
788 chp->wdc->sc_dev.dv_xname);
789 return;
790 }
791 #endif /* __OpenBSD__ */
792 if (!chp->_vtbl)
793 chp->_vtbl = &wdc_default_vtbl;
794
795 if (chp->wdc->drv_probe != NULL) {
796 chp->wdc->drv_probe(chp);
797 } else {
798 if (wdcprobe(chp) == 0) {
799 /* If no drives, abort attach here. */
800 #ifndef __OpenBSD__
801 wdc_delref(chp);
802 #endif
803 return;
804 }
805 }
806
807 /* ATAPI drives need settling time. Give them 250ms */
808 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
809 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
810 delay(250 * 1000);
811 }
812
813 #ifdef WDCDEBUG
814 if (chp->wdc->sc_dev.dv_cfdata->cf_flags & WDC_OPTION_PROBE_VERBOSE)
815 wdcdebug_mask |= DEBUG_PROBE;
816
817 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) ||
818 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) {
819 wdcdebug_mask = DEBUG_PROBE;
820 }
821 #endif /* WDCDEBUG */
822
823 /* initialise global data */
824 if (inited == 0) {
825 /* Initialize the wdc_xfer pool. */
826 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0,
827 0, 0, "wdcspl", NULL);
828 inited++;
829 }
830 TAILQ_INIT(&chp->ch_queue->sc_xfer);
831
832 for (i = 0; i < 2; i++) {
833 struct ata_drive_datas *drvp = &chp->ch_drive[i];
834
835 drvp->chnl_softc = chp;
836 drvp->drive = i;
837 /* If controller can't do 16bit flag the drives as 32bit */
838 if ((chp->wdc->cap &
839 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
840 WDC_CAPABILITY_DATA32)
841 drvp->drive_flags |= DRIVE_CAP32;
842
843 if ((drvp->drive_flags & DRIVE) == 0)
844 continue;
845
846 if (i == 1 && ((chp->ch_drive[0].drive_flags & DRIVE) == 0))
847 chp->ch_flags |= WDCF_ONESLAVE;
848 /*
849 * Wait a bit, some devices are weird just after a reset.
850 * Then issue a IDENTIFY command, to try to detect slave ghost.
851 */
852 delay(5000);
853 if (ata_get_params(&chp->ch_drive[i], at_poll, &drvp->id) ==
854 CMD_OK) {
855 /* If IDENTIFY succeeded, this is not an OLD ctrl */
856 drvp->drive_flags &= ~DRIVE_OLD;
857 } else {
858 drvp->drive_flags &=
859 ~(DRIVE_ATA | DRIVE_ATAPI);
860 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed\n",
861 chp->wdc->sc_dev.dv_xname,
862 chp->channel, i), DEBUG_PROBE);
863
864 if ((drvp->drive_flags & DRIVE_OLD) &&
865 !wdc_preata_drive(chp, i))
866 drvp->drive_flags &= ~DRIVE_OLD;
867 }
868 }
869 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags;
870 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff;
871
872 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n",
873 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags),
874 DEBUG_PROBE);
875
876 /* If no drives, abort here */
877 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 &&
878 (chp->ch_drive[1].drive_flags & DRIVE) == 0)
879 goto exit;
880
881 for (i = 0; i < 2; i++) {
882 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) {
883 continue;
884 }
885 bzero(&aa_link, sizeof(struct ata_atapi_attach));
886 if (chp->ch_drive[i].drive_flags & DRIVE_ATAPI)
887 aa_link.aa_type = T_ATAPI;
888 else
889 aa_link.aa_type = T_ATA;
890 aa_link.aa_channel = chp->channel;
891 aa_link.aa_openings = 1;
892 aa_link.aa_drv_data = &chp->ch_drive[i];
893 config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint);
894 }
895
896 /*
897 * reset drive_flags for unattached devices, reset state for attached
898 * ones
899 */
900 for (i = 0; i < 2; i++) {
901 if (chp->ch_drive[i].drive_name[0] == 0)
902 chp->ch_drive[i].drive_flags = 0;
903 }
904
905 #ifndef __OpenBSD__
906 wdc_delref(chp);
907 #endif
908
909 exit:
910 #ifdef WDCDEBUG
911 wdcdebug_mask = savedmask;
912 #endif
913 return;
914 }
915
916 /*
917 * Start I/O on a controller, for the given channel.
918 * The first xfer may be not for our channel if the channel queues
919 * are shared.
920 */
921 void
wdcstart(chp)922 wdcstart(chp)
923 struct channel_softc *chp;
924 {
925 struct wdc_xfer *xfer;
926
927 splassert(IPL_BIO);
928
929 /* is there a xfer ? */
930 if ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) == NULL) {
931 return;
932 }
933
934 /* adjust chp, in case we have a shared queue */
935 chp = xfer->chp;
936
937 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) {
938 return; /* channel already active */
939 }
940 #ifdef DIAGNOSTIC
941 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0)
942 panic("wdcstart: channel waiting for irq");
943 #endif /* DIAGNOSTIC */
944 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK)
945 if (!(chp->wdc->claim_hw)(chp, 0))
946 return;
947
948 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer,
949 chp->channel, xfer->drive), DEBUG_XFERS);
950 chp->ch_flags |= WDCF_ACTIVE;
951 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) {
952 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET;
953 chp->ch_drive[xfer->drive].state = 0;
954 }
955 xfer->c_start(chp, xfer);
956 }
957
958 int
wdcdetach(chp,flags)959 wdcdetach(chp, flags)
960 struct channel_softc *chp;
961 int flags;
962 {
963 int s, rv;
964
965 s = splbio();
966 wdc_kill_pending(chp);
967
968 rv = config_detach_children((struct device *)chp->wdc, flags);
969 splx(s);
970
971 return (rv);
972 }
973
974 /* restart an interrupted I/O */
975 void
wdcrestart(v)976 wdcrestart(v)
977 void *v;
978 {
979 struct channel_softc *chp = v;
980 int s;
981
982 s = splbio();
983 wdcstart(chp);
984 splx(s);
985 }
986
987
988 /*
989 * Interrupt routine for the controller. Acknowledge the interrupt, check for
990 * errors on the current operation, mark it done if necessary, and start the
991 * next request. Also check for a partially done transfer, and continue with
992 * the next chunk if so.
993 */
994 int
wdcintr(arg)995 wdcintr(arg)
996 void *arg;
997 {
998 struct channel_softc *chp = arg;
999 struct wdc_xfer *xfer;
1000 int ret;
1001
1002 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) {
1003 /* Acknowledge interrupt by reading status */
1004 if (chp->_vtbl == 0) {
1005 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh,
1006 wdr_status & _WDC_REGMASK);
1007 } else {
1008 CHP_READ_REG(chp, wdr_status);
1009 }
1010
1011 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR);
1012 return 0;
1013 }
1014
1015 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR);
1016 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer);
1017 if (chp->ch_flags & WDCF_DMA_WAIT) {
1018 chp->wdc->dma_status =
1019 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel,
1020 xfer->drive, 0);
1021 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) {
1022 /* IRQ not for us, not detected by DMA engine */
1023 return 0;
1024 }
1025 chp->ch_flags &= ~WDCF_DMA_WAIT;
1026 }
1027 chp->ch_flags &= ~WDCF_IRQ_WAIT;
1028 ret = xfer->c_intr(chp, xfer, 1);
1029 if (ret == 0) /* irq was not for us, still waiting for irq */
1030 chp->ch_flags |= WDCF_IRQ_WAIT;
1031 return (ret);
1032 }
1033
1034 /* Put all disk in RESET state */
wdc_reset_channel(drvp)1035 void wdc_reset_channel(drvp)
1036 struct ata_drive_datas *drvp;
1037 {
1038 struct channel_softc *chp = drvp->chnl_softc;
1039 int drive;
1040 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n",
1041 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
1042 DEBUG_FUNCS);
1043 (void) wdcreset(chp, VERBOSE);
1044 for (drive = 0; drive < 2; drive++) {
1045 chp->ch_drive[drive].state = 0;
1046 }
1047 }
1048
1049 int
wdcreset(chp,verb)1050 wdcreset(chp, verb)
1051 struct channel_softc *chp;
1052 int verb;
1053 {
1054 int drv_mask1, drv_mask2;
1055
1056 if (!chp->_vtbl)
1057 chp->_vtbl = &wdc_default_vtbl;
1058
1059 __wdcdo_reset(chp);
1060
1061 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00;
1062 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00;
1063 drv_mask2 = __wdcwait_reset(chp, drv_mask1);
1064 if (verb && drv_mask2 != drv_mask1) {
1065 printf("%s channel %d: reset failed for",
1066 chp->wdc->sc_dev.dv_xname, chp->channel);
1067 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0)
1068 printf(" drive 0");
1069 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0)
1070 printf(" drive 1");
1071 printf("\n");
1072 }
1073
1074 return (drv_mask1 != drv_mask2) ? 1 : 0;
1075 }
1076
1077 void
__wdcdo_reset(struct channel_softc * chp)1078 __wdcdo_reset(struct channel_softc *chp)
1079 {
1080 wdc_set_drive(chp, 0);
1081 DELAY(10);
1082 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT | WDCTL_RST);
1083 delay(10000);
1084 CHP_WRITE_REG(chp, wdr_ctlr, WDCTL_4BIT);
1085 delay(10000);
1086 }
1087
1088 int
__wdcwait_reset(chp,drv_mask)1089 __wdcwait_reset(chp, drv_mask)
1090 struct channel_softc *chp;
1091 int drv_mask;
1092 {
1093 int timeout;
1094 u_int8_t st0, er0, st1, er1;
1095
1096 /* wait for BSY to deassert */
1097 for (timeout = 0; timeout < WDCNDELAY_RST; timeout++) {
1098 wdc_set_drive(chp, 0);
1099 delay(10);
1100 st0 = CHP_READ_REG(chp, wdr_status);
1101 er0 = CHP_READ_REG(chp, wdr_error);
1102 wdc_set_drive(chp, 1);
1103 delay(10);
1104 st1 = CHP_READ_REG(chp, wdr_status);
1105 er1 = CHP_READ_REG(chp, wdr_error);
1106
1107 if ((drv_mask & 0x01) == 0) {
1108 /* no master */
1109 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) {
1110 /* No master, slave is ready, it's done */
1111 goto end;
1112 }
1113 } else if ((drv_mask & 0x02) == 0) {
1114 /* no slave */
1115 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) {
1116 /* No slave, master is ready, it's done */
1117 goto end;
1118 }
1119 } else {
1120 /* Wait for both master and slave to be ready */
1121 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) {
1122 goto end;
1123 }
1124 }
1125 delay(WDCDELAY);
1126 }
1127 /* Reset timed out. Maybe it's because drv_mask was not right */
1128 if (st0 & WDCS_BSY)
1129 drv_mask &= ~0x01;
1130 if (st1 & WDCS_BSY)
1131 drv_mask &= ~0x02;
1132 end:
1133 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%b, er0=0x%x, "
1134 "st1=0x%b, er1=0x%x, reset time=%d msec\n",
1135 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel,
1136 st0, WDCS_BITS, er0, st1, WDCS_BITS, er1,
1137 timeout * WDCDELAY / 1000), DEBUG_PROBE);
1138
1139 return drv_mask;
1140 }
1141
1142 /*
1143 * Wait for a drive to be !BSY, and have mask in its status register.
1144 * return -1 for a timeout after "timeout" ms.
1145 */
1146 int
wdc_wait_for_status(chp,mask,bits,timeout)1147 wdc_wait_for_status(chp, mask, bits, timeout)
1148 struct channel_softc *chp;
1149 int mask, bits, timeout;
1150 {
1151 u_char status;
1152 int time = 0;
1153
1154 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname
1155 :"none", chp->channel), DEBUG_STATUS);
1156 chp->ch_error = 0;
1157
1158 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */
1159
1160 for (;;) {
1161 chp->ch_status = status = CHP_READ_REG(chp, wdr_status);
1162 WDC_LOG_STATUS(chp, chp->ch_status);
1163
1164 if (status == 0xff && (chp->ch_flags & WDCF_ONESLAVE)) {
1165 wdc_set_drive(chp, 1);
1166 chp->ch_status = status =
1167 CHP_READ_REG(chp, wdr_status);
1168 WDC_LOG_STATUS(chp, chp->ch_status);
1169 }
1170 if ((status & WDCS_BSY) == 0 && (status & mask) == bits)
1171 break;
1172 if (++time > timeout) {
1173 WDCDEBUG_PRINT(("wdcwait: timeout, status 0x%b "
1174 "error 0x%x\n", status, WDCS_BITS,
1175 CHP_READ_REG(chp, wdr_error)),
1176 DEBUG_STATUSX | DEBUG_STATUS);
1177 return -1;
1178 }
1179 delay(WDCDELAY);
1180 }
1181 if (status & WDCS_ERR) {
1182 chp->ch_error = CHP_READ_REG(chp, wdr_error);
1183 WDC_LOG_ERROR(chp, chp->ch_error);
1184
1185 WDCDEBUG_PRINT(("wdcwait: error %x\n", chp->ch_error),
1186 DEBUG_STATUSX | DEBUG_STATUS);
1187 }
1188
1189 #ifdef WDCNDELAY_DEBUG
1190 /* After autoconfig, there should be no long delays. */
1191 if (!cold && time > WDCNDELAY_DEBUG) {
1192 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer);
1193 if (xfer == NULL)
1194 printf("%s channel %d: warning: busy-wait took %dus\n",
1195 chp->wdc->sc_dev.dv_xname, chp->channel,
1196 WDCDELAY * time);
1197 else
1198 printf("%s:%d:%d: warning: busy-wait took %dus\n",
1199 chp->wdc->sc_dev.dv_xname, chp->channel,
1200 xfer->drive,
1201 WDCDELAY * time);
1202 }
1203 #endif /* WDCNDELAY_DEBUG */
1204 return time;
1205 }
1206
1207 /*
1208 * Busy-wait for DMA to complete
1209 */
1210 int
wdc_dmawait(chp,xfer,timeout)1211 wdc_dmawait(chp, xfer, timeout)
1212 struct channel_softc *chp;
1213 struct wdc_xfer *xfer;
1214 int timeout;
1215 {
1216 int time;
1217 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) {
1218 chp->wdc->dma_status =
1219 (*chp->wdc->dma_finish)(chp->wdc->dma_arg,
1220 chp->channel, xfer->drive, 0);
1221 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0)
1222 return 0;
1223 delay(WDCDELAY);
1224 }
1225 /* timeout, force a DMA halt */
1226 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg,
1227 chp->channel, xfer->drive, 1);
1228 return 1;
1229 }
1230
1231 void
wdctimeout(arg)1232 wdctimeout(arg)
1233 void *arg;
1234 {
1235 struct channel_softc *chp = (struct channel_softc *)arg;
1236 struct wdc_xfer *xfer;
1237 int s;
1238
1239 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS);
1240
1241 s = splbio();
1242 xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer);
1243
1244 /* Did we lose a race with the interrupt? */
1245 if (xfer == NULL ||
1246 !timeout_triggered(&chp->ch_timo)) {
1247 splx(s);
1248 return;
1249 }
1250 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) {
1251 __wdcerror(chp, "timeout");
1252 printf("\ttype: %s\n", (xfer->c_flags & C_ATAPI) ?
1253 "atapi":"ata");
1254 printf("\tc_bcount: %d\n", xfer->c_bcount);
1255 printf("\tc_skip: %d\n", xfer->c_skip);
1256 if (chp->ch_flags & WDCF_DMA_WAIT) {
1257 chp->wdc->dma_status =
1258 (*chp->wdc->dma_finish)(chp->wdc->dma_arg,
1259 chp->channel, xfer->drive, 1);
1260 chp->ch_flags &= ~WDCF_DMA_WAIT;
1261 }
1262 /*
1263 * Call the interrupt routine. If we just missed and interrupt,
1264 * it will do what's needed. Else, it will take the needed
1265 * action (reset the device).
1266 */
1267 xfer->c_flags |= C_TIMEOU;
1268 chp->ch_flags &= ~WDCF_IRQ_WAIT;
1269 xfer->c_intr(chp, xfer, 1);
1270 } else
1271 __wdcerror(chp, "missing untimeout");
1272 splx(s);
1273 }
1274
1275 /*
1276 * Probe drive's capabilities, for use by the controller later.
1277 * Assumes drvp points to an existing drive.
1278 * XXX this should be a controller-indep function
1279 */
1280 void
wdc_probe_caps(drvp,params)1281 wdc_probe_caps(drvp, params)
1282 struct ata_drive_datas *drvp;
1283 struct ataparams *params;
1284 {
1285 struct channel_softc *chp = drvp->chnl_softc;
1286 struct wdc_softc *wdc = chp->wdc;
1287 int i, valid_mode_found;
1288 int cf_flags = drvp->cf_flags;
1289
1290 if ((wdc->cap & WDC_CAPABILITY_SATA) != 0 &&
1291 (params->atap_sata_caps != 0x0000 &&
1292 params->atap_sata_caps != 0xffff)) {
1293 WDCDEBUG_PRINT(("%s: atap_sata_caps=0x%x\n", __func__,
1294 params->atap_sata_caps), DEBUG_PROBE);
1295
1296 /* Skip ATA modes detection for native SATA drives */
1297 drvp->PIO_mode = drvp->PIO_cap = 4;
1298 drvp->DMA_mode = drvp->DMA_cap = 2;
1299 drvp->UDMA_mode = drvp->UDMA_cap = 5;
1300 drvp->drive_flags |= DRIVE_SATA | DRIVE_MODE | DRIVE_UDMA;
1301 drvp->ata_vers = 4;
1302 return;
1303 }
1304
1305 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) ==
1306 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) {
1307 struct ataparams params2;
1308
1309 /*
1310 * Controller claims 16 and 32 bit transfers.
1311 * Re-do an IDENTIFY with 32-bit transfers,
1312 * and compare results.
1313 */
1314 drvp->drive_flags |= DRIVE_CAP32;
1315 ata_get_params(drvp, at_poll, ¶ms2);
1316 if (bcmp(params, ¶ms2, sizeof(struct ataparams)) != 0) {
1317 /* Not good. fall back to 16bits */
1318 drvp->drive_flags &= ~DRIVE_CAP32;
1319 }
1320 }
1321 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */
1322 if (params->atap_ata_major > 0x01 &&
1323 params->atap_ata_major != 0xffff) {
1324 for (i = 14; i > 0; i--) {
1325 if (params->atap_ata_major & (1 << i)) {
1326 printf("%sATA version %d\n", sep, i);
1327 drvp->ata_vers = i;
1328 break;
1329 }
1330 }
1331 } else
1332 #endif /* 0 */
1333 /* Use PIO mode 3 as a default value for ATAPI devices */
1334 if (drvp->drive_flags & DRIVE_ATAPI)
1335 drvp->PIO_mode = 3;
1336
1337 WDCDEBUG_PRINT(("wdc_probe_caps: wdc_cap 0x%x cf_flags 0x%x\n",
1338 wdc->cap, cf_flags), DEBUG_PROBE);
1339
1340 valid_mode_found = 0;
1341
1342 WDCDEBUG_PRINT(("%s: atap_oldpiotiming=%d\n", __func__,
1343 params->atap_oldpiotiming), DEBUG_PROBE);
1344 /*
1345 * ATA-4 compliant devices contain PIO mode
1346 * number in atap_oldpiotiming.
1347 */
1348 if (params->atap_oldpiotiming <= 2) {
1349 drvp->PIO_cap = params->atap_oldpiotiming;
1350 valid_mode_found = 1;
1351 drvp->drive_flags |= DRIVE_MODE;
1352 } else if (params->atap_oldpiotiming > 180) {
1353 /*
1354 * ATA-2 compliant devices contain cycle
1355 * time in atap_oldpiotiming.
1356 * A device with a cycle time of 180ns
1357 * or less is at least PIO mode 3 and
1358 * should be reporting that in
1359 * atap_piomode_supp, so ignore it here.
1360 */
1361 if (params->atap_oldpiotiming <= 240) {
1362 drvp->PIO_cap = 2;
1363 } else {
1364 drvp->PIO_cap = 1;
1365 }
1366 valid_mode_found = 1;
1367 drvp->drive_flags |= DRIVE_MODE;
1368 }
1369 if (valid_mode_found)
1370 drvp->PIO_mode = drvp->PIO_cap;
1371
1372 WDCDEBUG_PRINT(("%s: atap_extensions=0x%x, atap_piomode_supp=0x%x, "
1373 "atap_dmamode_supp=0x%x, atap_udmamode_supp=0x%x\n",
1374 __func__, params->atap_extensions, params->atap_piomode_supp,
1375 params->atap_dmamode_supp, params->atap_udmamode_supp),
1376 DEBUG_PROBE);
1377
1378 /*
1379 * It's not in the specs, but it seems that some drive
1380 * returns 0xffff in atap_extensions when this field is invalid
1381 */
1382 if (params->atap_extensions != 0xffff &&
1383 (params->atap_extensions & WDC_EXT_MODES)) {
1384 /*
1385 * XXX some drives report something wrong here (they claim to
1386 * support PIO mode 8 !). As mode is coded on 3 bits in
1387 * SET FEATURE, limit it to 7 (so limit i to 4).
1388 * If higher mode than 7 is found, abort.
1389 */
1390 for (i = 7; i >= 0; i--) {
1391 if ((params->atap_piomode_supp & (1 << i)) == 0)
1392 continue;
1393 if (i > 4)
1394 return;
1395
1396 valid_mode_found = 1;
1397
1398 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0) {
1399 drvp->PIO_cap = i + 3;
1400 continue;
1401 }
1402
1403 /*
1404 * See if mode is accepted.
1405 * If the controller can't set its PIO mode,
1406 * assume the BIOS set it up correctly
1407 */
1408 if (ata_set_mode(drvp, 0x08 | (i + 3),
1409 at_poll) != CMD_OK)
1410 continue;
1411
1412 /*
1413 * If controller's driver can't set its PIO mode,
1414 * set the highest one the controller supports
1415 */
1416 if (wdc->PIO_cap >= i + 3) {
1417 drvp->PIO_mode = i + 3;
1418 drvp->PIO_cap = i + 3;
1419 break;
1420 }
1421 }
1422 if (!valid_mode_found) {
1423 /*
1424 * We didn't find a valid PIO mode.
1425 * Assume the values returned for DMA are buggy too
1426 */
1427 return;
1428 }
1429 drvp->drive_flags |= DRIVE_MODE;
1430
1431 /* Some controllers don't support ATAPI DMA */
1432 if ((drvp->drive_flags & DRIVE_ATAPI) &&
1433 (wdc->cap & WDC_CAPABILITY_NO_ATAPI_DMA))
1434 return;
1435
1436 valid_mode_found = 0;
1437 for (i = 7; i >= 0; i--) {
1438 if ((params->atap_dmamode_supp & (1 << i)) == 0)
1439 continue;
1440 if ((wdc->cap & WDC_CAPABILITY_DMA) &&
1441 (wdc->cap & WDC_CAPABILITY_MODE))
1442 if (ata_set_mode(drvp, 0x20 | i, at_poll)
1443 != CMD_OK)
1444 continue;
1445
1446 valid_mode_found = 1;
1447
1448 if (wdc->cap & WDC_CAPABILITY_DMA) {
1449 if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1450 wdc->DMA_cap < i)
1451 continue;
1452 drvp->DMA_mode = i;
1453 drvp->DMA_cap = i;
1454 drvp->drive_flags |= DRIVE_DMA;
1455 }
1456 break;
1457 }
1458 if (params->atap_extensions & WDC_EXT_UDMA_MODES) {
1459 for (i = 7; i >= 0; i--) {
1460 if ((params->atap_udmamode_supp & (1 << i))
1461 == 0)
1462 continue;
1463 if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1464 (wdc->cap & WDC_CAPABILITY_UDMA))
1465 if (ata_set_mode(drvp, 0x40 | i,
1466 at_poll) != CMD_OK)
1467 continue;
1468 if (wdc->cap & WDC_CAPABILITY_UDMA) {
1469 if ((wdc->cap & WDC_CAPABILITY_MODE) &&
1470 wdc->UDMA_cap < i)
1471 continue;
1472 drvp->UDMA_mode = i;
1473 drvp->UDMA_cap = i;
1474 drvp->drive_flags |= DRIVE_UDMA;
1475 }
1476 break;
1477 }
1478 }
1479 }
1480
1481 /* Try to guess ATA version here, if it didn't get reported */
1482 if (drvp->ata_vers == 0) {
1483 if (drvp->drive_flags & DRIVE_UDMA)
1484 drvp->ata_vers = 4; /* should be at last ATA-4 */
1485 else if (drvp->PIO_cap > 2)
1486 drvp->ata_vers = 2; /* should be at last ATA-2 */
1487 }
1488 if (cf_flags & ATA_CONFIG_PIO_SET) {
1489 drvp->PIO_mode =
1490 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF;
1491 drvp->drive_flags |= DRIVE_MODE;
1492 }
1493 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) {
1494 /* don't care about DMA modes */
1495 return;
1496 }
1497 if (cf_flags & ATA_CONFIG_DMA_SET) {
1498 if ((cf_flags & ATA_CONFIG_DMA_MODES) ==
1499 ATA_CONFIG_DMA_DISABLE) {
1500 drvp->drive_flags &= ~DRIVE_DMA;
1501 } else {
1502 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >>
1503 ATA_CONFIG_DMA_OFF;
1504 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE;
1505 }
1506 }
1507 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) {
1508 /* don't care about UDMA modes */
1509 return;
1510 }
1511 if (cf_flags & ATA_CONFIG_UDMA_SET) {
1512 if ((cf_flags & ATA_CONFIG_UDMA_MODES) ==
1513 ATA_CONFIG_UDMA_DISABLE) {
1514 drvp->drive_flags &= ~DRIVE_UDMA;
1515 } else {
1516 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >>
1517 ATA_CONFIG_UDMA_OFF;
1518 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE;
1519 }
1520 }
1521 }
1522
1523 void
wdc_output_bytes(drvp,bytes,buflen)1524 wdc_output_bytes(drvp, bytes, buflen)
1525 struct ata_drive_datas *drvp;
1526 void *bytes;
1527 unsigned int buflen;
1528 {
1529 struct channel_softc *chp = drvp->chnl_softc;
1530 unsigned int off = 0;
1531 unsigned int len = buflen, roundlen;
1532
1533 if (drvp->drive_flags & DRIVE_CAP32) {
1534 roundlen = len & ~3;
1535
1536 CHP_WRITE_RAW_MULTI_4(chp,
1537 (void *)((u_int8_t *)bytes + off), roundlen);
1538
1539 off += roundlen;
1540 len -= roundlen;
1541 }
1542
1543 if (len > 0) {
1544 roundlen = (len + 1) & ~0x1;
1545
1546 CHP_WRITE_RAW_MULTI_2(chp,
1547 (void *)((u_int8_t *)bytes + off), roundlen);
1548 }
1549
1550 return;
1551 }
1552
1553 void
wdc_input_bytes(drvp,bytes,buflen)1554 wdc_input_bytes(drvp, bytes, buflen)
1555 struct ata_drive_datas *drvp;
1556 void *bytes;
1557 unsigned int buflen;
1558 {
1559 struct channel_softc *chp = drvp->chnl_softc;
1560 unsigned int off = 0;
1561 unsigned int len = buflen, roundlen;
1562
1563 if (drvp->drive_flags & DRIVE_CAP32) {
1564 roundlen = len & ~3;
1565
1566 CHP_READ_RAW_MULTI_4(chp,
1567 (void *)((u_int8_t *)bytes + off), roundlen);
1568
1569 off += roundlen;
1570 len -= roundlen;
1571 }
1572
1573 if (len > 0) {
1574 roundlen = (len + 1) & ~0x1;
1575
1576 CHP_READ_RAW_MULTI_2(chp,
1577 (void *)((u_int8_t *)bytes + off), roundlen);
1578 }
1579
1580 return;
1581 }
1582
1583 void
wdc_print_caps(drvp)1584 wdc_print_caps(drvp)
1585 struct ata_drive_datas *drvp;
1586 {
1587 /* This is actually a lie until we fix the _probe_caps
1588 algorithm. Don't print out lies */
1589 #if 0
1590 printf("%s: can use ", drvp->drive_name);
1591
1592 if (drvp->drive_flags & DRIVE_CAP32) {
1593 printf("32-bit");
1594 } else
1595 printf("16-bit");
1596
1597 printf(", PIO mode %d", drvp->PIO_cap);
1598
1599 if (drvp->drive_flags & DRIVE_DMA) {
1600 printf(", DMA mode %d", drvp->DMA_cap);
1601 }
1602
1603 if (drvp->drive_flags & DRIVE_UDMA) {
1604 printf(", Ultra-DMA mode %d", drvp->UDMA_cap);
1605 }
1606
1607 printf("\n");
1608 #endif /* 0 */
1609 }
1610
1611 void
wdc_print_current_modes(chp)1612 wdc_print_current_modes(chp)
1613 struct channel_softc *chp;
1614 {
1615 int drive;
1616 struct ata_drive_datas *drvp;
1617
1618 for (drive = 0; drive < 2; drive++) {
1619 drvp = &chp->ch_drive[drive];
1620 if ((drvp->drive_flags & DRIVE) == 0)
1621 continue;
1622
1623 printf("%s(%s:%d:%d):",
1624 drvp->drive_name,
1625 chp->wdc->sc_dev.dv_xname, chp->channel, drive);
1626
1627 if ((chp->wdc->cap & WDC_CAPABILITY_MODE) == 0 &&
1628 !(drvp->cf_flags & ATA_CONFIG_PIO_SET))
1629 printf(" using BIOS timings");
1630 else
1631 printf(" using PIO mode %d", drvp->PIO_mode);
1632 if (drvp->drive_flags & DRIVE_DMA)
1633 printf(", DMA mode %d", drvp->DMA_mode);
1634 if (drvp->drive_flags & DRIVE_UDMA)
1635 printf(", Ultra-DMA mode %d", drvp->UDMA_mode);
1636 printf("\n");
1637 }
1638 }
1639
1640 /*
1641 * downgrade the transfer mode of a drive after an error. return 1 if
1642 * downgrade was possible, 0 otherwise.
1643 */
1644 int
wdc_downgrade_mode(drvp)1645 wdc_downgrade_mode(drvp)
1646 struct ata_drive_datas *drvp;
1647 {
1648 struct channel_softc *chp = drvp->chnl_softc;
1649 struct wdc_softc *wdc = chp->wdc;
1650 int cf_flags = drvp->cf_flags;
1651
1652 /* if drive or controller don't know its mode, we can't do much */
1653 if ((drvp->drive_flags & DRIVE_MODE) == 0 ||
1654 (wdc->cap & WDC_CAPABILITY_MODE) == 0)
1655 return 0;
1656 /* current drive mode was set by a config flag, let it this way */
1657 if ((cf_flags & ATA_CONFIG_PIO_SET) ||
1658 (cf_flags & ATA_CONFIG_DMA_SET) ||
1659 (cf_flags & ATA_CONFIG_UDMA_SET))
1660 return 0;
1661
1662 /*
1663 * We'd ideally like to use an Ultra DMA mode since they have the
1664 * protection of a CRC. So we try each Ultra DMA mode and see if
1665 * we can find any working combo
1666 */
1667 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode > 0) {
1668 drvp->UDMA_mode = drvp->UDMA_mode - 1;
1669 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n",
1670 drvp->drive_name, drvp->UDMA_mode);
1671 } else if ((drvp->drive_flags & DRIVE_UDMA) &&
1672 (drvp->drive_flags & DRIVE_DMAERR) == 0) {
1673 /*
1674 * If we were using ultra-DMA, don't downgrade to
1675 * multiword DMA if we noticed a CRC error. It has
1676 * been noticed that CRC errors in ultra-DMA lead to
1677 * silent data corruption in multiword DMA. Data
1678 * corruption is less likely to occur in PIO mode.
1679 */
1680 drvp->drive_flags &= ~DRIVE_UDMA;
1681 drvp->drive_flags |= DRIVE_DMA;
1682 drvp->DMA_mode = drvp->DMA_cap;
1683 printf("%s: transfer error, downgrading to DMA mode %d\n",
1684 drvp->drive_name, drvp->DMA_mode);
1685 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) {
1686 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA);
1687 drvp->PIO_mode = drvp->PIO_cap;
1688 printf("%s: transfer error, downgrading to PIO mode %d\n",
1689 drvp->drive_name, drvp->PIO_mode);
1690 } else /* already using PIO, can't downgrade */
1691 return 0;
1692
1693 wdc->set_modes(chp);
1694 /* reset the channel, which will schedule all drives for setup */
1695 wdc_reset_channel(drvp);
1696 return 1;
1697 }
1698
1699 int
wdc_exec_command(drvp,wdc_c)1700 wdc_exec_command(drvp, wdc_c)
1701 struct ata_drive_datas *drvp;
1702 struct wdc_command *wdc_c;
1703 {
1704 struct channel_softc *chp = drvp->chnl_softc;
1705 struct wdc_xfer *xfer;
1706 int s, ret;
1707
1708 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n",
1709 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive),
1710 DEBUG_FUNCS);
1711
1712 /* set up an xfer and queue. Wait for completion */
1713 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP :
1714 WDC_NOSLEEP);
1715 if (xfer == NULL) {
1716 return WDC_TRY_AGAIN;
1717 }
1718
1719 if (wdc_c->flags & AT_POLL)
1720 xfer->c_flags |= C_POLL;
1721 xfer->drive = drvp->drive;
1722 xfer->databuf = wdc_c->data;
1723 xfer->c_bcount = wdc_c->bcount;
1724 xfer->cmd = wdc_c;
1725 xfer->c_start = __wdccommand_start;
1726 xfer->c_intr = __wdccommand_intr;
1727 xfer->c_kill_xfer = __wdccommand_done;
1728
1729 s = splbio();
1730 wdc_exec_xfer(chp, xfer);
1731 #ifdef DIAGNOSTIC
1732 if ((wdc_c->flags & AT_POLL) != 0 &&
1733 (wdc_c->flags & AT_DONE) == 0)
1734 panic("wdc_exec_command: polled command not done");
1735 #endif /* DIAGNOSTIC */
1736 if (wdc_c->flags & AT_DONE) {
1737 ret = WDC_COMPLETE;
1738 } else {
1739 if (wdc_c->flags & AT_WAIT) {
1740 WDCDEBUG_PRINT(("wdc_exec_command sleeping\n"),
1741 DEBUG_FUNCS);
1742
1743 while ((wdc_c->flags & AT_DONE) == 0) {
1744 tsleep(wdc_c, PRIBIO, "wdccmd", 0);
1745 }
1746 ret = WDC_COMPLETE;
1747 } else {
1748 ret = WDC_QUEUED;
1749 }
1750 }
1751 splx(s);
1752 return ret;
1753 }
1754
1755 void
__wdccommand_start(chp,xfer)1756 __wdccommand_start(chp, xfer)
1757 struct channel_softc *chp;
1758 struct wdc_xfer *xfer;
1759 {
1760 int drive = xfer->drive;
1761 struct wdc_command *wdc_c = xfer->cmd;
1762
1763 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n",
1764 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive),
1765 DEBUG_FUNCS);
1766
1767 /*
1768 * Disable interrupts if we're polling
1769 */
1770 if (xfer->c_flags & C_POLL) {
1771 wdc_disable_intr(chp);
1772 }
1773
1774 wdc_set_drive(chp, drive);
1775 DELAY(1);
1776
1777 /*
1778 * For resets, we don't really care to make sure that
1779 * the bus is free
1780 */
1781 if (wdc_c->r_command != ATAPI_SOFT_RESET) {
1782 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ,
1783 wdc_c->r_st_bmask, wdc_c->timeout) != 0) {
1784 goto timeout;
1785 }
1786 } else
1787 DELAY(10);
1788
1789 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head,
1790 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp);
1791
1792 if ((wdc_c->flags & AT_WRITE) == AT_WRITE) {
1793 /* wait at least 400ns before reading status register */
1794 DELAY(10);
1795 if (wait_for_unbusy(chp, wdc_c->timeout) != 0)
1796 goto timeout;
1797
1798 if ((chp->ch_status & (WDCS_DRQ | WDCS_ERR)) == WDCS_ERR) {
1799 __wdccommand_done(chp, xfer);
1800 return;
1801 }
1802
1803 if (wait_for_drq(chp, wdc_c->timeout) != 0)
1804 goto timeout;
1805
1806 wdc_output_bytes(&chp->ch_drive[drive],
1807 wdc_c->data, wdc_c->bcount);
1808 }
1809
1810 if ((wdc_c->flags & AT_POLL) == 0) {
1811 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */
1812 timeout_add(&chp->ch_timo, wdc_c->timeout / 1000 * hz);
1813 return;
1814 }
1815
1816 /*
1817 * Polled command. Wait for drive ready or drq. Done in intr().
1818 * Wait for at last 400ns for status bit to be valid.
1819 */
1820 delay(10);
1821 __wdccommand_intr(chp, xfer, 0);
1822 return;
1823
1824 timeout:
1825 wdc_c->flags |= AT_TIMEOU;
1826 __wdccommand_done(chp, xfer);
1827 }
1828
1829 int
__wdccommand_intr(chp,xfer,irq)1830 __wdccommand_intr(chp, xfer, irq)
1831 struct channel_softc *chp;
1832 struct wdc_xfer *xfer;
1833 int irq;
1834 {
1835 struct ata_drive_datas *drvp = &chp->ch_drive[xfer->drive];
1836 struct wdc_command *wdc_c = xfer->cmd;
1837 int bcount = wdc_c->bcount;
1838 char *data = wdc_c->data;
1839
1840 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n",
1841 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR);
1842 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask,
1843 (irq == 0) ? wdc_c->timeout : 0)) {
1844 if (irq && (xfer->c_flags & C_TIMEOU) == 0)
1845 return 0; /* IRQ was not for us */
1846 wdc_c->flags |= AT_TIMEOU;
1847 goto out;
1848 }
1849 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK)
1850 chp->wdc->irqack(chp);
1851 if (wdc_c->flags & AT_READ) {
1852 if ((chp->ch_status & WDCS_DRQ) == 0) {
1853 wdc_c->flags |= AT_TIMEOU;
1854 goto out;
1855 }
1856 wdc_input_bytes(drvp, data, bcount);
1857 /* Should we wait for device to indicate idle? */
1858 }
1859 out:
1860 __wdccommand_done(chp, xfer);
1861 WDCDEBUG_PRINT(("__wdccommand_intr returned\n"), DEBUG_INTR);
1862 return 1;
1863 }
1864
1865 void
__wdccommand_done(chp,xfer)1866 __wdccommand_done(chp, xfer)
1867 struct channel_softc *chp;
1868 struct wdc_xfer *xfer;
1869 {
1870 struct wdc_command *wdc_c = xfer->cmd;
1871
1872 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d %02x\n",
1873 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive,
1874 chp->ch_status), DEBUG_FUNCS);
1875 if (chp->ch_status & WDCS_DWF)
1876 wdc_c->flags |= AT_DF;
1877 if (chp->ch_status & WDCS_ERR) {
1878 wdc_c->flags |= AT_ERROR;
1879 wdc_c->r_error = chp->ch_error;
1880 }
1881 wdc_c->flags |= AT_DONE;
1882 if ((wdc_c->flags & AT_READREG) != 0 &&
1883 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) {
1884 wdc_c->r_head = CHP_READ_REG(chp, wdr_sdh);
1885 wdc_c->r_cyl = CHP_READ_REG(chp, wdr_cyl_hi) << 8;
1886 wdc_c->r_cyl |= CHP_READ_REG(chp, wdr_cyl_lo);
1887 wdc_c->r_sector = CHP_READ_REG(chp, wdr_sector);
1888 wdc_c->r_count = CHP_READ_REG(chp, wdr_seccnt);
1889 wdc_c->r_error = CHP_READ_REG(chp, wdr_error);
1890 wdc_c->r_precomp = wdc_c->r_error;
1891 /* XXX CHP_READ_REG(chp, wdr_precomp); - precomp
1892 isn't a readable register */
1893 }
1894
1895 if (xfer->c_flags & C_POLL) {
1896 wdc_enable_intr(chp);
1897 }
1898
1899 wdc_free_xfer(chp, xfer);
1900 WDCDEBUG_PRINT(("__wdccommand_done before callback\n"), DEBUG_INTR);
1901
1902 if (wdc_c->flags & AT_WAIT)
1903 wakeup(wdc_c);
1904 else
1905 if (wdc_c->callback)
1906 wdc_c->callback(wdc_c->callback_arg);
1907 wdcstart(chp);
1908 WDCDEBUG_PRINT(("__wdccommand_done returned\n"), DEBUG_INTR);
1909 }
1910
1911 /*
1912 * Send a command. The drive should be ready.
1913 * Assumes interrupts are blocked.
1914 */
1915 void
wdccommand(chp,drive,command,cylin,head,sector,count,precomp)1916 wdccommand(chp, drive, command, cylin, head, sector, count, precomp)
1917 struct channel_softc *chp;
1918 u_int8_t drive;
1919 u_int8_t command;
1920 u_int16_t cylin;
1921 u_int8_t head, sector, count, precomp;
1922 {
1923 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d "
1924 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname,
1925 chp->channel, drive, command, cylin, head, sector, count, precomp),
1926 DEBUG_FUNCS);
1927 WDC_LOG_ATA_CMDLONG(chp, head, precomp, cylin, cylin >> 8, sector,
1928 count, command);
1929
1930 /* Select drive, head, and addressing mode. */
1931 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4) | head);
1932
1933 /* Load parameters. wdr_features(ATA/ATAPI) = wdr_precomp(ST506) */
1934 CHP_WRITE_REG(chp, wdr_precomp, precomp);
1935 CHP_WRITE_REG(chp, wdr_cyl_lo, cylin);
1936 CHP_WRITE_REG(chp, wdr_cyl_hi, cylin >> 8);
1937 CHP_WRITE_REG(chp, wdr_sector, sector);
1938 CHP_WRITE_REG(chp, wdr_seccnt, count);
1939
1940 /* Send command. */
1941 CHP_WRITE_REG(chp, wdr_command, command);
1942 return;
1943 }
1944
1945 /*
1946 * Send a 48-bit addressing command. The drive should be ready.
1947 * Assumes interrupts are blocked.
1948 */
1949 void
wdccommandext(chp,drive,command,blkno,count)1950 wdccommandext(chp, drive, command, blkno, count)
1951 struct channel_softc *chp;
1952 u_int8_t drive;
1953 u_int8_t command;
1954 u_int64_t blkno;
1955 u_int16_t count;
1956 {
1957 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%llu "
1958 "count=%d\n", chp->wdc->sc_dev.dv_xname,
1959 chp->channel, drive, command, blkno, count),
1960 DEBUG_FUNCS);
1961 WDC_LOG_ATA_CMDEXT(chp, blkno >> 40, blkno >> 16, blkno >> 32,
1962 blkno >> 8, blkno >> 24, blkno, count >> 8, count, command);
1963
1964 /* Select drive and LBA mode. */
1965 CHP_WRITE_REG(chp, wdr_sdh, (drive << 4) | WDSD_LBA);
1966
1967 /* Load parameters. All registers are two byte deep FIFOs. */
1968 CHP_WRITE_REG(chp, wdr_lba_hi, blkno >> 40);
1969 CHP_WRITE_REG(chp, wdr_lba_hi, blkno >> 16);
1970 CHP_WRITE_REG(chp, wdr_lba_mi, blkno >> 32);
1971 CHP_WRITE_REG(chp, wdr_lba_mi, blkno >> 8);
1972 CHP_WRITE_REG(chp, wdr_lba_lo, blkno >> 24);
1973 CHP_WRITE_REG(chp, wdr_lba_lo, blkno);
1974 CHP_WRITE_REG(chp, wdr_seccnt, count >> 8);
1975 CHP_WRITE_REG(chp, wdr_seccnt, count);
1976
1977 /* Send command. */
1978 CHP_WRITE_REG(chp, wdr_command, command);
1979 return;
1980 }
1981
1982 /*
1983 * Simplified version of wdccommand(). Unbusy/ready/drq must be
1984 * tested by the caller.
1985 */
1986 void
wdccommandshort(chp,drive,command)1987 wdccommandshort(chp, drive, command)
1988 struct channel_softc *chp;
1989 int drive;
1990 int command;
1991 {
1992
1993 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n",
1994 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command),
1995 DEBUG_FUNCS);
1996 WDC_LOG_ATA_CMDSHORT(chp, command);
1997
1998 /* Select drive. */
1999 CHP_WRITE_REG(chp, wdr_sdh, WDSD_IBM | (drive << 4));
2000 CHP_WRITE_REG(chp, wdr_command, command);
2001 }
2002
2003 /* Add a command to the queue and start controller. Must be called at splbio */
2004
2005 void
wdc_exec_xfer(chp,xfer)2006 wdc_exec_xfer(chp, xfer)
2007 struct channel_softc *chp;
2008 struct wdc_xfer *xfer;
2009 {
2010 WDCDEBUG_PRINT(("wdc_exec_xfer %p flags 0x%x channel %d drive %d\n",
2011 xfer, xfer->c_flags, chp->channel, xfer->drive), DEBUG_XFERS);
2012
2013 /* complete xfer setup */
2014 xfer->chp = chp;
2015
2016 /*
2017 * If we are a polled command, and the list is not empty,
2018 * we are doing a dump. Drop the list to allow the polled command
2019 * to complete, we're going to reboot soon anyway.
2020 */
2021 if ((xfer->c_flags & C_POLL) != 0 &&
2022 !TAILQ_EMPTY(&chp->ch_queue->sc_xfer)) {
2023 TAILQ_INIT(&chp->ch_queue->sc_xfer);
2024 }
2025 /* insert at the end of command list */
2026 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain);
2027 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n",
2028 chp->ch_flags), DEBUG_XFERS);
2029 wdcstart(chp);
2030 }
2031
2032 struct wdc_xfer *
wdc_get_xfer(flags)2033 wdc_get_xfer(flags)
2034 int flags;
2035 {
2036 struct wdc_xfer *xfer;
2037 int s;
2038
2039 s = splbio();
2040 xfer = pool_get(&wdc_xfer_pool,
2041 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK));
2042 splx(s);
2043 if (xfer != NULL)
2044 memset(xfer, 0, sizeof(struct wdc_xfer));
2045 return xfer;
2046 }
2047
2048 void
wdc_free_xfer(chp,xfer)2049 wdc_free_xfer(chp, xfer)
2050 struct channel_softc *chp;
2051 struct wdc_xfer *xfer;
2052 {
2053 struct wdc_softc *wdc = chp->wdc;
2054 int s;
2055
2056 if (wdc->cap & WDC_CAPABILITY_HWLOCK)
2057 (*wdc->free_hw)(chp);
2058 s = splbio();
2059 chp->ch_flags &= ~WDCF_ACTIVE;
2060 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain);
2061 pool_put(&wdc_xfer_pool, xfer);
2062 splx(s);
2063 }
2064
2065
2066 /*
2067 * Kill off all pending xfers for a channel_softc.
2068 *
2069 * Must be called at splbio().
2070 */
2071 void
wdc_kill_pending(chp)2072 wdc_kill_pending(chp)
2073 struct channel_softc *chp;
2074 {
2075 struct wdc_xfer *xfer;
2076
2077 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) {
2078 chp = xfer->chp;
2079 (*xfer->c_kill_xfer)(chp, xfer);
2080 }
2081 }
2082
2083 void
__wdcerror(chp,msg)2084 __wdcerror(chp, msg)
2085 struct channel_softc *chp;
2086 char *msg;
2087 {
2088 struct wdc_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer);
2089 if (xfer == NULL)
2090 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel,
2091 msg);
2092 else
2093 printf("%s(%s:%d:%d): %s\n",
2094 chp->ch_drive[xfer->drive].drive_name,
2095 chp->wdc->sc_dev.dv_xname,
2096 chp->channel, xfer->drive, msg);
2097 }
2098
2099 /*
2100 * the bit bucket
2101 */
2102 void
wdcbit_bucket(chp,size)2103 wdcbit_bucket(chp, size)
2104 struct channel_softc *chp;
2105 int size;
2106 {
2107 CHP_READ_RAW_MULTI_2(chp, NULL, size);
2108 }
2109
2110
2111 #include <sys/ataio.h>
2112 #include <sys/file.h>
2113 #include <sys/buf.h>
2114
2115 /*
2116 * Glue necessary to hook ATAIOCCOMMAND into physio
2117 */
2118
2119 struct wdc_ioctl {
2120 LIST_ENTRY(wdc_ioctl) wi_list;
2121 struct buf wi_bp;
2122 struct uio wi_uio;
2123 struct iovec wi_iov;
2124 atareq_t wi_atareq;
2125 struct ata_drive_datas *wi_drvp;
2126 };
2127
2128 struct wdc_ioctl *wdc_ioctl_find(struct buf *);
2129 void wdc_ioctl_free(struct wdc_ioctl *);
2130 struct wdc_ioctl *wdc_ioctl_get(void);
2131 void wdc_ioctl_strategy(struct buf *);
2132
2133 LIST_HEAD(, wdc_ioctl) wi_head;
2134
2135 /*
2136 * Allocate space for a ioctl queue structure. Mostly taken from
2137 * scsipi_ioctl.c
2138 */
2139 struct wdc_ioctl *
wdc_ioctl_get()2140 wdc_ioctl_get()
2141 {
2142 struct wdc_ioctl *wi;
2143 int s;
2144
2145 wi = malloc(sizeof(struct wdc_ioctl), M_TEMP, M_WAITOK);
2146 bzero(wi, sizeof (struct wdc_ioctl));
2147 s = splbio();
2148 LIST_INSERT_HEAD(&wi_head, wi, wi_list);
2149 splx(s);
2150 return (wi);
2151 }
2152
2153 /*
2154 * Free an ioctl structure and remove it from our list
2155 */
2156
2157 void
wdc_ioctl_free(wi)2158 wdc_ioctl_free(wi)
2159 struct wdc_ioctl *wi;
2160 {
2161 int s;
2162
2163 s = splbio();
2164 LIST_REMOVE(wi, wi_list);
2165 splx(s);
2166 free(wi, M_TEMP);
2167 }
2168
2169 /*
2170 * Find a wdc_ioctl structure based on the struct buf.
2171 */
2172
2173 struct wdc_ioctl *
wdc_ioctl_find(bp)2174 wdc_ioctl_find(bp)
2175 struct buf *bp;
2176 {
2177 struct wdc_ioctl *wi;
2178 int s;
2179
2180 s = splbio();
2181 LIST_FOREACH(wi, &wi_head, wi_list)
2182 if (bp == &wi->wi_bp)
2183 break;
2184 splx(s);
2185 return (wi);
2186 }
2187
2188 /*
2189 * Ioctl pseudo strategy routine
2190 *
2191 * This is mostly stolen from scsipi_ioctl.c:scsistrategy(). What
2192 * happens here is:
2193 *
2194 * - wdioctl() queues a wdc_ioctl structure.
2195 *
2196 * - wdioctl() calls physio/wdc_ioctl_strategy based on whether or not
2197 * user space I/O is required. If physio() is called, physio() eventually
2198 * calls wdc_ioctl_strategy().
2199 *
2200 * - In either case, wdc_ioctl_strategy() calls wdc_exec_command()
2201 * to perform the actual command
2202 *
2203 * The reason for the use of the pseudo strategy routine is because
2204 * when doing I/O to/from user space, physio _really_ wants to be in
2205 * the loop. We could put the entire buffer into the ioctl request
2206 * structure, but that won't scale if we want to do things like download
2207 * microcode.
2208 */
2209
2210 void
wdc_ioctl_strategy(bp)2211 wdc_ioctl_strategy(bp)
2212 struct buf *bp;
2213 {
2214 struct wdc_ioctl *wi;
2215 struct wdc_command wdc_c;
2216 int error = 0;
2217 int s;
2218
2219 wi = wdc_ioctl_find(bp);
2220 if (wi == NULL) {
2221 printf("user_strat: No ioctl\n");
2222 error = EINVAL;
2223 goto bad;
2224 }
2225
2226 bzero(&wdc_c, sizeof(wdc_c));
2227
2228 /*
2229 * Abort if physio broke up the transfer
2230 */
2231
2232 if ((u_long)bp->b_bcount != wi->wi_atareq.datalen) {
2233 printf("physio split wd ioctl request... cannot proceed\n");
2234 error = EIO;
2235 goto bad;
2236 }
2237
2238 /*
2239 * Make sure a timeout was supplied in the ioctl request
2240 */
2241
2242 if (wi->wi_atareq.timeout == 0) {
2243 error = EINVAL;
2244 goto bad;
2245 }
2246
2247 if (wi->wi_atareq.flags & ATACMD_READ)
2248 wdc_c.flags |= AT_READ;
2249 else if (wi->wi_atareq.flags & ATACMD_WRITE)
2250 wdc_c.flags |= AT_WRITE;
2251
2252 if (wi->wi_atareq.flags & ATACMD_READREG)
2253 wdc_c.flags |= AT_READREG;
2254
2255 wdc_c.flags |= AT_WAIT;
2256
2257 wdc_c.timeout = wi->wi_atareq.timeout;
2258 wdc_c.r_command = wi->wi_atareq.command;
2259 wdc_c.r_head = wi->wi_atareq.head & 0x0f;
2260 wdc_c.r_cyl = wi->wi_atareq.cylinder;
2261 wdc_c.r_sector = wi->wi_atareq.sec_num;
2262 wdc_c.r_count = wi->wi_atareq.sec_count;
2263 wdc_c.r_precomp = wi->wi_atareq.features;
2264 if (wi->wi_drvp->drive_flags & DRIVE_ATAPI) {
2265 wdc_c.r_st_bmask = 0;
2266 wdc_c.r_st_pmask = 0;
2267 if (wdc_c.r_command == WDCC_IDENTIFY)
2268 wdc_c.r_command = ATAPI_IDENTIFY_DEVICE;
2269 } else {
2270 wdc_c.r_st_bmask = WDCS_DRDY;
2271 wdc_c.r_st_pmask = WDCS_DRDY;
2272 }
2273 wdc_c.data = wi->wi_bp.b_data;
2274 wdc_c.bcount = wi->wi_bp.b_bcount;
2275
2276 if (wdc_exec_command(wi->wi_drvp, &wdc_c) != WDC_COMPLETE) {
2277 wi->wi_atareq.retsts = ATACMD_ERROR;
2278 goto bad;
2279 }
2280
2281 if (wdc_c.flags & (AT_ERROR | AT_TIMEOU | AT_DF)) {
2282 if (wdc_c.flags & AT_ERROR) {
2283 wi->wi_atareq.retsts = ATACMD_ERROR;
2284 wi->wi_atareq.error = wdc_c.r_error;
2285 } else if (wdc_c.flags & AT_DF)
2286 wi->wi_atareq.retsts = ATACMD_DF;
2287 else
2288 wi->wi_atareq.retsts = ATACMD_TIMEOUT;
2289 } else {
2290 wi->wi_atareq.retsts = ATACMD_OK;
2291 if (wi->wi_atareq.flags & ATACMD_READREG) {
2292 wi->wi_atareq.head = wdc_c.r_head ;
2293 wi->wi_atareq.cylinder = wdc_c.r_cyl;
2294 wi->wi_atareq.sec_num = wdc_c.r_sector;
2295 wi->wi_atareq.sec_count = wdc_c.r_count;
2296 wi->wi_atareq.features = wdc_c.r_precomp;
2297 wi->wi_atareq.error = wdc_c.r_error;
2298 }
2299 }
2300
2301 bp->b_error = 0;
2302 s = splbio();
2303 biodone(bp);
2304 splx(s);
2305 return;
2306 bad:
2307 bp->b_flags |= B_ERROR;
2308 bp->b_error = error;
2309 s = splbio();
2310 biodone(bp);
2311 splx(s);
2312 }
2313
2314 int
wdc_ioctl(drvp,xfer,addr,flag,p)2315 wdc_ioctl(drvp, xfer, addr, flag, p)
2316 struct ata_drive_datas *drvp;
2317 u_long xfer;
2318 caddr_t addr;
2319 int flag;
2320 struct proc *p;
2321 {
2322 int error = 0;
2323
2324 switch (xfer) {
2325 case ATAIOGETTRACE: {
2326 atagettrace_t *agt = (atagettrace_t *)addr;
2327 unsigned int size = 0;
2328 char *log_to_copy;
2329
2330 size = agt->buf_size;
2331 if (size > 65536) {
2332 size = 65536;
2333 }
2334
2335 log_to_copy = wdc_get_log(&size, &agt->bytes_left);
2336
2337 if (log_to_copy != NULL) {
2338 error = copyout(log_to_copy, agt->buf, size);
2339 free(log_to_copy, M_TEMP);
2340 }
2341
2342 agt->bytes_copied = size;
2343 break;
2344 }
2345
2346 case ATAIOCCOMMAND:
2347 /*
2348 * Make sure this command is (relatively) safe first
2349 */
2350 if ((((atareq_t *) addr)->flags & ATACMD_READ) == 0 &&
2351 (flag & FWRITE) == 0) {
2352 error = EBADF;
2353 goto exit;
2354 }
2355 {
2356 struct wdc_ioctl *wi;
2357 atareq_t *atareq = (atareq_t *) addr;
2358
2359 wi = wdc_ioctl_get();
2360 wi->wi_drvp = drvp;
2361 wi->wi_atareq = *atareq;
2362
2363 if (atareq->datalen && atareq->flags &
2364 (ATACMD_READ | ATACMD_WRITE)) {
2365 wi->wi_iov.iov_base = atareq->databuf;
2366 wi->wi_iov.iov_len = atareq->datalen;
2367 wi->wi_uio.uio_iov = &wi->wi_iov;
2368 wi->wi_uio.uio_iovcnt = 1;
2369 wi->wi_uio.uio_resid = atareq->datalen;
2370 wi->wi_uio.uio_offset = 0;
2371 wi->wi_uio.uio_segflg = UIO_USERSPACE;
2372 wi->wi_uio.uio_rw =
2373 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE;
2374 wi->wi_uio.uio_procp = curproc;
2375 error = physio(wdc_ioctl_strategy, &wi->wi_bp, 0,
2376 (atareq->flags & ATACMD_READ) ? B_READ : B_WRITE,
2377 minphys, &wi->wi_uio);
2378 } else {
2379 /* No need to call physio if we don't have any
2380 user data */
2381 wi->wi_bp.b_flags = 0;
2382 wi->wi_bp.b_data = 0;
2383 wi->wi_bp.b_bcount = 0;
2384 wi->wi_bp.b_dev = 0;
2385 wi->wi_bp.b_proc = curproc;
2386 LIST_INIT(&wi->wi_bp.b_dep);
2387 wdc_ioctl_strategy(&wi->wi_bp);
2388 error = wi->wi_bp.b_error;
2389 }
2390 *atareq = wi->wi_atareq;
2391 wdc_ioctl_free(wi);
2392 goto exit;
2393 }
2394 default:
2395 error = ENOTTY;
2396 goto exit;
2397 }
2398
2399 exit:
2400 return (error);
2401 }
2402