1 /* $OpenBSD: trm.c,v 1.4 2004/01/14 20:50:49 miod Exp $
2 * ------------------------------------------------------------
3 * O.S : OpenBSD
4 * File Name : trm.c
5 * Device Driver for Tekram DC395U/UW/F,DC315/U
6 * PCI SCSI Bus Master Host Adapter
7 * (SCSI chip set used Tekram ASIC TRM-S1040)
8 *
9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd.
10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback
11 * ------------------------------------------------------------
12 * HISTORY:
13 *
14 * REV# DATE NAME DESCRIPTION
15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x
16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8
17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting
18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic
19 * ------------------------------------------------------------
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions
23 * are met:
24 * 1. Redistributions of source code must retain the above copyright
25 * notice, this list of conditions and the following disclaimer.
26 * 2. Redistributions in binary form must reproduce the above copyright
27 * notice, this list of conditions and the following disclaimer in the
28 * documentation and/or other materials provided with the distribution.
29 * 3. The name of the author may not be used to endorse or promote products
30 * derived from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 * ------------------------------------------------------------
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/malloc.h>
50 #include <sys/buf.h>
51 #include <sys/device.h>
52
53 #include <machine/bus.h>
54
55 #include <scsi/scsi_all.h>
56 #include <scsi/scsiconf.h>
57 #include <scsi/scsi_message.h>
58
59 #include <dev/pci/pcidevs.h>
60 #include <dev/ic/trm.h>
61
62 /* #define TRM_DEBUG0 */
63
64 void trm_minphys(struct buf *);
65
66 void trm_initSRB(struct trm_scsi_req_q *);
67
68 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t);
69 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t);
70 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t);
71
72 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t);
73 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t);
74
75 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t);
76
77 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t);
78
79 int trm_scsi_cmd(struct scsi_xfer *);
80
81 struct trm_scsi_req_q *trm_GetFreeSRB(struct trm_softc *);
82
83 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
84 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
85 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
86 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
87 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
88 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
89 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
90 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
91 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
92 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
93 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
94 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
95
96 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int);
97
98 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t);
99
100 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *);
101 void trm_ReleaseSRB (struct trm_softc *, struct trm_scsi_req_q *);
102 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *);
103 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *);
104 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *);
105
106 void trm_initAdapter (struct trm_softc *);
107 void trm_Disconnect (struct trm_softc *);
108 void trm_Reselect (struct trm_softc *);
109 void trm_GoingSRB_Done (struct trm_softc *);
110 void trm_ScsiRstDetect (struct trm_softc *);
111 void trm_ResetSCSIBus (struct trm_softc *);
112 void trm_reset (struct trm_softc *);
113 void trm_StartWaitingSRB (struct trm_softc *);
114 void trm_ResetAllDevParam(struct trm_softc *);
115 void trm_RecoverSRB (struct trm_softc *);
116 void trm_linkSRB (struct trm_softc *);
117
118 void trm_initACB(struct trm_softc *, int);
119
120 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t);
121
122 void trm_EnableMsgOut(struct trm_softc *, u_int8_t);
123
124 void trm_timeout(void *);
125
126 void trm_print_info(struct trm_softc *, struct trm_dcb *);
127
128 /*
129 * Define structures
130 */
131 struct cfdriver trm_cd = {
132 NULL, "trm", DV_DULL
133 };
134
135 struct scsi_adapter trm_switch = {
136 trm_scsi_cmd,
137 trm_minphys,
138 NULL,
139 NULL
140 };
141
142 static struct scsi_device trm_device = {
143 NULL, /* Use default error handler */
144 NULL, /* have a queue, served by this */
145 NULL, /* have no async handler */
146 NULL, /* Use default 'done' routine */
147 };
148
149 /*
150 * ------------------------------------------------------------
151 *
152 * stateV = (void *) trm_SCSI_phase0[phase]
153 *
154 * ------------------------------------------------------------
155 */
156 static void *trm_SCSI_phase0[8] = {
157 trm_DataOutPhase0, /* phase:0 */
158 trm_DataInPhase0, /* phase:1 */
159 trm_Nop, /* phase:2 */
160 trm_StatusPhase0, /* phase:3 */
161 trm_Nop, /* phase:4 */
162 trm_Nop, /* phase:5 */
163 trm_MsgOutPhase0, /* phase:6 */
164 trm_MsgInPhase0, /* phase:7 */
165 };
166
167 /*
168 * ------------------------------------------------------------
169 *
170 * stateV = (void *) trm_SCSI_phase1[phase]
171 *
172 * ------------------------------------------------------------
173 */
174 static void *trm_SCSI_phase1[8] = {
175 trm_DataOutPhase1, /* phase:0 */
176 trm_DataInPhase1, /* phase:1 */
177 trm_CommandPhase1, /* phase:2 */
178 trm_StatusPhase1, /* phase:3 */
179 trm_Nop, /* phase:4 */
180 trm_Nop, /* phase:5 */
181 trm_MsgOutPhase1, /* phase:6 */
182 trm_MsgInPhase1, /* phase:7 */
183 };
184
185
186 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM];
187 /*
188 *Fast20: 000 50ns, 20.0 Mbytes/s
189 * 001 75ns, 13.3 Mbytes/s
190 * 010 100ns, 10.0 Mbytes/s
191 * 011 125ns, 8.0 Mbytes/s
192 * 100 150ns, 6.6 Mbytes/s
193 * 101 175ns, 5.7 Mbytes/s
194 * 110 200ns, 5.0 Mbytes/s
195 * 111 250ns, 4.0 Mbytes/s
196 *
197 *Fast40: 000 25ns, 40.0 Mbytes/s
198 * 001 50ns, 20.0 Mbytes/s
199 * 010 75ns, 13.3 Mbytes/s
200 * 011 100ns, 10.0 Mbytes/s
201 * 100 125ns, 8.0 Mbytes/s
202 * 101 150ns, 6.6 Mbytes/s
203 * 110 175ns, 5.7 Mbytes/s
204 * 111 200ns, 5.0 Mbytes/s
205 */
206
207 /*
208 * real period:
209 */
210 u_int8_t trm_clock_period[8] = {
211 /* nanosecond divided by 4 */
212 12, /* 48 ns 20 MB/sec */
213 18, /* 72 ns 13.3 MB/sec */
214 25, /* 100 ns 10.0 MB/sec */
215 31, /* 124 ns 8.0 MB/sec */
216 37, /* 148 ns 6.6 MB/sec */
217 43, /* 172 ns 5.7 MB/sec */
218 50, /* 200 ns 5.0 MB/sec */
219 62 /* 248 ns 4.0 MB/sec */
220 };
221
222 /*
223 * ------------------------------------------------------------
224 * Function : trm_GetFreeSRB
225 * Purpose : Get the first free SRB
226 * Inputs :
227 * Return : NULL or a free SCSI Request block
228 * ------------------------------------------------------------
229 */
230 struct trm_scsi_req_q *
trm_GetFreeSRB(struct trm_softc * sc)231 trm_GetFreeSRB(struct trm_softc *sc)
232 {
233 struct trm_scsi_req_q *pSRB;
234
235 /* ASSUME we are called from inside a splbio()/splx() region */
236
237 pSRB = TAILQ_FIRST(&sc->freeSRB);
238
239 if (pSRB != NULL)
240 TAILQ_REMOVE(&sc->freeSRB, pSRB, link);
241
242 #ifdef TRM_DEBUG0
243 printf("%s: trm_GetFreeSRB. pSRB = %p, next pSRB = %p\n",
244 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB));
245 #endif
246
247 return pSRB;
248 }
249
250 /*
251 * ------------------------------------------------------------
252 * Function : trm_RewaitSRB
253 * Purpose : Q back to pending Q
254 * Inputs : struct trm_dcb * -
255 * struct trm_scsi_req_q * -
256 * ------------------------------------------------------------
257 */
258 void
trm_RewaitSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)259 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
260 {
261 int intflag;
262
263 intflag = splbio();
264
265 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) {
266 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB;
267 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link);
268 }
269
270 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) {
271 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB;
272 TAILQ_REMOVE(&sc->goingSRB, pSRB, link);
273 }
274
275 pSRB->SRBState = TRM_READY;
276 pSRB->TargetStatus = SCSI_OK;
277 pSRB->AdaptStatus = TRM_STATUS_GOOD;
278
279 pSRB->SRBFlag |= TRM_ON_WAITING_SRB;
280 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link);
281
282 splx(intflag);
283 }
284
285 /*
286 * ------------------------------------------------------------
287 * Function : trm_StartWaitingSRB
288 * Purpose : If there is no active DCB then run robin through
289 * the DCB's to find the next waiting SRB
290 * and move it to the going list.
291 * Inputs : struct trm_softc * -
292 * ------------------------------------------------------------
293 */
294 void
trm_StartWaitingSRB(struct trm_softc * sc)295 trm_StartWaitingSRB(struct trm_softc *sc)
296 {
297 struct trm_scsi_req_q *pSRB;
298 int intflag;
299
300 intflag = splbio();
301
302 if ((sc->pActiveDCB != NULL) ||
303 (TAILQ_EMPTY(&sc->waitingSRB)) ||
304 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0)
305 return;
306
307 TAILQ_FOREACH(pSRB, &sc->waitingSRB, link) {
308 if (trm_StartSRB(sc, pSRB) == 0) {
309 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB;
310 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link);
311 pSRB->SRBFlag |= TRM_ON_GOING_SRB;
312 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link);
313 break;
314 }
315 }
316
317 splx(intflag);
318 }
319
320 /*
321 * ------------------------------------------------------------
322 * Function : trm_scsi_cmd
323 * Purpose : enqueues a SCSI command
324 * Inputs :
325 * Call By : GENERIC SCSI driver
326 * ------------------------------------------------------------
327 */
328 int
trm_scsi_cmd(struct scsi_xfer * xs)329 trm_scsi_cmd(struct scsi_xfer *xs)
330 {
331 struct trm_scsi_req_q *pSRB;
332 bus_space_handle_t ioh;
333 struct trm_softc *sc;
334 bus_space_tag_t iot;
335 struct trm_dcb *pDCB;
336 u_int8_t target, lun;
337 int i, error, intflag, xferflags;
338
339 target = xs->sc_link->target;
340 lun = xs->sc_link->lun;
341
342 sc = (struct trm_softc *)xs->sc_link->adapter_softc;
343 ioh = sc->sc_iohandle;
344 iot = sc->sc_iotag;
345
346 #ifdef TRM_DEBUG0
347 if ((xs->flags & SCSI_POLL) != 0)
348 printf("%s: trm_scsi_cmd. sc = %p, xs = %p, targ/lun = %d/%d opcode = 0x%02x\n",
349 sc->sc_device.dv_xname, sc, xs, target, lun, xs->cmd->opcode);
350 #endif
351
352 if (target >= TRM_MAX_TARGETS) {
353 printf("%s: target=%d >= %d\n",
354 sc->sc_device.dv_xname, target, TRM_MAX_TARGETS);
355 xs->error = XS_DRIVER_STUFFUP;
356 return COMPLETE;
357 }
358 if (lun >= TRM_MAX_LUNS) {
359 printf("%s: lun=%d >= %d\n",
360 sc->sc_device.dv_xname, lun, TRM_MAX_LUNS);
361 xs->error = XS_DRIVER_STUFFUP;
362 return COMPLETE;
363 }
364
365 pDCB = sc->pDCB[target][lun];
366 if (pDCB == NULL) {
367 /* Removed as a result of INQUIRY proving no device present */
368 xs->error = XS_DRIVER_STUFFUP;
369 return COMPLETE;
370 }
371
372 xferflags = xs->flags;
373 if (xferflags & SCSI_RESET) {
374 #ifdef TRM_DEBUG0
375 printf("%s: trm_reset\n", sc->sc_device.dv_xname);
376 #endif
377 trm_reset(sc);
378 xs->error = XS_NOERROR;
379 return COMPLETE;
380 }
381
382 if (xferflags & ITSDONE) {
383 #ifdef TRM_DEBUG0
384 printf("%s: Is it done?\n", sc->sc_device.dv_xname);
385 #endif
386 xs->flags &= ~ITSDONE;
387 }
388
389 xs->error = XS_NOERROR;
390 xs->status = SCSI_OK;
391 xs->resid = 0;
392
393 intflag = splbio();
394
395 pSRB = trm_GetFreeSRB(sc);
396
397 if (pSRB == NULL) {
398 xs->error = XS_DRIVER_STUFFUP;
399 splx(intflag);
400 return TRY_AGAIN_LATER;
401 }
402
403 /*
404 * BuildSRB(pSRB,pDCB);
405 */
406 if (xs->datalen != 0) {
407 #ifdef TRM_DEBUG0
408 printf("%s: xs->datalen=%x\n", sc->sc_device.dv_xname,
409 (u_int32_t)xs->datalen);
410 printf("%s: sc->sc_dmatag=0x%x\n", sc->sc_device.dv_xname,
411 (u_int32_t)sc->sc_dmatag);
412 printf("%s: pSRB->dmamapxfer=0x%x\n", sc->sc_device.dv_xname,
413 (u_int32_t)pSRB->dmamapxfer);
414 printf("%s: xs->data=0x%x\n", sc->sc_device.dv_xname,
415 (u_int32_t)xs->data);
416 #endif
417 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer,
418 xs->data, xs->datalen, NULL,
419 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT :
420 BUS_DMA_WAITOK)) != 0) {
421 printf("%s: DMA transfer map unable to load, error = %d\n"
422 , sc->sc_device.dv_xname, error);
423 xs->error = XS_DRIVER_STUFFUP;
424 /*
425 * free SRB
426 */
427 TAILQ_INSERT_HEAD(&sc->freeSRB, pSRB, link);
428 splx(intflag);
429 return COMPLETE;
430 }
431
432 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer,
433 0, pSRB->dmamapxfer->dm_mapsize,
434 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
435
436 /*
437 * Set up the scatter gather list
438 */
439 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) {
440 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr;
441 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len;
442 }
443 pSRB->SRBTotalXferLength = xs->datalen;
444 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs;
445 }
446
447 pSRB->pSRBDCB = pDCB;
448 pSRB->xs = xs;
449 pSRB->ScsiCmdLen = xs->cmdlen;
450
451 memcpy(pSRB->CmdBlock, xs->cmd, xs->cmdlen);
452
453 splx (intflag);
454
455 timeout_set(&xs->stimeout, trm_timeout, pSRB);
456
457 intflag = splbio();
458
459 pSRB->SRBFlag |= TRM_ON_WAITING_SRB;
460 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link);
461 trm_StartWaitingSRB(sc);
462
463 if ((xferflags & SCSI_POLL) == 0) {
464 timeout_add(&xs->stimeout, (xs->timeout * hz) / 1000);
465 splx(intflag);
466 return SUCCESSFULLY_QUEUED;
467 }
468
469 while ((--xs->timeout > 0) && ((xs->flags & ITSDONE) == 0)) {
470 trm_Interrupt(sc);
471 DELAY(1000);
472 }
473
474 if (xs->timeout == 0)
475 trm_timeout(pSRB);
476
477 splx(intflag);
478 return COMPLETE;
479 }
480
481 /*
482 * ------------------------------------------------------------
483 * Function : trm_ResetAllDevParam
484 * Purpose :
485 * Inputs : struct trm_softc *
486 * ------------------------------------------------------------
487 */
488 void
trm_ResetAllDevParam(struct trm_softc * sc)489 trm_ResetAllDevParam(struct trm_softc *sc)
490 {
491 struct trm_adapter_nvram *pEEpromBuf;
492 int target, quirks;
493
494 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit];
495
496 for (target = 0; target < TRM_MAX_TARGETS; target++) {
497 if (target == sc->sc_AdaptSCSIID)
498 continue;
499
500 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)
501 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS;
502 else
503 quirks = sc->pDCB[target][0]->sc_link->quirks;
504
505 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks);
506 }
507 }
508
509 /*
510 * ------------------------------------------------------------
511 * Function : trm_ResetDevParam
512 * Purpose :
513 * Inputs :
514 * ------------------------------------------------------------
515 */
516 void
trm_ResetDevParam(struct trm_softc * sc,struct trm_dcb * pDCB,u_int8_t quirks)517 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks)
518 {
519 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit];
520 u_int8_t PeriodIndex;
521 const int target = pDCB->target;
522
523 pDCB->DCBFlag &= TRM_QUIRKS_VALID;
524 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE);
525
526 pDCB->SyncPeriod = 0;
527 pDCB->SyncOffset = 0;
528 pDCB->MaxNegoPeriod = 0;
529
530 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0;
531
532 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0));
533
534 if (((quirks & SDEV_NOWIDE) == 0) &&
535 (pDCB->DevMode & TRM_WIDE) &&
536 ((sc->sc_config & HCC_WIDE_CARD) != 0))
537 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT;
538
539 if (((quirks & SDEV_NOSYNC) == 0) &&
540 ((pDCB->DevMode & TRM_SYNC) != 0)) {
541 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07;
542 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex];
543 }
544
545 if (((quirks & SDEV_NOTAGS) == 0) &&
546 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) &&
547 ((pDCB->DevMode & TRM_DISCONNECT) != 0))
548 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */
549 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING;
550
551 trm_SetXferParams(sc, pDCB, 0);
552 }
553
554 /*
555 * ------------------------------------------------------------
556 * Function : trm_RecoverSRB
557 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs
558 * Inputs : struct trm_softc * -
559 * ------------------------------------------------------------
560 */
561 void
trm_RecoverSRB(struct trm_softc * sc)562 trm_RecoverSRB(struct trm_softc *sc)
563 {
564 struct trm_scsi_req_q *pSRB;
565
566 /* ASSUME we are inside splbio()/splx() */
567
568 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) {
569 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB;
570 TAILQ_REMOVE(&sc->goingSRB, pSRB, link);
571 pSRB->SRBFlag |= TRM_ON_WAITING_SRB;
572 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link);
573 }
574 }
575
576 /*
577 * ------------------------------------------------------------
578 * Function : trm_reset
579 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip).
580 * Inputs :
581 * ------------------------------------------------------------
582 */
583 void
trm_reset(struct trm_softc * sc)584 trm_reset (struct trm_softc *sc)
585 {
586 const bus_space_handle_t ioh = sc->sc_iohandle;
587 const bus_space_tag_t iot = sc->sc_iotag;
588 int i, intflag;
589
590 #ifdef TRM_DEBUG0
591 printf("%s: trm_reset", sc->sc_device.dv_xname);
592 #endif
593
594 intflag = splbio();
595
596 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0);
597 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0);
598
599 trm_ResetSCSIBus(sc);
600 for (i = 0; i < 500; i++)
601 DELAY(1000);
602
603 /*
604 * Enable all SCSI interrupts except EN_SCAM
605 */
606 bus_space_write_1(iot, ioh,
607 TRM_S1040_SCSI_INTEN,
608 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
609 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE));
610 /*
611 * Enable DMA interrupt
612 */
613 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR);
614 /*
615 * Clear DMA FIFO
616 */
617 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO);
618 /*
619 * Clear SCSI FIFO
620 */
621 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
622
623 trm_ResetAllDevParam(sc);
624 trm_GoingSRB_Done(sc);
625 sc->pActiveDCB = NULL;
626
627 /*
628 * RESET_DETECT, RESET_DONE, RESET_DEV
629 */
630 sc->sc_Flag = 0;
631 trm_StartWaitingSRB(sc);
632
633 splx(intflag);
634 }
635
636 /*
637 * ------------------------------------------------------------
638 * Function : trm_timeout
639 * Purpose : Prints a timeout message and aborts the timed out SCSI request
640 * Inputs : void * - A struct trm_scsi_req_q * structure pointer
641 * ------------------------------------------------------------
642 */
643 void
trm_timeout(void * arg1)644 trm_timeout(void *arg1)
645 {
646 struct trm_scsi_req_q *pSRB;
647 struct scsi_xfer *xs;
648 struct trm_softc *sc;
649
650 pSRB = (struct trm_scsi_req_q *)arg1;
651 xs = pSRB->xs;
652
653 if (xs != NULL) {
654 sc = xs->sc_link->adapter_softc;
655 sc_print_addr(xs->sc_link);
656 printf("%s: SCSI OpCode 0x%02x for target %d lun %d timed out\n",
657 sc->sc_device.dv_xname, xs->cmd->opcode,
658 xs->sc_link->target, xs->sc_link->lun);
659 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT;
660 trm_FinishSRB(sc, pSRB);
661 trm_StartWaitingSRB(sc);
662 }
663 #ifdef TRM_DEBUG0
664 else
665 printf("%s: trm_timeout called with xs == NULL\n",
666 sc->sc_device.dv_xname);
667 #endif
668 }
669
670 /*
671 * ------------------------------------------------------------
672 * Function : trm_StartSRB
673 * Purpose : Send the commands in the SRB to the device
674 * Inputs : struct trm_softc * -
675 * struct trm_scsi_req_q * -
676 * Return : 0 - SCSI processor is unoccupied
677 * 1 - SCSI processor is occupied with an SRB
678 * ------------------------------------------------------------
679 */
680 int
trm_StartSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)681 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
682 {
683 const bus_space_handle_t ioh = sc->sc_iohandle;
684 const bus_space_tag_t iot = sc->sc_iotag;
685 struct trm_dcb *pDCB = pSRB->pSRBDCB;
686 u_int32_t tag_mask;
687 u_int8_t tag_id, scsicommand;
688
689 #ifdef TRM_DEBUG0
690 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n",
691 sc->sc_device.dv_xname, sc, pDCB, pSRB);
692 #endif
693 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) != 0)
694 return 1;
695
696 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID);
697 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target);
698 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod);
699 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset);
700
701 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) &&
702 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) {
703 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID;
704 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks);
705 }
706
707 /*
708 * initial phase
709 */
710
711 pSRB->ScsiPhase = PH_BUS_FREE;
712
713 /*
714 * Flush FIFO
715 */
716 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
717
718 sc->MsgCnt = 1;
719 sc->MsgBuf[0] = pDCB->IdentifyMsg;
720 if (((pSRB->xs->flags & SCSI_POLL) != 0) ||
721 (pSRB->CmdBlock[0] == INQUIRY) ||
722 (pSRB->CmdBlock[0] == REQUEST_SENSE))
723 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG;
724
725 scsicommand = SCMD_SEL_ATN;
726 pSRB->SRBState = TRM_START;
727
728 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) {
729 scsicommand = SCMD_SEL_ATNSTOP;
730 pSRB->SRBState = TRM_MSGOUT;
731
732 } else if (((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) &&
733 ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0)) {
734
735 if (pSRB->TagNumber == TRM_NO_TAG) {
736 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1)
737 if ((tag_mask & pDCB->TagMask) == 0) {
738 pDCB->TagMask |= tag_mask;
739 pSRB->TagNumber = tag_id;
740 break;
741 }
742
743 if (tag_id >= 32) {
744 pDCB->DCBFlag |= TRM_QUEUE_FULL;
745 sc->MsgCnt = 0;
746 return 1;
747 }
748 }
749
750 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */
751 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG;
752 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber;
753
754 scsicommand = SCMD_SEL_ATN3;
755 }
756
757 if ((bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT) != 0) {
758 /*
759 * return 1 :
760 * current interrupt status is interrupt disreenable
761 * It's said that SCSI processor has more than one SRB it needs
762 * to do, SCSI processor has been occupied by one SRB.
763 */
764 pSRB->SRBState = TRM_READY;
765 return 1;
766 }
767
768 /*
769 * return 0 :
770 * current interrupt status is interrupt enable
771 * It's said that SCSI processor is unoccupied
772 */
773 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
774 sc->pActiveDCB = pDCB;
775 pDCB->pActiveSRB = pSRB;
776
777 if (sc->MsgCnt > 0) {
778 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]);
779 if (sc->MsgCnt > 1) {
780 DELAY(30);
781 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1);
782 }
783 sc->MsgCnt = 0;
784 }
785
786 /*
787 * it's important for atn stop
788 */
789 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT);
790 /*
791 * SCSI command
792 */
793 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand);
794
795 return 0;
796 }
797
798 /*
799 * ------------------------------------------------------------
800 * Function : trm_Interrupt
801 * Purpose : Catch an interrupt from the adapter
802 * Process pending device interrupts.
803 * Inputs : void * - struct trm_softc * structure pointer
804 * ------------------------------------------------------------
805 */
806 int
trm_Interrupt(void * vsc)807 trm_Interrupt(void *vsc)
808 {
809 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *);
810 struct trm_scsi_req_q *pSRB;
811 bus_space_handle_t ioh;
812 struct trm_softc *sc = (struct trm_softc *)vsc;
813 bus_space_tag_t iot;
814 u_int16_t phase;
815 u_int8_t scsi_status, scsi_intstatus;
816 int intflag;
817
818 intflag = splbio();
819
820 if (sc == NULL) {
821 splx(intflag);
822 return 0;
823 }
824
825 ioh = sc->sc_iohandle;
826 iot = sc->sc_iotag;
827
828 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS);
829 if (!(scsi_status & SCSIINTERRUPT)) {
830 splx(intflag);
831 return 0;
832 }
833 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS);
834
835 #ifdef TRM_DEBUG0
836 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n",
837 sc->sc_device.dv_xname, scsi_status, scsi_intstatus);
838 #endif
839 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0)
840 trm_Disconnect(sc);
841
842 else if ((scsi_intstatus & INT_RESELECTED) != 0)
843 trm_Reselect(sc);
844
845 else if ((scsi_intstatus & INT_SCSIRESET) != 0)
846 trm_ScsiRstDetect(sc);
847
848 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) {
849 pSRB = sc->pActiveDCB->pActiveSRB;
850 /*
851 * software sequential machine
852 */
853 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */
854 /*
855 * 62037 or 62137
856 * call trm_SCSI_phase0[]... "phase entry"
857 * handle every phase before start transfer
858 */
859 stateV = trm_SCSI_phase0[phase];
860 stateV(sc, pSRB, &scsi_status);
861 /*
862 * if any exception occurred
863 * scsi_status will be modified to bus free phase
864 * new scsi_status transfer out from previous stateV
865 */
866 /*
867 * phase:0,1,2,3,4,5,6,7
868 */
869 pSRB->ScsiPhase = scsi_status & PHASEMASK;
870 phase = (u_int16_t) scsi_status & PHASEMASK;
871 /*
872 * call trm_SCSI_phase1[]... "phase entry"
873 * handle every phase do transfer
874 */
875 stateV = trm_SCSI_phase1[phase];
876 stateV(sc, pSRB, &scsi_status);
877
878 } else {
879 splx(intflag);
880 return 0;
881 }
882
883 splx(intflag);
884 return 1;
885 }
886
887 /*
888 * ------------------------------------------------------------
889 * Function : trm_MsgOutPhase0
890 * Purpose : Check the state machine before sending a message out
891 * Inputs : struct trm_softc * -
892 * struct trm_scsi_req_q * -
893 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready
894 * ------------------------------------------------------------
895 */
896 void
trm_MsgOutPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)897 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
898 {
899 switch (pSRB->SRBState) {
900 case TRM_UNEXPECT_RESEL:
901 case TRM_ABORT_SENT:
902 *pscsi_status = PH_BUS_FREE; /* initial phase */
903 break;
904
905 default:
906 break;
907 }
908 }
909
910 /*
911 * ------------------------------------------------------------
912 * Function : trm_MsgOutPhase1
913 * Purpose : Write the message out to the bus
914 * Inputs : struct trm_softc * -
915 * struct trm_scsi_req_q * -
916 * u_int8_t * - unused
917 * ------------------------------------------------------------
918 */
919 void
trm_MsgOutPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)920 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
921 {
922 const bus_space_handle_t ioh = sc->sc_iohandle;
923 const bus_space_tag_t iot = sc->sc_iotag;
924 struct trm_dcb *pDCB = sc->pActiveDCB;
925
926 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
927
928 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) {
929 /*
930 * WIDE DATA TRANSFER REQUEST code (03h)
931 */
932 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE;
933 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO;
934
935 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG;
936 sc->MsgBuf[1] = MSG_EXTENDED;
937 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN;
938 sc->MsgBuf[3] = MSG_EXT_WDTR;
939
940 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0)
941 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT;
942 else
943 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT;
944
945 sc->MsgCnt = 5;
946
947 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) {
948
949 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE;
950 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO;
951
952 sc->MsgCnt = 0;
953
954 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0)
955 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG;
956
957 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED;
958 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN;
959 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR;
960 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod;
961
962 if (pDCB->MaxNegoPeriod > 0)
963 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET;
964 else
965 sc->MsgBuf[sc->MsgCnt++] = 0;
966 }
967
968 if (sc->MsgCnt > 0) {
969 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt);
970 if (sc->MsgBuf[0] == MSG_ABORT)
971 pSRB->SRBState = TRM_ABORT_SENT;
972 sc->MsgCnt = 0;
973 }
974 /*
975 * it's important for atn stop
976 */
977 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
978 /*
979 * Transfer information out
980 */
981 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT);
982 }
983
984 /*
985 * ------------------------------------------------------------
986 * Function : trm_CommandPhase1
987 * Purpose : Send commands to bus
988 * Inputs :
989 * ------------------------------------------------------------
990 */
991 void
trm_CommandPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)992 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
993 {
994 const bus_space_handle_t ioh = sc->sc_iohandle;
995 const bus_space_tag_t iot = sc->sc_iotag;
996
997 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO);
998
999 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen);
1000
1001 pSRB->SRBState = TRM_COMMAND;
1002 /*
1003 * it's important for atn stop
1004 */
1005 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1006 /*
1007 * Transfer information out
1008 */
1009 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT);
1010 }
1011
1012 /*
1013 * ------------------------------------------------------------
1014 * Function : trm_DataOutPhase0
1015 * Purpose : Ready for Data Out, clear FIFO
1016 * Inputs : u_int8_t * - SCSI status, used but not set
1017 * ------------------------------------------------------------
1018 */
1019 void
trm_DataOutPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1020 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1021 {
1022 const bus_space_handle_t ioh = sc->sc_iohandle;
1023 const bus_space_tag_t iot = sc->sc_iotag;
1024 struct SGentry *pseg;
1025 struct trm_dcb *pDCB;
1026 u_int32_t dLeftCounter, TempSRBXferredLength;
1027 u_int16_t scsi_status;
1028 u_int8_t TempDMAstatus, SGIndexTemp;
1029
1030 dLeftCounter = 0;
1031
1032 pDCB = pSRB->pSRBDCB;
1033 scsi_status = *pscsi_status;
1034
1035 if (pSRB->SRBState != TRM_XFERPAD) {
1036 if ((scsi_status & PARITYERROR) != 0)
1037 pSRB->SRBFlag |= TRM_PARITY_ERROR;
1038 if ((scsi_status & SCSIXFERDONE) == 0) {
1039 /*
1040 * when data transfer from DMA FIFO to SCSI FIFO
1041 * if there was some data left in SCSI FIFO
1042 */
1043 dLeftCounter = (u_int32_t)(bus_space_read_1(
1044 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F);
1045 if (pDCB->SyncPeriod & WIDE_SYNC) {
1046 /*
1047 * if WIDE scsi SCSI FIFOCNT unit is word
1048 * so need to * 2
1049 */
1050 dLeftCounter <<= 1;
1051 }
1052 }
1053 /*
1054 * calculate all the residue data that not yet transferred
1055 * SCSI transfer counter + left in SCSI FIFO data
1056 *
1057 * .....TRM_S1040_SCSI_COUNTER (24bits)
1058 * The counter always decrement by one for every SCSI byte
1059 * transfer.
1060 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits)
1061 * The counter is SCSI FIFO offset counter
1062 */
1063 dLeftCounter += bus_space_read_4(iot, ioh,
1064 TRM_S1040_SCSI_COUNTER);
1065 if (dLeftCounter == 1) {
1066 dLeftCounter = 0;
1067 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL,
1068 DO_CLRFIFO);
1069 }
1070 if (dLeftCounter == 0 ||
1071 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) {
1072 TempDMAstatus = bus_space_read_1(iot,
1073 ioh, TRM_S1040_DMA_STATUS);
1074 while ((TempDMAstatus & DMAXFERCOMP) == 0) {
1075 TempDMAstatus = bus_space_read_1(iot,
1076 ioh, TRM_S1040_DMA_STATUS);
1077 }
1078 pSRB->SRBTotalXferLength = 0;
1079 } else {
1080 /*
1081 * Update SG list
1082 */
1083 /*
1084 * if transfer not yet complete
1085 * there were some data residue in SCSI FIFO or
1086 * SCSI transfer counter not empty
1087 */
1088 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1089 /*
1090 * data that had transferred length
1091 */
1092 TempSRBXferredLength = pSRB->SRBTotalXferLength
1093 - dLeftCounter;
1094 /*
1095 * next time to be transferred length
1096 */
1097 pSRB->SRBTotalXferLength = dLeftCounter;
1098 /*
1099 * parsing from last time disconnect SRBSGIndex
1100 */
1101 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex];
1102 for (SGIndexTemp = pSRB->SRBSGIndex;
1103 SGIndexTemp < pSRB->SRBSGCount;
1104 SGIndexTemp++) {
1105 /*
1106 * find last time which SG transfer be
1107 * disconnect
1108 */
1109 if (TempSRBXferredLength >= pseg->length)
1110 TempSRBXferredLength -= pseg->length;
1111 else {
1112 /*
1113 * update last time disconnected
1114 * SG list
1115 */
1116 /*
1117 * residue data length
1118 */
1119 pseg->length -=
1120 TempSRBXferredLength;
1121 /*
1122 * residue data pointer
1123 */
1124 pseg->address +=
1125 TempSRBXferredLength;
1126 pSRB->SRBSGIndex = SGIndexTemp;
1127 break;
1128 }
1129 pseg++;
1130 }
1131 }
1132 }
1133 }
1134 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER);
1135 }
1136
1137 /*
1138 * ------------------------------------------------------------
1139 * Function : trm_DataOutPhase1
1140 * Purpose : Transfers data out, calls trm_DataIO_transfer
1141 * Inputs :
1142 * ------------------------------------------------------------
1143 */
1144 void
trm_DataOutPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1145 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1146 {
1147 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT);
1148 }
1149
1150 /*
1151 * ------------------------------------------------------------
1152 * Function : trm_DataInPhase0
1153 * Purpose : Prepare for reading data in from bus
1154 * Inputs :
1155 * ------------------------------------------------------------
1156 */
1157 void
trm_DataInPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1158 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1159 {
1160 const bus_space_handle_t ioh = sc->sc_iohandle;
1161 const bus_space_tag_t iot = sc->sc_iotag;
1162 struct SGentry *pseg;
1163 u_int32_t TempSRBXferredLength, dLeftCounter;
1164 u_int16_t scsi_status;
1165 u_int8_t SGIndexTemp;
1166
1167 dLeftCounter = 0;
1168
1169 scsi_status = *pscsi_status;
1170 if (pSRB->SRBState != TRM_XFERPAD) {
1171 if ((scsi_status & PARITYERROR) != 0)
1172 pSRB->SRBFlag |= TRM_PARITY_ERROR;
1173 dLeftCounter += bus_space_read_4(iot, ioh,
1174 TRM_S1040_SCSI_COUNTER);
1175 if (dLeftCounter == 0 ||
1176 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) {
1177 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0)
1178 ;
1179 pSRB->SRBTotalXferLength = 0;
1180 } else {
1181 /*
1182 * phase changed
1183 *
1184 * parsing the case:
1185 * when a transfer not yet complete
1186 * but be disconnected by uper layer
1187 * if transfer not yet complete
1188 * there were some data residue in SCSI FIFO or
1189 * SCSI transfer counter not empty
1190 */
1191 if (pSRB->SRBTotalXferLength != dLeftCounter) {
1192 /*
1193 * data that had transferred length
1194 */
1195 TempSRBXferredLength = pSRB->SRBTotalXferLength
1196 - dLeftCounter;
1197 /*
1198 * next time to be transferred length
1199 */
1200 pSRB->SRBTotalXferLength = dLeftCounter;
1201 /*
1202 * parsing from last time disconnect SRBSGIndex
1203 */
1204 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex];
1205 for (SGIndexTemp = pSRB->SRBSGIndex;
1206 SGIndexTemp < pSRB->SRBSGCount;
1207 SGIndexTemp++) {
1208 /*
1209 * find last time which SG transfer be
1210 * disconnect
1211 */
1212 if (TempSRBXferredLength >=
1213 pseg->length) {
1214 TempSRBXferredLength -= pseg->length;
1215 } else {
1216 /*
1217 * update last time disconnected
1218 * SG list
1219 *
1220 * residue data length
1221 */
1222 pseg->length -= TempSRBXferredLength;
1223 /*
1224 * residue data pointer
1225 */
1226 pseg->address += TempSRBXferredLength;
1227 pSRB->SRBSGIndex = SGIndexTemp;
1228 break;
1229 }
1230 pseg++;
1231 }
1232 }
1233 }
1234 }
1235 }
1236
1237 /*
1238 * ------------------------------------------------------------
1239 * Function : trm_DataInPhase1
1240 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer
1241 * Inputs :
1242 * ------------------------------------------------------------
1243 */
1244 void
trm_DataInPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1245 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1246 {
1247 trm_DataIO_transfer(sc, pSRB, XFERDATAIN);
1248 }
1249
1250 /*
1251 * ------------------------------------------------------------
1252 * Function : trm_DataIO_transfer
1253 * Purpose :
1254 * Inputs :
1255 * ------------------------------------------------------------
1256 */
1257 void
trm_DataIO_transfer(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int16_t ioDir)1258 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir)
1259 {
1260 const bus_space_handle_t ioh = sc->sc_iohandle;
1261 const bus_space_tag_t iot = sc->sc_iotag;
1262 struct trm_dcb *pDCB = pSRB->pSRBDCB;
1263 u_int8_t bval;
1264
1265 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) {
1266 if (pSRB->SRBTotalXferLength != 0) {
1267 /*
1268 * load what physical address of Scatter/Gather list
1269 * table want to be transfer
1270 */
1271 pSRB->SRBState = TRM_DATA_XFER;
1272 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0);
1273 bus_space_write_4(iot, ioh,
1274 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr +
1275 ((u_int32_t)pSRB->SRBSGIndex << 3)));
1276 /*
1277 * load how many bytes in the Scatter/Gather list table
1278 */
1279 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT,
1280 ((u_int32_t)(pSRB->SRBSGCount -
1281 pSRB->SRBSGIndex) << 3));
1282 /*
1283 * load total transfer length (24bits,
1284 * pSRB->SRBTotalXferLength) max value 16Mbyte
1285 */
1286 bus_space_write_4(iot, ioh,
1287 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength);
1288 /*
1289 * Start DMA transfer
1290 */
1291 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir);
1292 /* bus_space_write_2(iot, ioh,
1293 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/
1294 /*
1295 * Set the transfer bus and direction
1296 */
1297 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN;
1298 } else {
1299 /*
1300 * xfer pad
1301 */
1302 if (pSRB->SRBSGCount)
1303 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN;
1304
1305 if (pDCB->SyncPeriod & WIDE_SYNC) {
1306 bus_space_write_4(iot, ioh,
1307 TRM_S1040_SCSI_COUNTER, 2);
1308 } else {
1309 bus_space_write_4(iot, ioh,
1310 TRM_S1040_SCSI_COUNTER, 1);
1311 }
1312
1313 if (ioDir == XFERDATAOUT) {
1314 bus_space_write_2(iot,
1315 ioh, TRM_S1040_SCSI_FIFO, 0);
1316 } else {
1317 bus_space_read_2(iot,
1318 ioh, TRM_S1040_SCSI_FIFO);
1319 }
1320 pSRB->SRBState = TRM_XFERPAD;
1321 /*
1322 * Set the transfer bus and direction
1323 */
1324 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN;
1325 }
1326 /*
1327 * it's important for atn stop
1328 */
1329 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1330 /*
1331 * Tell the bus to do the transfer
1332 */
1333 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval);
1334 }
1335 }
1336
1337 /*
1338 * ------------------------------------------------------------
1339 * Function : trm_StatusPhase0
1340 * Purpose : Update Target Status with data from SCSI FIFO
1341 * Inputs : u_int8_t * - Set to PH_BUS_FREE
1342 * ------------------------------------------------------------
1343 */
1344 void
trm_StatusPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1345 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1346 {
1347 const bus_space_handle_t ioh = sc->sc_iohandle;
1348 const bus_space_tag_t iot = sc->sc_iotag;
1349
1350 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO);
1351
1352 pSRB->SRBState = TRM_COMPLETED;
1353 /*
1354 * initial phase
1355 */
1356 *pscsi_status = PH_BUS_FREE;
1357 /*
1358 * it's important for atn stop
1359 */
1360 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1361 /*
1362 * Tell bus that the message was accepted
1363 */
1364 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT);
1365 }
1366
1367 /*
1368 * ------------------------------------------------------------
1369 * Function : trm_StatusPhase1
1370 * Purpose : Clear FIFO of DMA and SCSI
1371 * Inputs :
1372 * ------------------------------------------------------------
1373 */
1374 void
trm_StatusPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1375 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1376 {
1377 const bus_space_handle_t ioh = sc->sc_iohandle;
1378 const bus_space_tag_t iot = sc->sc_iotag;
1379
1380 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) {
1381 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40)
1382 == 0) {
1383 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL,
1384 DO_CLRFIFO);
1385 }
1386 if ((bus_space_read_2(iot, ioh,
1387 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) {
1388 bus_space_write_1(iot, ioh,
1389 TRM_S1040_DMA_CONTROL, CLRXFIFO);
1390 }
1391 } else {
1392 if ((bus_space_read_2(iot, ioh,
1393 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) {
1394 bus_space_write_1(iot, ioh,
1395 TRM_S1040_DMA_CONTROL, CLRXFIFO);
1396 }
1397 if ((bus_space_read_1(iot, ioh,
1398 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) {
1399 bus_space_write_2(iot, ioh,
1400 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
1401 }
1402 }
1403 pSRB->SRBState = TRM_STATUS;
1404 /*
1405 * it's important for atn stop
1406 */
1407 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1408 /*
1409 * Tell the bus that the command is complete
1410 */
1411 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP);
1412 }
1413
1414 /*
1415 * ------------------------------------------------------------
1416 * Function : trm_MsgInPhase0
1417 * Purpose :
1418 * Inputs :
1419 *
1420 * extended message codes:
1421 * code description
1422 * ---- -----------
1423 * 02h Reserved
1424 * 00h MODIFY DATA POINTER
1425 * 01h SYNCHRONOUS DATA TRANSFER REQUEST
1426 * 03h WIDE DATA TRANSFER REQUEST
1427 * 04h - 7Fh Reserved
1428 * 80h - FFh Vendor specific
1429 *
1430 * ------------------------------------------------------------
1431 */
1432 void
trm_MsgInPhase0(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1433 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1434 {
1435 const bus_space_handle_t ioh = sc->sc_iohandle;
1436 const bus_space_tag_t iot = sc->sc_iotag;
1437 struct trm_dcb *pDCB;
1438 u_int8_t message_in_code, bIndex, message_in_tag_id;
1439
1440 pDCB = sc->pActiveDCB;
1441
1442 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO);
1443
1444 if (pSRB->SRBState != TRM_EXTEND_MSGIN) {
1445 switch (message_in_code) {
1446 case MSG_DISCONNECT:
1447 pSRB->SRBState = TRM_DISCONNECTED;
1448 break;
1449
1450 case MSG_EXTENDED:
1451 case MSG_SIMPLE_Q_TAG:
1452 case MSG_HEAD_OF_Q_TAG:
1453 case MSG_ORDERED_Q_TAG:
1454 pSRB->SRBState = TRM_EXTEND_MSGIN;
1455 /*
1456 * extended message (01h)
1457 */
1458 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf));
1459 sc->MsgBuf[0] = message_in_code;
1460 sc->MsgCnt = 1;
1461 /*
1462 * extended message length (n)
1463 */
1464 break;
1465
1466 case MSG_MESSAGE_REJECT:
1467 /*
1468 * Reject message
1469 */
1470 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) {
1471 /*
1472 * do wide nego reject
1473 */
1474 pDCB = pSRB->pSRBDCB;
1475
1476 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO;
1477 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE;
1478
1479 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) {
1480 /*
1481 * Set ATN, in case ATN was clear
1482 */
1483 pSRB->SRBState = TRM_MSGOUT;
1484 bus_space_write_2(iot, ioh,
1485 TRM_S1040_SCSI_CONTROL, DO_SETATN);
1486 } else {
1487 /*
1488 * Clear ATN
1489 */
1490 bus_space_write_2(iot, ioh,
1491 TRM_S1040_SCSI_CONTROL, DO_CLRATN);
1492 }
1493
1494 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) {
1495 /*
1496 * do sync nego reject
1497 */
1498 pDCB = pSRB->pSRBDCB;
1499
1500 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO;
1501
1502 pDCB->SyncPeriod = 0;
1503 pDCB->SyncOffset = 0;
1504
1505 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN);
1506 goto re_prog;
1507 }
1508 break;
1509
1510 case MSG_IGN_WIDE_RESIDUE:
1511 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1);
1512 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO);
1513 break;
1514
1515 default:
1516 break;
1517 }
1518
1519 } else {
1520
1521 /*
1522 * We are collecting an extended message. Save the latest byte and then
1523 * check to see if the message is complete. If so, process it.
1524 */
1525 sc->MsgBuf[sc->MsgCnt++] = message_in_code;
1526 #ifdef TRM_DEBUG0
1527 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n",
1528 sc->sc_device.dv_xname,
1529 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] );
1530 #endif
1531 switch (sc->MsgBuf[0]) {
1532 case MSG_SIMPLE_Q_TAG:
1533 case MSG_HEAD_OF_Q_TAG:
1534 case MSG_ORDERED_Q_TAG:
1535 if (sc->MsgCnt == 2) {
1536 pSRB->SRBState = TRM_FREE;
1537 message_in_tag_id = sc->MsgBuf[1];
1538 sc->MsgCnt = 0;
1539 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) {
1540 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id))
1541 break;
1542 }
1543 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) {
1544 pDCB->pActiveSRB = pSRB;
1545 pSRB->SRBState = TRM_DATA_XFER;
1546 } else {
1547 pSRB = &sc->SRB[0];
1548 pSRB->SRBState = TRM_UNEXPECT_RESEL;
1549 pDCB->pActiveSRB = pSRB;
1550 trm_EnableMsgOut(sc, MSG_ABORT_TAG);
1551 }
1552 }
1553 break;
1554
1555 case MSG_EXTENDED:
1556 /* TODO XXXX: Correctly handling target initiated negotiations? */
1557 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) {
1558 /*
1559 * ======================================
1560 * WIDE DATA TRANSFER REQUEST
1561 * ======================================
1562 * byte 0 : Extended message (01h)
1563 * byte 1 : Extended message length (02h)
1564 * byte 2 : WIDE DATA TRANSFER code (03h)
1565 * byte 3 : Transfer width exponent
1566 */
1567
1568 pSRB->SRBState = TRM_FREE;
1569 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO);
1570
1571 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN)
1572 goto reject_offer;
1573
1574 switch (sc->MsgBuf[3]) {
1575 case MSG_EXT_WDTR_BUS_32_BIT:
1576 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0)
1577 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT;
1578 else
1579 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT;
1580 break;
1581
1582 case MSG_EXT_WDTR_BUS_16_BIT:
1583 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) {
1584 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT;
1585 break;
1586 }
1587 pDCB->SyncPeriod |= WIDE_SYNC;
1588 /* FALL THROUGH == ACCEPT OFFER */
1589
1590 case MSG_EXT_WDTR_BUS_8_BIT:
1591 pSRB->SRBState = TRM_MSGOUT;
1592 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE);
1593
1594 if (pDCB->MaxNegoPeriod == 0) {
1595 pDCB->SyncPeriod = 0;
1596 pDCB->SyncOffset = 0;
1597 goto re_prog;
1598 }
1599 break;
1600
1601 default:
1602 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE;
1603 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE;
1604 reject_offer:
1605 sc->MsgCnt = 1;
1606 sc->MsgBuf[0] = MSG_MESSAGE_REJECT;
1607 break;
1608 }
1609
1610 /* Echo accepted offer, or send revised offer */
1611 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN);
1612
1613 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) {
1614 /*
1615 * =================================
1616 * SYNCHRONOUS DATA TRANSFER REQUEST
1617 * =================================
1618 * byte 0 : Extended message (01h)
1619 * byte 1 : Extended message length (03)
1620 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h)
1621 * byte 3 : Transfer period factor
1622 * byte 4 : REQ/ACK offset
1623 */
1624
1625 pSRB->SRBState = TRM_FREE;
1626 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO);
1627
1628 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN)
1629 goto reject_offer;
1630
1631 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) {
1632 /*
1633 * Asynchronous transfers
1634 */
1635 pDCB->SyncPeriod = 0;
1636 pDCB->SyncOffset = 0;
1637
1638 } else {
1639 /*
1640 * Synchronous transfers
1641 */
1642 /*
1643 * REQ/ACK offset
1644 */
1645 pDCB->SyncOffset = sc->MsgBuf[4];
1646
1647 for (bIndex = 0; bIndex < 7; bIndex++)
1648 if (sc->MsgBuf[3] <= trm_clock_period[bIndex])
1649 break;
1650
1651 pDCB->SyncPeriod |= (bIndex | ALT_SYNC);
1652 }
1653
1654 re_prog: /*
1655 * program SCSI control register
1656 */
1657 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod);
1658 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset);
1659
1660 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID));
1661 }
1662 break;
1663
1664 default:
1665 break;
1666 }
1667 }
1668
1669 /*
1670 * initial phase
1671 */
1672 *pscsi_status = PH_BUS_FREE;
1673 /*
1674 * it's important for atn stop
1675 */
1676 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1677 /*
1678 * Tell bus that the message was accepted
1679 */
1680 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT);
1681 }
1682
1683 /*
1684 * ------------------------------------------------------------
1685 * Function : trm_MsgInPhase1
1686 * Purpose : Clear the FIFO
1687 * Inputs :
1688 * ------------------------------------------------------------
1689 */
1690 void
trm_MsgInPhase1(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1691 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1692 {
1693 const bus_space_handle_t ioh = sc->sc_iohandle;
1694 const bus_space_tag_t iot = sc->sc_iotag;
1695
1696 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
1697 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1);
1698
1699 /*
1700 * it's important for atn stop
1701 */
1702 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1703 /*
1704 * SCSI command
1705 */
1706 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN);
1707 }
1708
1709 /*
1710 * ------------------------------------------------------------
1711 * Function : trm_Nop
1712 * Purpose : EMPTY
1713 * Inputs :
1714 * ------------------------------------------------------------
1715 */
1716 void
trm_Nop(struct trm_softc * sc,struct trm_scsi_req_q * pSRB,u_int8_t * pscsi_status)1717 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status)
1718 {
1719 }
1720
1721 /*
1722 * ------------------------------------------------------------
1723 * Function : trm_SetXferParams
1724 * Purpose : Set the Sync period, offset and mode for each device that has
1725 * the same target as the given one (struct trm_dcb *)
1726 * Inputs :
1727 * ------------------------------------------------------------
1728 */
1729 void
trm_SetXferParams(struct trm_softc * sc,struct trm_dcb * pDCB,int print_info)1730 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info)
1731 {
1732 struct trm_dcb *pDCBTemp;
1733 int lun, target;
1734
1735 /*
1736 * set all lun device's period, offset
1737 */
1738 #ifdef TRM_DEBUG0
1739 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname);
1740 #endif
1741
1742 target = pDCB->target;
1743 for(lun = 0; lun < TRM_MAX_LUNS; lun++) {
1744 pDCBTemp = sc->pDCB[target][lun];
1745 if (pDCBTemp != NULL) {
1746 pDCBTemp->DevMode = pDCB->DevMode;
1747 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod;
1748 pDCBTemp->SyncPeriod = pDCB->SyncPeriod;
1749 pDCBTemp->SyncOffset = pDCB->SyncOffset;
1750 pDCBTemp->DCBFlag = pDCB->DCBFlag;
1751 }
1752 }
1753
1754 if (print_info)
1755 trm_print_info(sc, pDCB);
1756 }
1757
1758 /*
1759 * ------------------------------------------------------------
1760 * Function : trm_Disconnect
1761 * Purpose :
1762 * Inputs :
1763 *
1764 * ---SCSI bus phase
1765 * PH_DATA_OUT 0x00 Data out phase
1766 * PH_DATA_IN 0x01 Data in phase
1767 * PH_COMMAND 0x02 Command phase
1768 * PH_STATUS 0x03 Status phase
1769 * PH_BUS_FREE 0x04 Invalid phase used as bus free
1770 * PH_BUS_FREE 0x05 Invalid phase used as bus free
1771 * PH_MSG_OUT 0x06 Message out phase
1772 * PH_MSG_IN 0x07 Message in phase
1773 * ------------------------------------------------------------
1774 */
1775 void
trm_Disconnect(struct trm_softc * sc)1776 trm_Disconnect(struct trm_softc *sc)
1777 {
1778 const bus_space_handle_t ioh = sc->sc_iohandle;
1779 struct trm_scsi_req_q *pSRB, *pNextSRB;
1780 const bus_space_tag_t iot = sc->sc_iotag;
1781 struct trm_dcb *pDCB;
1782 int j;
1783
1784 #ifdef TRM_DEBUG0
1785 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname);
1786 #endif
1787
1788 pDCB = sc->pActiveDCB;
1789 if (pDCB == NULL) {
1790 /* TODO: Why use a loop? Why not use DELAY(400)? */
1791 for(j = 400; j > 0; --j)
1792 DELAY(1); /* 1 msec */
1793 bus_space_write_2(iot, ioh,
1794 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT));
1795 return;
1796 }
1797
1798 pSRB = pDCB->pActiveSRB;
1799 sc->pActiveDCB = NULL;
1800 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
1801 bus_space_write_2(iot, ioh,
1802 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT));
1803 DELAY(100);
1804
1805 switch (pSRB->SRBState) {
1806 case TRM_UNEXPECT_RESEL:
1807 pSRB->SRBState = TRM_FREE;
1808 break;
1809
1810 case TRM_ABORT_SENT:
1811 pSRB = TAILQ_FIRST(&sc->goingSRB);
1812 while (pSRB != NULL) {
1813 /*
1814 * Need to save pNextSRB because trm_FinishSRB() puts
1815 * pSRB in freeSRB queue, and thus its links no longer
1816 * point to members of the goingSRB queue. This is why
1817 * TAILQ_FOREACH() will not work for this traversal.
1818 */
1819 pNextSRB = TAILQ_NEXT(pSRB, link);
1820 if (pSRB->pSRBDCB == pDCB) {
1821 /* TODO XXXX: Is TIMED_OUT the best state to report? */
1822 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT;
1823 trm_FinishSRB(sc, pSRB);
1824 }
1825 pSRB = pNextSRB;
1826 }
1827 break;
1828
1829 case TRM_START:
1830 case TRM_MSGOUT:
1831 /*
1832 * Selection time out
1833 */
1834 /* If not polling just keep trying until xs->stimeout expires */
1835 if ((pSRB->xs->flags & SCSI_POLL) == 0) {
1836 trm_RewaitSRB(sc, pSRB);
1837 } else {
1838 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT;
1839 goto disc1;
1840 }
1841 break;
1842
1843 case TRM_COMPLETED:
1844 disc1:
1845 /*
1846 * TRM_COMPLETED - remove id from mask of active tags
1847 */
1848 pDCB->pActiveSRB = NULL;
1849 trm_FinishSRB(sc, pSRB);
1850 break;
1851
1852 default:
1853 break;
1854 }
1855
1856 trm_StartWaitingSRB(sc);
1857 }
1858
1859 /*
1860 * ------------------------------------------------------------
1861 * Function : trm_Reselect
1862 * Purpose :
1863 * Inputs :
1864 * ------------------------------------------------------------
1865 */
1866 void
trm_Reselect(struct trm_softc * sc)1867 trm_Reselect(struct trm_softc *sc)
1868 {
1869 const bus_space_handle_t ioh = sc->sc_iohandle;
1870 const bus_space_tag_t iot = sc->sc_iotag;
1871 struct trm_scsi_req_q *pSRB;
1872 struct trm_dcb *pDCB;
1873 u_int16_t RselTarLunId;
1874 u_int8_t target, lun;
1875
1876 #ifdef TRM_DEBUG0
1877 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname);
1878 #endif
1879
1880 pDCB = sc->pActiveDCB;
1881 if (pDCB != NULL) {
1882 /*
1883 * Arbitration lost but Reselection win
1884 */
1885 pSRB = pDCB->pActiveSRB;
1886 trm_RewaitSRB(sc, pSRB);
1887 }
1888
1889 /*
1890 * Read Reselected Target Id and LUN
1891 */
1892 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF;
1893 /* TODO XXXX: Make endian independent! */
1894 target = RselTarLunId & 0xff;
1895 lun = (RselTarLunId >> 8) & 0xff;
1896
1897 #ifdef TRM_DEBUG0
1898 printf("%s: reselect - target = %d, lun = %d\n",
1899 sc->sc_device.dv_xname, target, lun);
1900 #endif
1901
1902 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS))
1903 pDCB = sc->pDCB[target][lun];
1904 else
1905 pDCB = NULL;
1906
1907 if (pDCB == NULL)
1908 printf("%s: reselect - target = %d, lun = %d not found\n",
1909 sc->sc_device.dv_xname, target, lun);
1910
1911 sc->pActiveDCB = pDCB;
1912
1913 /* TODO XXXX: This will crash if pDCB is ever NULL */
1914 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) {
1915 pSRB = &sc->SRB[0];
1916 pDCB->pActiveSRB = pSRB;
1917 } else {
1918 pSRB = pDCB->pActiveSRB;
1919 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) {
1920 /*
1921 * abort command
1922 */
1923 pSRB = &sc->SRB[0];
1924 pSRB->SRBState = TRM_UNEXPECT_RESEL;
1925 pDCB->pActiveSRB = pSRB;
1926 trm_EnableMsgOut(sc, MSG_ABORT);
1927 } else
1928 pSRB->SRBState = TRM_DATA_XFER;
1929 }
1930 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
1931
1932 /*
1933 * Program HA ID, target ID, period and offset
1934 */
1935 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target);
1936 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID);
1937 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod);
1938 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset);
1939
1940 /*
1941 * it's important for atn stop
1942 */
1943 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH);
1944 DELAY(30);
1945
1946 /*
1947 * SCSI command
1948 * to rls the /ACK signal
1949 */
1950 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT);
1951 }
1952
1953 /*
1954 * ------------------------------------------------------------
1955 * Function : trm_FinishSRB
1956 * Purpose : Complete execution of a SCSI command
1957 * Signal completion to the generic SCSI driver
1958 * Inputs :
1959 * ------------------------------------------------------------
1960 */
1961 void
trm_FinishSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)1962 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
1963 {
1964 struct scsi_inquiry_data *ptr;
1965 struct scsi_sense_data *s1, *s2;
1966 struct scsi_xfer *xs = pSRB->xs;
1967 struct trm_dcb *pDCB = pSRB->pSRBDCB;
1968 int target, lun;
1969
1970 #ifdef TRM_DEBUG0
1971 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n",
1972 sc->sc_device.dv_xname, sc, pSRB);
1973 #endif
1974 pDCB->DCBFlag &= ~TRM_QUEUE_FULL;
1975
1976 if (xs == NULL) {
1977 trm_ReleaseSRB(sc, pSRB);
1978 return;
1979 }
1980
1981 timeout_del(&xs->stimeout);
1982
1983 xs->status = pSRB->TargetStatus;
1984
1985 switch (xs->status) {
1986 case SCSI_INTERM_COND_MET:
1987 case SCSI_COND_MET:
1988 case SCSI_INTERM:
1989 case SCSI_OK:
1990 switch (pSRB->AdaptStatus) {
1991 case TRM_STATUS_GOOD:
1992 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) {
1993 #ifdef TRM_DEBUG0
1994 printf("%s: trm_FinishSRB. TRM_PARITY_ERROR\n",
1995 sc->sc_device.dv_xname);
1996 #endif
1997 xs->error = XS_DRIVER_STUFFUP;
1998
1999 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) {
2000 xs->error = XS_TIMEOUT;
2001
2002 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) {
2003 s1 = &pSRB->scsisense;
2004 s2 = &xs->sense;
2005
2006 *s2 = *s1;
2007
2008 xs->status = SCSI_CHECK;
2009 xs->error = XS_SENSE;
2010
2011 } else
2012 xs->error = XS_NOERROR;
2013 break;
2014
2015 case TRM_OVER_UNDER_RUN:
2016 #ifdef TRM_DEBUG0
2017 printf("%s: trm_FinishSRB. TRM_OVER_UNDER_RUN\n",
2018 sc->sc_device.dv_xname);
2019 #endif
2020 xs->error = XS_DRIVER_STUFFUP;
2021 break;
2022
2023 default:
2024 #ifdef TRM_DEBUG0
2025 printf("%s: trm_FinishSRB. AdaptStatus Error = 0x%02x\n",
2026 sc->sc_device.dv_xname, pSRB->AdaptStatus);
2027 #endif
2028 xs->error = XS_DRIVER_STUFFUP;
2029 break;
2030 }
2031 break;
2032
2033 case SCSI_TERMINATED:
2034 case SCSI_ACA_ACTIVE:
2035 case SCSI_CHECK:
2036 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0)
2037 xs->error = XS_DRIVER_STUFFUP;
2038 else {
2039 trm_RequestSense(sc, pSRB);
2040 return;
2041 }
2042 break;
2043
2044 case SCSI_QUEUE_FULL:
2045 /* this says no more until someone completes */
2046 pDCB->DCBFlag |= TRM_QUEUE_FULL;
2047 trm_RewaitSRB(sc, pSRB);
2048 return;
2049
2050 case SCSI_RESV_CONFLICT:
2051 case SCSI_BUSY:
2052 xs->error = XS_BUSY;
2053 break;
2054
2055 case TRM_SCSI_UNEXP_BUS_FREE:
2056 xs->status = SCSI_OK;
2057 xs->error = XS_DRIVER_STUFFUP;
2058 break;
2059
2060 case TRM_SCSI_BUS_RST_DETECTED:
2061 xs->status = SCSI_OK;
2062 xs->error = XS_RESET;
2063 break;
2064
2065 case TRM_SCSI_SELECT_TIMEOUT:
2066 xs->status = SCSI_OK;
2067 xs->error = XS_SELTIMEOUT;
2068 break;
2069
2070 default:
2071 xs->error = XS_DRIVER_STUFFUP;
2072 break;
2073 }
2074
2075 target = xs->sc_link->target;
2076 lun = xs->sc_link->lun;
2077
2078 if ((xs->flags & SCSI_POLL) != 0) {
2079
2080 if (xs->cmd->opcode == INQUIRY) {
2081
2082 ptr = (struct scsi_inquiry_data *) xs->data;
2083
2084 if ((xs->error != XS_NOERROR) ||
2085 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) {
2086 #ifdef TRM_DEBUG0
2087 printf("%s: trm_FinishSRB NO Device:target= %d,lun= %d\n",
2088 sc->sc_device.dv_xname, target, lun);
2089 #endif
2090 free(pDCB, M_DEVBUF);
2091 sc->pDCB[target][lun] = NULL;
2092 pDCB = NULL;
2093
2094 } else
2095 pDCB->sc_link = xs->sc_link;
2096 }
2097 }
2098
2099 trm_ReleaseSRB(sc, pSRB);
2100
2101 xs->flags |= ITSDONE;
2102
2103 /*
2104 * Notify cmd done
2105 */
2106 #ifdef TRM_DEBUG0
2107 if ((xs->error != 0) || (xs->status != 0) || ((xs->flags & SCSI_POLL) != 0))
2108 printf("%s: trm_FinishSRB. %d/%d xs->cmd->opcode = 0x%02x, xs->error = %d, xs->status = %d\n",
2109 sc->sc_device.dv_xname, target, lun, xs->cmd->opcode, xs->error, xs->status);
2110 #endif
2111
2112 scsi_done(xs);
2113 }
2114
2115 /*
2116 * ------------------------------------------------------------
2117 * Function : trm_ReleaseSRB
2118 * Purpose :
2119 * Inputs :
2120 * ------------------------------------------------------------
2121 */
2122 void
trm_ReleaseSRB(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)2123 trm_ReleaseSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
2124 {
2125 struct scsi_xfer *xs = pSRB->xs;
2126 int intflag;
2127
2128 intflag = splbio();
2129
2130 if (pSRB->TagNumber != TRM_NO_TAG) {
2131 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber);
2132 pSRB->TagNumber = TRM_NO_TAG;
2133 }
2134
2135 if (xs != NULL) {
2136 timeout_del(&xs->stimeout);
2137
2138 if (xs->datalen != 0) {
2139 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer,
2140 0, pSRB->dmamapxfer->dm_mapsize,
2141 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD :
2142 BUS_DMASYNC_POSTWRITE);
2143 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer);
2144 }
2145 }
2146
2147 /* SRB may have started & finished, or be waiting and timed out */
2148 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) {
2149 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB;
2150 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link);
2151 }
2152 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) {
2153 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB;
2154 TAILQ_REMOVE(&sc->goingSRB, pSRB, link);
2155 }
2156
2157 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX));
2158 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock));
2159 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense));
2160
2161 pSRB->SRBTotalXferLength = 0;
2162 pSRB->SRBSGCount = 0;
2163 pSRB->SRBSGIndex = 0;
2164 pSRB->SRBFlag = 0;
2165
2166 pSRB->SRBState = TRM_FREE;
2167 pSRB->AdaptStatus = TRM_STATUS_GOOD;
2168 pSRB->TargetStatus = SCSI_OK;
2169 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */
2170
2171 pSRB->xs = NULL;
2172 pSRB->pSRBDCB = NULL;
2173
2174 if (pSRB != &sc->SRB[0])
2175 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link);
2176
2177 splx(intflag);
2178 }
2179
2180 /*
2181 * ------------------------------------------------------------
2182 * Function : trm_GoingSRB_Done
2183 * Purpose :
2184 * Inputs :
2185 * ------------------------------------------------------------
2186 */
2187 void
trm_GoingSRB_Done(struct trm_softc * sc)2188 trm_GoingSRB_Done(struct trm_softc *sc)
2189 {
2190 struct trm_scsi_req_q *pSRB;
2191
2192 /* ASSUME we are inside a splbio()/splx() pair */
2193
2194 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) {
2195 /* TODO XXXX: Is TIMED_OUT the best status? */
2196 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT;
2197 trm_FinishSRB(sc, pSRB);
2198 }
2199 }
2200
2201 /*
2202 * ------------------------------------------------------------
2203 * Function : trm_ResetSCSIBus
2204 * Purpose : Reset the SCSI bus
2205 * Inputs : struct trm_softc * -
2206 * ------------------------------------------------------------
2207 */
2208 void
trm_ResetSCSIBus(struct trm_softc * sc)2209 trm_ResetSCSIBus(struct trm_softc *sc)
2210 {
2211 const bus_space_handle_t ioh = sc->sc_iohandle;
2212 const bus_space_tag_t iot = sc->sc_iotag;
2213 int intflag;
2214
2215 intflag = splbio();
2216
2217 sc->sc_Flag |= RESET_DEV;
2218
2219 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI);
2220 while ((bus_space_read_2(iot, ioh,
2221 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0);
2222
2223 splx(intflag);
2224 }
2225
2226 /*
2227 * ------------------------------------------------------------
2228 * Function : trm_ScsiRstDetect
2229 * Purpose :
2230 * Inputs :
2231 * ------------------------------------------------------------
2232 */
2233 void
trm_ScsiRstDetect(struct trm_softc * sc)2234 trm_ScsiRstDetect(struct trm_softc *sc)
2235 {
2236 const bus_space_handle_t ioh = sc->sc_iohandle;
2237 const bus_space_tag_t iot = sc->sc_iotag;
2238 int wlval;
2239
2240 #ifdef TRM_DEBUG0
2241 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname);
2242 #endif
2243
2244 wlval = 1000;
2245 /*
2246 * delay 1 sec
2247 */
2248 while (--wlval != 0)
2249 DELAY(1000);
2250
2251 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER);
2252 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO);
2253
2254 if ((sc->sc_Flag & RESET_DEV) != 0)
2255 sc->sc_Flag |= RESET_DONE;
2256 else {
2257 sc->sc_Flag |= RESET_DETECT;
2258 trm_ResetAllDevParam(sc);
2259 trm_RecoverSRB(sc);
2260 sc->pActiveDCB = NULL;
2261 sc->sc_Flag = 0;
2262 trm_StartWaitingSRB(sc);
2263 }
2264 }
2265
2266 /*
2267 * ------------------------------------------------------------
2268 * Function : trm_RequestSense
2269 * Purpose :
2270 * Inputs :
2271 * ------------------------------------------------------------
2272 */
2273 void
trm_RequestSense(struct trm_softc * sc,struct trm_scsi_req_q * pSRB)2274 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB)
2275 {
2276 pSRB->SRBFlag |= TRM_AUTO_REQSENSE;
2277
2278 /*
2279 * Status of initiator/target
2280 */
2281 pSRB->AdaptStatus = TRM_STATUS_GOOD;
2282 pSRB->TargetStatus = SCSI_OK;
2283 /*
2284 * Status of initiator/target
2285 */
2286
2287 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr;
2288 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data);
2289 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data);
2290 pSRB->SRBSGCount = 1;
2291 pSRB->SRBSGIndex = 0;
2292
2293 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock));
2294
2295 pSRB->CmdBlock[0] = REQUEST_SENSE;
2296 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5;
2297 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data);
2298
2299 pSRB->ScsiCmdLen = 6;
2300
2301 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0))
2302 timeout_add(&pSRB->xs->stimeout, (pSRB->xs->timeout/1000) * hz);
2303
2304 if (trm_StartSRB(sc, pSRB) != 0)
2305 trm_RewaitSRB(sc, pSRB);
2306 }
2307
2308 /*
2309 * ------------------------------------------------------------
2310 * Function : trm_EnableMsgOut
2311 * Purpose : set up MsgBuf to send out a single byte message
2312 * Inputs :
2313 * ------------------------------------------------------------
2314 */
2315 void
trm_EnableMsgOut(struct trm_softc * sc,u_int8_t msg)2316 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg)
2317 {
2318 sc->MsgBuf[0] = msg;
2319 sc->MsgCnt = 1;
2320
2321 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN);
2322 }
2323
2324 /*
2325 * ------------------------------------------------------------
2326 * Function : trm_linkSRB
2327 * Purpose :
2328 * Inputs :
2329 * ------------------------------------------------------------
2330 */
2331 void
trm_linkSRB(struct trm_softc * sc)2332 trm_linkSRB(struct trm_softc *sc)
2333 {
2334 struct trm_scsi_req_q *pSRB;
2335 int i, intflag;
2336
2337 intflag = splbio();
2338
2339 for (i = 0; i < TRM_MAX_SRB_CNT; i++) {
2340 pSRB = &sc->SRB[i];
2341
2342 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr
2343 + i * sizeof(struct trm_scsi_req_q);
2344
2345 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr
2346 + i * sizeof(struct trm_scsi_req_q)
2347 + offsetof(struct trm_scsi_req_q, SegmentX);
2348
2349 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr
2350 + i * sizeof(struct trm_scsi_req_q)
2351 + offsetof(struct trm_scsi_req_q, scsisense);
2352
2353 /*
2354 * map all SRB space
2355 */
2356 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE,
2357 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0,
2358 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
2359 &pSRB->dmamapxfer) != 0) {
2360 printf("%s: unable to create DMA transfer map\n",
2361 sc->sc_device.dv_xname);
2362 splx(intflag);
2363 return;
2364 }
2365
2366 if (i > 0)
2367 /* We use sc->SRB[0] directly, so *don't* link it */
2368 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link);
2369 #ifdef TRM_DEBUG0
2370 printf("pSRB = %p ", pSRB);
2371 #endif
2372 }
2373 #ifdef TRM_DEBUG0
2374 printf("\n ");
2375 #endif
2376 splx(intflag);
2377 }
2378
2379 /*
2380 * ------------------------------------------------------------
2381 * Function : trm_minphys
2382 * Purpose : limited by the number of segments in the dma segment list
2383 * Inputs : *buf
2384 * ------------------------------------------------------------
2385 */
2386 void
trm_minphys(struct buf * bp)2387 trm_minphys(struct buf *bp)
2388 {
2389 if (bp->b_bcount > (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG) {
2390 bp->b_bcount = (TRM_MAX_SG_LISTENTRY-1) * (long) NBPG;
2391 }
2392 minphys(bp);
2393 }
2394
2395 /*
2396 * ------------------------------------------------------------
2397 * Function : trm_initACB
2398 * Purpose : initialize the internal structures for a given SCSI host
2399 * Inputs :
2400 * ------------------------------------------------------------
2401 */
2402 void
trm_initACB(struct trm_softc * sc,int unit)2403 trm_initACB(struct trm_softc *sc, int unit)
2404 {
2405 const bus_space_handle_t ioh = sc->sc_iohandle;
2406 const bus_space_tag_t iot = sc->sc_iotag;
2407 struct trm_adapter_nvram *pEEpromBuf;
2408 struct trm_dcb *pDCB;
2409 int target, lun;
2410
2411 pEEpromBuf = &trm_eepromBuf[unit];
2412 sc->sc_config = HCC_AUTOTERM | HCC_PARITY;
2413
2414 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0)
2415 sc->sc_config |= HCC_WIDE_CARD;
2416
2417 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0)
2418 sc->sc_config |= HCC_SCSI_RESET;
2419
2420 TAILQ_INIT(&sc->freeSRB);
2421 TAILQ_INIT(&sc->waitingSRB);
2422 TAILQ_INIT(&sc->goingSRB);
2423
2424 sc->pActiveDCB = NULL;
2425 sc->sc_AdapterUnit = unit;
2426 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId;
2427 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag;
2428 sc->sc_Flag = 0;
2429
2430 /*
2431 * put all SRB's (except [0]) onto the freeSRB list
2432 */
2433 trm_linkSRB(sc);
2434
2435 /*
2436 * allocate DCB array
2437 */
2438 for (target = 0; target < TRM_MAX_TARGETS; target++) {
2439 if (target == sc->sc_AdaptSCSIID)
2440 continue;
2441
2442 for (lun = 0; lun < TRM_MAX_LUNS; lun++) {
2443 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), M_DEVBUF, M_NOWAIT);
2444 sc->pDCB[target][lun] = pDCB;
2445
2446 if (pDCB == NULL)
2447 continue;
2448
2449 bzero(pDCB, sizeof(struct trm_dcb));
2450
2451 pDCB->target = target;
2452 pDCB->lun = lun;
2453 pDCB->pActiveSRB = NULL;
2454 }
2455 }
2456
2457 sc->sc_adapter.scsi_cmd = trm_scsi_cmd;
2458 sc->sc_adapter.scsi_minphys = trm_minphys;
2459
2460 sc->sc_link.adapter_softc = sc;
2461 sc->sc_link.adapter_target = sc->sc_AdaptSCSIID;
2462 sc->sc_link.openings = 30; /* So TagMask (32 bit integer) always has space */
2463 sc->sc_link.device = &trm_device;
2464 sc->sc_link.adapter = &sc->sc_adapter;
2465 sc->sc_link.adapter_buswidth = ((sc->sc_config & HCC_WIDE_CARD) == 0) ? 8:16;
2466
2467 trm_reset(sc);
2468 }
2469
2470 /*
2471 * ------------------------------------------------------------
2472 * Function : trm_write_all
2473 * Description : write pEEpromBuf 128 bytes to seeprom
2474 * Input : iot, ioh - chip's base address
2475 * Output : none
2476 * ------------------------------------------------------------
2477 */
2478 void
trm_write_all(struct trm_adapter_nvram * pEEpromBuf,bus_space_tag_t iot,bus_space_handle_t ioh)2479 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot,
2480 bus_space_handle_t ioh)
2481 {
2482 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf;
2483 u_int8_t bAddr;
2484
2485 /*
2486 * Enable SEEPROM
2487 */
2488 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2489 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM));
2490 /*
2491 * Write enable
2492 */
2493 trm_write_cmd(iot, ioh, 0x04, 0xFF);
2494 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2495 trm_wait_30us(iot, ioh);
2496 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
2497 trm_set_data(iot, ioh, bAddr, *bpEeprom);
2498 /*
2499 * Write disable
2500 */
2501 trm_write_cmd(iot, ioh, 0x04, 0x00);
2502 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2503 trm_wait_30us(iot, ioh);
2504 /*
2505 * Disable SEEPROM
2506 */
2507 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2508 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM));
2509 }
2510
2511 /*
2512 * ------------------------------------------------------------
2513 * Function : trm_set_data
2514 * Description : write one byte to seeprom
2515 * Input : iot, ioh - chip's base address
2516 * bAddr - address of SEEPROM
2517 * bData - data of SEEPROM
2518 * Output : none
2519 * ------------------------------------------------------------
2520 */
2521 void
trm_set_data(bus_space_tag_t iot,bus_space_handle_t ioh,u_int8_t bAddr,u_int8_t bData)2522 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr,
2523 u_int8_t bData)
2524 {
2525 u_int8_t bSendData;
2526 int i;
2527
2528 /*
2529 * Send write command & address
2530 */
2531 trm_write_cmd(iot, ioh, 0x05, bAddr);
2532 /*
2533 * Write data
2534 */
2535 for (i = 0; i < 8; i++, bData <<= 1) {
2536 bSendData = NVR_SELECT;
2537 if ((bData & 0x80) != 0) { /* Start from bit 7 */
2538 bSendData |= NVR_BITOUT;
2539 }
2540 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData);
2541 trm_wait_30us(iot, ioh);
2542 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2543 (bSendData | NVR_CLOCK));
2544 trm_wait_30us(iot, ioh);
2545 }
2546 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2547 trm_wait_30us(iot, ioh);
2548 /*
2549 * Disable chip select
2550 */
2551 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2552 trm_wait_30us(iot, ioh);
2553 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2554 trm_wait_30us(iot, ioh);
2555 /*
2556 * Wait for write ready
2557 */
2558 for (;;) {
2559 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2560 (NVR_SELECT | NVR_CLOCK));
2561 trm_wait_30us(iot, ioh);
2562 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2563 trm_wait_30us(iot, ioh);
2564 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN)
2565 break;
2566 }
2567 /*
2568 * Disable chip select
2569 */
2570 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2571 }
2572
2573 /*
2574 * ------------------------------------------------------------
2575 * Function : trm_read_all
2576 * Description : read seeprom 128 bytes to pEEpromBuf
2577 * Input : pEEpromBuf, iot, ioh - chip's base address
2578 * Output : none
2579 * ------------------------------------------------------------
2580 */
2581 void
trm_read_all(struct trm_adapter_nvram * pEEpromBuf,bus_space_tag_t iot,bus_space_handle_t ioh)2582 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot,
2583 bus_space_handle_t ioh)
2584 {
2585 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf;
2586 u_int8_t bAddr;
2587
2588 /*
2589 * Enable SEEPROM
2590 */
2591 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2592 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM));
2593
2594 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++)
2595 *bpEeprom = trm_get_data(iot, ioh, bAddr);
2596
2597 /*
2598 * Disable SEEPROM
2599 */
2600 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL,
2601 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM));
2602 }
2603
2604 /*
2605 * ------------------------------------------------------------
2606 * Function : trm_get_data
2607 * Description : read one byte from seeprom
2608 * Input : iot, ioh - chip's base address
2609 * bAddr - address of SEEPROM
2610 * Output : bData - data of SEEPROM
2611 * ------------------------------------------------------------
2612 */
2613 u_int8_t
trm_get_data(bus_space_tag_t iot,bus_space_handle_t ioh,u_int8_t bAddr)2614 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr)
2615 {
2616 u_int8_t bReadData, bData;
2617 int i;
2618
2619 bData = 0;
2620
2621 /*
2622 * Send read command & address
2623 */
2624 trm_write_cmd(iot, ioh, 0x06, bAddr);
2625
2626 for (i = 0; i < 8; i++) {
2627 /*
2628 * Read data
2629 */
2630 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2631 (NVR_SELECT | NVR_CLOCK));
2632 trm_wait_30us(iot, ioh);
2633 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2634 /*
2635 * Get data bit while falling edge
2636 */
2637 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM);
2638 bData <<= 1;
2639 if ((bReadData & NVR_BITIN) != 0)
2640 bData |= 1;
2641 trm_wait_30us(iot, ioh);
2642 }
2643 /*
2644 * Disable chip select
2645 */
2646 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0);
2647
2648 return bData;
2649 }
2650
2651 /*
2652 * ------------------------------------------------------------
2653 * Function : trm_wait_30us
2654 * Description : wait 30 us
2655 * Input : iot, ioh - chip's base address
2656 * Output : none
2657 * ------------------------------------------------------------
2658 */
2659 void
trm_wait_30us(bus_space_tag_t iot,bus_space_handle_t ioh)2660 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh)
2661 {
2662 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5);
2663
2664 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT)
2665 == 0);
2666 }
2667
2668 /*
2669 * ------------------------------------------------------------
2670 * Function : trm_write_cmd
2671 * Description : write SB and Op Code into seeprom
2672 * Input : iot, ioh - chip's base address
2673 * bCmd - SB + Op Code
2674 * bAddr - address of SEEPROM
2675 * Output : none
2676 * ------------------------------------------------------------
2677 */
2678 void
trm_write_cmd(bus_space_tag_t iot,bus_space_handle_t ioh,u_int8_t bCmd,u_int8_t bAddr)2679 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd,
2680 u_int8_t bAddr)
2681 {
2682 u_int8_t bSendData;
2683 int i;
2684
2685 for (i = 0; i < 3; i++, bCmd <<= 1) {
2686 /*
2687 * Program SB + OP code
2688 */
2689 bSendData = NVR_SELECT;
2690 if (bCmd & 0x04) /* Start from bit 2 */
2691 bSendData |= NVR_BITOUT;
2692 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData);
2693 trm_wait_30us(iot, ioh);
2694 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2695 (bSendData | NVR_CLOCK));
2696 trm_wait_30us(iot, ioh);
2697 }
2698
2699 for (i = 0; i < 7; i++, bAddr <<= 1) {
2700 /*
2701 * Program address
2702 */
2703 bSendData = NVR_SELECT;
2704 if (bAddr & 0x40) { /* Start from bit 6 */
2705 bSendData |= NVR_BITOUT;
2706 }
2707 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData);
2708 trm_wait_30us(iot, ioh);
2709 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM,
2710 (bSendData | NVR_CLOCK));
2711 trm_wait_30us(iot, ioh);
2712 }
2713 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT);
2714 trm_wait_30us(iot, ioh);
2715 }
2716
2717 /*
2718 * ------------------------------------------------------------
2719 * Function : trm_check_eeprom
2720 * Description : read eeprom 128 bytes to pEEpromBuf and check
2721 * checksum. If it is wrong, updated with default value.
2722 * Input : eeprom, iot, ioh - chip's base address
2723 * Output : none
2724 * ------------------------------------------------------------
2725 */
2726 void
trm_check_eeprom(struct trm_adapter_nvram * pEEpromBuf,bus_space_tag_t iot,bus_space_handle_t ioh)2727 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot,
2728 bus_space_handle_t ioh)
2729 {
2730 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget;
2731 u_int32_t dAddr;
2732 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf;
2733 u_int16_t wAddr, wCheckSum;
2734
2735 #ifdef TRM_DEBUG0
2736 printf("\ntrm_check_eeprom\n");
2737 #endif
2738 trm_read_all(pEEpromBuf, iot, ioh);
2739 wCheckSum = 0;
2740 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++)
2741 wCheckSum += *wpEeprom;
2742
2743 if (wCheckSum != 0x1234) {
2744 #ifdef TRM_DEBUG0
2745 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n");
2746 #endif
2747 /*
2748 * Checksum error, load default
2749 */
2750 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2;
2751 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2
2752 >> 8);
2753 pEEpromBuf->NvramSubSysID[0] = (u_int8_t)
2754 PCI_PRODUCT_TEKRAM2_DC3X5U;
2755 pEEpromBuf->NvramSubSysID[1] = (u_int8_t)
2756 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8);
2757 pEEpromBuf->NvramSubClass = 0;
2758 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2;
2759 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2
2760 >> 8);
2761 pEEpromBuf->NvramDeviceID[0] = (u_int8_t)
2762 PCI_PRODUCT_TEKRAM2_DC3X5U;
2763 pEEpromBuf->NvramDeviceID[1] = (u_int8_t)
2764 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8);
2765 pEEpromBuf->NvramReserved = 0;
2766
2767 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++)
2768 /*
2769 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0
2770 */
2771 *dpEeprom = 0x00000077;
2772
2773 /*
2774 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId
2775 */
2776 *dpEeprom++ = 0x04000F07;
2777
2778 /*
2779 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0
2780 */
2781 *dpEeprom++ = 0x00000015;
2782 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++)
2783 *dpEeprom = 0;
2784
2785 pEEpromBuf->NvramCheckSum = 0;
2786 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++)
2787 wCheckSum += *wpEeprom;
2788
2789 *wpEeprom = 0x1234 - wCheckSum;
2790 trm_write_all(pEEpromBuf, iot, ioh);
2791 }
2792 }
2793
2794 /*
2795 * ------------------------------------------------------------
2796 * Function : trm_initAdapter
2797 * Purpose : initialize the SCSI chip ctrl registers
2798 * Inputs : psh - pointer to this host adapter's structure
2799 * ------------------------------------------------------------
2800 */
2801 void
trm_initAdapter(struct trm_softc * sc)2802 trm_initAdapter(struct trm_softc *sc)
2803 {
2804 const bus_space_handle_t ioh = sc->sc_iohandle;
2805 const bus_space_tag_t iot = sc->sc_iotag;
2806 u_int16_t wval;
2807 u_int8_t bval;
2808
2809 /*
2810 * program configuration 0
2811 */
2812 if ((sc->sc_config & HCC_PARITY) != 0) {
2813 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK;
2814 } else {
2815 bval = PHASELATCH | INITIATOR | BLOCKRST;
2816 }
2817 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval);
2818 /*
2819 * program configuration 1
2820 */
2821 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13);
2822 /*
2823 * 250ms selection timeout
2824 */
2825 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT);
2826 /*
2827 * Mask all the interrupt
2828 */
2829 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0);
2830 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0);
2831 /*
2832 * Reset SCSI module
2833 */
2834 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE);
2835 /*
2836 * program Host ID
2837 */
2838 bval = sc->sc_AdaptSCSIID;
2839 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval);
2840 /*
2841 * set ansynchronous transfer
2842 */
2843 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0);
2844 /*
2845 * Turn LED control off
2846 */
2847 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F;
2848 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval);
2849 /*
2850 * DMA config
2851 */
2852 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE;
2853 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval);
2854 /*
2855 * Clear pending interrupt status
2856 */
2857 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS);
2858 /*
2859 * Enable SCSI interrupts
2860 */
2861 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN,
2862 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED |
2863 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE));
2864 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR);
2865 }
2866
2867 /*
2868 * ------------------------------------------------------------
2869 * Function : trm_init
2870 * Purpose : initialize the internal structures for a given SCSI host
2871 * Inputs : host - pointer to this host adapter's structure
2872 * Preconditions : when this function is called, the chip_type field of
2873 * the ACB structure MUST have been set.
2874 * ------------------------------------------------------------
2875 */
2876 int
trm_init(struct trm_softc * sc,int unit)2877 trm_init(struct trm_softc *sc, int unit)
2878 {
2879 const bus_space_handle_t ioh = sc->sc_iohandle;
2880 const bus_space_tag_t iot = sc->sc_iotag;
2881 bus_dma_segment_t seg;
2882 int error, rseg, all_srbs_size;
2883
2884 /*
2885 * EEPROM CHECKSUM
2886 */
2887 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh);
2888
2889 /*
2890 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK
2891 */
2892 /*
2893 * allocate the space for all SCSI control blocks (SRB) for DMA memory.
2894 */
2895 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q);
2896
2897 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg,
2898 1, &rseg, BUS_DMA_NOWAIT);
2899 if (error != 0) {
2900 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n",
2901 sc->sc_device.dv_xname, error);
2902 /*errx(error, "%s: unable to allocate SCSI request blocks",
2903 sc->sc_device.dv_xname);*/
2904 return -1;
2905 }
2906
2907 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size,
2908 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT);
2909 if (error != 0) {
2910 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n",
2911 sc->sc_device.dv_xname, error);
2912 /*errx(error, "unable to map SCSI request blocks");*/
2913 return -1;
2914 }
2915
2916 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1,
2917 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control);
2918 if (error != 0) {
2919 printf("%s: unable to create SRB DMA maps, error = %d\n",
2920 sc->sc_device.dv_xname, error);
2921 /*errx(error, "unable to create SRB DMA maps");*/
2922 return -1;
2923 }
2924
2925 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control,
2926 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT);
2927 if (error != 0) {
2928 printf("%s: unable to load SRB DMA maps, error = %d\n",
2929 sc->sc_device.dv_xname, error);
2930 /*errx(error, "unable to load SRB DMA maps");*/
2931 return -1;
2932 }
2933 #ifdef TRM_DEBUG0
2934 printf("\n\n%s: all_srbs_size=%x\n",
2935 sc->sc_device.dv_xname, all_srbs_size);
2936 #endif
2937 bzero(sc->SRB, all_srbs_size);
2938 trm_initACB(sc, unit);
2939 trm_initAdapter(sc);
2940
2941 return 0;
2942 }
2943
2944 /* ------------------------------------------------------------
2945 * Function : trm_print_info
2946 * Purpose : Print the DCB negotiation information
2947 * Inputs :
2948 * ------------------------------------------------------------
2949 */
2950 void
trm_print_info(struct trm_softc * sc,struct trm_dcb * pDCB)2951 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB)
2952 {
2953 int syncXfer, index;
2954
2955 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC);
2956
2957 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target);
2958 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0)
2959 printf("16 bit ");
2960 else
2961 printf("8 bit ");
2962
2963 if (pDCB->SyncOffset == 0)
2964 printf("Asynchronous ");
2965 else {
2966 syncXfer = 100000 / (trm_clock_period[index] * 4);
2967 printf("%d.%01d MHz, Offset %d ",
2968 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset);
2969 }
2970 printf("data transfers ");
2971
2972 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0)
2973 printf("with Tag Queuing");
2974
2975 printf("\n");
2976 }
2977