1 /* $OpenBSD: tc921x.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 2001, 2002 Vladimir Popov <jumbo@narod.ru>. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 24 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 /* 27 * Toshiba's High Speed PLL for DTS 28 * http://www.chipbook.co.kr/pdf/ic/toshiba/TC9216.pdf 29 * 30 * TC9216P, TC9217P, TC9217F are a high speed PLL-LSI with built-in 2 modulus 31 * prescaler. Each function is controlled through 3 serial bus lines and high 32 * performance digital tuning system can be constituted. 33 * 34 */ 35 36 #ifndef _TC921X_H_ 37 #define _TC921X_H_ 38 39 #include <sys/types.h> 40 41 #include <machine/bus.h> 42 43 #define TC921X_REGISTER_LENGTH 24 44 45 /* Input Register at 0xD0 */ 46 #define TC921X_D0_FREQ_DIVIDER 0xFFFF 47 48 /* (*) are only available at 4.5 MHz crystal resonator used */ 49 #define TC921X_D0_REF_FREQ_500_HZ (0x0 << 16) 50 #define TC921X_D0_REF_FREQ_1_KHZ (0x1 << 16) 51 #define TC921X_D0_REF_FREQ_2P5_KHZ (0x2 << 16) 52 #define TC921X_D0_REF_FREQ_3_KHZ (0x3 << 16) 53 #define TC921X_D0_REF_FREQ_3P125_KHZ (0x4 << 16) 54 #define TC921X_D0_REF_FREQ_3PXXX_KHZ (0x5 << 16) /* (*) */ 55 #define TC921X_D0_REF_FREQ_5_KHZ (0x6 << 16) 56 #define TC921X_D0_REF_FREQ_6P25_KHZ (0x7 << 16) 57 #define TC921X_D0_REF_FREQ_7PXXX_KHZ (0x8 << 16) /* (*) */ 58 #define TC921X_D0_REF_FREQ_9_KHZ (0x9 << 16) 59 #define TC921X_D0_REF_FREQ_10_KHZ (0xA << 16) 60 #define TC921X_D0_REF_FREQ_12P5_KHZ (0xB << 16) 61 #define TC921X_D0_REF_FREQ_25_KHZ (0xC << 16) 62 #define TC921X_D0_REF_FREQ_50_KHZ (0xD << 16) 63 #define TC921X_D0_REF_FREQ_100_KHZ (0xE << 16) 64 #define TC921X_D0_REF_FREQ_NOT_USED (0xF << 16) 65 66 #define TC921X_D0_DIRECT_DIVIDING_MODE (0 << 20) 67 #define TC921X_D0_PULSE_SWALLOW_HF_MODE (2 << 20) 68 #define TC921X_D0_PULSE_SWALLOW_FM_MODE (1 << 20) 69 #define TC921X_D0_HALF_PULSE_SWALLOW_MODE (3 << 20) 70 71 #define TC921X_D0_OSC_7POINT2_MHZ (1 << 22) 72 #define TC921X_D0_OSC_4POINT5_MHZ (0 << 22) 73 74 #define TC921X_D0_OUT_CONTROL_ON (1 << 23) 75 #define TC921X_D0_OUT_CONTROL_OFF (0 << 23) 76 77 /* Input Register at 0xD2 */ 78 #define TC921X_D2_GATE_TIME(x) (x << 0) 79 #define TC921X_D2_GATE_TIME_1MS TC921X_D2_GATE_TIME(0) 80 #define TC921X_D2_GATE_TIME_4MS TC921X_D2_GATE_TIME(1) 81 #define TC921X_D2_GATE_TIME_16MS TC921X_D2_GATE_TIME(2) 82 #define TC921X_D2_GATE_TIME_MANUAL TC921X_D2_GATE_TIME(3) 83 84 #define TC921X_D2_COUNTER_MODE(x) (x << 2) 85 86 #define TC921X_D2_COUNTER_INPUT_SC (1 << 5) 87 #define TC921X_D2_COUNTER_INPUT_HFC (1 << 6) 88 #define TC921X_D2_COUNTER_INPUT_LFC (1 << 7) 89 90 #define TC921X_D2_START_BIT (1 << 8) 91 #define TC921X_D2_TEST_BIT (1 << 9) 92 93 #define TC921X_D2_IO_PORT(x) (x << 10) 94 #define TC921X_D2_IO_PORT_OUTPUT(x) (x << 15) 95 #define TC921X_D2_IO_PORT_INPUT(x) (x << 19) 96 97 struct tc921x_t { 98 bus_space_tag_t iot; 99 bus_space_handle_t ioh; 100 bus_size_t offset; 101 102 u_int8_t period; 103 u_int8_t clock; 104 u_int8_t data; 105 }; 106 107 void tc921x_write_addr(struct tc921x_t *, u_int8_t, u_int32_t); 108 u_int32_t tc921x_read_addr(struct tc921x_t *, u_int8_t); 109 u_int32_t tc921x_encode_freq(u_int32_t); 110 u_int32_t tc921x_decode_freq(u_int32_t); 111 112 #endif /* _TC921X_H_ */ 113