1 /* $OpenBSD: tc921x.c,v 1.2 2003/10/21 18:58:49 jmc Exp $ */
2
3 /*
4 * Copyright (c) 2001, 2002 Vladimir Popov <jumbo@narod.ru>.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
24 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26 /*
27 * Toshiba's High Speed PLL for DTS
28 * http://www.chipbook.co.kr/pdf/ic/toshiba/TC9216.pdf
29 *
30 * TC9216P, TC9217P, TC9217F are a high speed PLL-LSI with built-in 2 modulus
31 * prescaler. Each function is controlled through 3 serial bus lines and high
32 * performance digital tuning system can be constituted.
33 *
34 * Each function is controlled by the data setting to a pair of 24-bit
35 * registers. Each data of these registers is exchanged with controller side
36 * by 3 serial lines of DATA, CLOCK and PERIOD.
37 *
38 * 8 address bits and 24 data bits, total 32 bits, are transferred thru
39 * serial port.
40 *
41 * Input data is latched to the first and second input registers at the fall
42 * of PERIOD signal and each function is activated.
43 *
44 * Each output data is latched to output register in parallel at the fall
45 * timing of the 9th of CLOCK signal and can be received serially over the
46 * DATA line. Serial data of DATA, CLOCK and PERIOD is synchronized with
47 * crystal oscillation clock and tacken into the internal circuit of LSI.
48 * Thus, if crystal oscillator is stopped, serial data can not be input.
49 */
50
51 #include <sys/param.h>
52 #include <sys/radioio.h>
53
54 #include <dev/ic/tc921x.h>
55
56 #define PL_CL_DL(c) ((0 << c->period) | (0 << c->clock) | (0 << c->data))
57 #define PL_CL_DH(c) ((0 << c->period) | (0 << c->clock) | (1 << c->data))
58 #define PL_CH_DL(c) ((0 << c->period) | (1 << c->clock) | (0 << c->data))
59 #define PL_CH_DH(c) ((0 << c->period) | (1 << c->clock) | (1 << c->data))
60
61 #define PH_CL_DL(c) ((1 << c->period) | (0 << c->clock) | (0 << c->data))
62 #define PH_CL_DH(c) ((1 << c->period) | (0 << c->clock) | (1 << c->data))
63 #define PH_CH_DL(c) ((1 << c->period) | (1 << c->clock) | (0 << c->data))
64 #define PH_CH_DH(c) ((1 << c->period) | (1 << c->clock) | (1 << c->data))
65
66 #define PERIOD_LOW 0
67 #define PERIOD_HIGH 1
68
69 static void __tc921x_write_burst(unsigned int, u_int32_t, struct tc921x_t *, int);
70 static u_int32_t __tc921x_read_burst(unsigned int, struct tc921x_t *);
71
72 u_int32_t
tc921x_encode_freq(u_int32_t freq)73 tc921x_encode_freq(u_int32_t freq) {
74 /* Normalize incoming frequency */
75 if (freq < MIN_FM_FREQ)
76 freq = MIN_FM_FREQ;
77 if (freq > MAX_FM_FREQ)
78 freq = MAX_FM_FREQ;
79
80 return (freq + IF_FREQ)/10;
81 }
82
83 u_int32_t
tc921x_decode_freq(u_int32_t reg)84 tc921x_decode_freq(u_int32_t reg) {
85 return (reg & TC921X_D0_FREQ_DIVIDER) * 10 - IF_FREQ;
86 }
87
88 u_int32_t
tc921x_read_addr(struct tc921x_t * c,u_int8_t addr)89 tc921x_read_addr(struct tc921x_t *c, u_int8_t addr) {
90 u_int32_t ret;
91
92 /* Finish previous transmission - PERIOD HIGH, CLOCK HIGH, DATA HIGH */
93 bus_space_write_1(c->iot, c->ioh, c->offset, PH_CH_DH(c));
94 /* Start transmission - PERIOD LOW, CLOCK HIGH, DATA HIGH */
95 bus_space_write_1(c->iot, c->ioh, c->offset, PL_CH_DH(c));
96
97 /*
98 * Period must be low when the register address transmission starts.
99 * Period must be high when the register data transmission starts.
100 * Do the switch in the middle of the address transmission.
101 */
102 __tc921x_write_burst(4, addr, c, PERIOD_LOW);
103 __tc921x_write_burst(4, addr >> 4, c, PERIOD_HIGH);
104
105 /* Reading data from the register */
106 ret = __tc921x_read_burst(TC921X_REGISTER_LENGTH, c);
107
108 /* End of transmission - PERIOD goes LOW then HIGH */
109 bus_space_write_1(c->iot, c->ioh, c->offset, PL_CH_DH(c));
110 bus_space_write_1(c->iot, c->ioh, c->offset, PH_CH_DH(c));
111
112 return ret;
113 }
114
115 void
tc921x_write_addr(struct tc921x_t * c,u_int8_t addr,u_int32_t reg)116 tc921x_write_addr(struct tc921x_t *c, u_int8_t addr, u_int32_t reg) {
117 /* Finish previous transmission - PERIOD HIGH, CLOCK HIGH, DATA HIGH */
118 bus_space_write_1(c->iot, c->ioh, c->offset, PH_CH_DH(c));
119 /* Start transmission - PERIOD LOW, CLOCK HIGH, DATA HIGH */
120 bus_space_write_1(c->iot, c->ioh, c->offset, PL_CH_DH(c));
121
122 /*
123 * Period must be low when the register address transmission starts.
124 * Period must be high when the register data transmission starts.
125 * Do the switch in the middle of the address transmission.
126 */
127 __tc921x_write_burst(4, addr, c, PERIOD_LOW);
128 __tc921x_write_burst(4, addr >> 4, c, PERIOD_HIGH);
129
130 /* Writing data to the register */
131 __tc921x_write_burst(TC921X_REGISTER_LENGTH, reg, c, 1);
132
133 /* End of transmission - PERIOD goes LOW then HIGH */
134 bus_space_write_1(c->iot, c->ioh, c->offset, PL_CH_DH(c));
135 bus_space_write_1(c->iot, c->ioh, c->offset, PH_CH_DH(c));
136 }
137
138 static void
__tc921x_write_burst(unsigned int length,u_int32_t data,struct tc921x_t * c,int p)139 __tc921x_write_burst(unsigned int length, u_int32_t data, struct tc921x_t *c, int p) {
140 int i;
141 u_int8_t cldh, chdh, cldl, chdl;
142
143 cldh = p == PERIOD_LOW ? PL_CL_DH(c) : PH_CL_DH(c);
144 chdh = p == PERIOD_LOW ? PL_CH_DH(c) : PH_CH_DH(c);
145 cldl = p == PERIOD_LOW ? PL_CL_DL(c) : PH_CL_DL(c);
146 chdl = p == PERIOD_LOW ? PL_CH_DL(c) : PH_CH_DL(c);
147
148 for (i = 0; i < length; i++)
149 if (data & (1 << i)) {
150 bus_space_write_1(c->iot, c->ioh, c->offset, cldh);
151 bus_space_write_1(c->iot, c->ioh, c->offset, chdh);
152 } else {
153 bus_space_write_1(c->iot, c->ioh, c->offset, cldl);
154 bus_space_write_1(c->iot, c->ioh, c->offset, chdl);
155 }
156 }
157
158 static u_int32_t
__tc921x_read_burst(unsigned int length,struct tc921x_t * c)159 __tc921x_read_burst(unsigned int length, struct tc921x_t *c) {
160 unsigned int i;
161 u_int32_t ret = 0ul;
162
163 #define DATA_ON (1 << c->data)
164
165 for (i = 0; i < length; i++) {
166 bus_space_write_1(c->iot, c->ioh, c->offset, PH_CL_DH(c));
167 bus_space_write_1(c->iot, c->ioh, c->offset, PH_CH_DH(c));
168 ret |= bus_space_read_1(c->iot, c->ioh, c->offset) & DATA_ON ?
169 (1 << i) : (0 << i);
170 }
171
172 return ret;
173 }
174