1 /* $OpenBSD: re.c,v 1.13 2005/05/24 00:46:18 brad Exp $ */
2 /* $FreeBSD: if_re.c,v 1.31 2004/09/04 07:54:05 ru Exp $ */
3 /*
4 * Copyright (c) 1997, 1998-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver
37 *
38 * Written by Bill Paul <wpaul@windriver.com>
39 * Senior Networking Software Engineer
40 * Wind River Systems
41 */
42
43 /*
44 * This driver is designed to support RealTek's next generation of
45 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
46 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S
47 * and the RTL8110S.
48 *
49 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
50 * with the older 8139 family, however it also supports a special
51 * C+ mode of operation that provides several new performance enhancing
52 * features. These include:
53 *
54 * o Descriptor based DMA mechanism. Each descriptor represents
55 * a single packet fragment. Data buffers may be aligned on
56 * any byte boundary.
57 *
58 * o 64-bit DMA
59 *
60 * o TCP/IP checksum offload for both RX and TX
61 *
62 * o High and normal priority transmit DMA rings
63 *
64 * o VLAN tag insertion and extraction
65 *
66 * o TCP large send (segmentation offload)
67 *
68 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
69 * programming API is fairly straightforward. The RX filtering, EEPROM
70 * access and PHY access is the same as it is on the older 8139 series
71 * chips.
72 *
73 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
74 * same programming API and feature set as the 8139C+ with the following
75 * differences and additions:
76 *
77 * o 1000Mbps mode
78 *
79 * o Jumbo frames
80 *
81 * o GMII and TBI ports/registers for interfacing with copper
82 * or fiber PHYs
83 *
84 * o RX and TX DMA rings can have up to 1024 descriptors
85 * (the 8139C+ allows a maximum of 64)
86 *
87 * o Slight differences in register layout from the 8139C+
88 *
89 * The TX start and timer interrupt registers are at different locations
90 * on the 8169 than they are on the 8139C+. Also, the status word in the
91 * RX descriptor has a slightly different bit layout. The 8169 does not
92 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
93 * copper gigE PHY.
94 *
95 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
96 * (the 'S' stands for 'single-chip'). These devices have the same
97 * programming API as the older 8169, but also have some vendor-specific
98 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
99 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
100 *
101 * This driver takes advantage of the RX and TX checksum offload and
102 * VLAN tag insertion/extraction features. It also implements TX
103 * interrupt moderation using the timer interrupt registers, which
104 * significantly reduces TX interrupt load. There is also support
105 * for jumbo frames, however the 8169/8169S/8110S can not transmit
106 * jumbo frames larger than 7.5K, so the max MTU possible with this
107 * driver is 7500 bytes.
108 */
109
110 #include "bpfilter.h"
111 #include "vlan.h"
112
113 #include <sys/param.h>
114 #include <sys/endian.h>
115 #include <sys/systm.h>
116 #include <sys/sockio.h>
117 #include <sys/mbuf.h>
118 #include <sys/malloc.h>
119 #include <sys/kernel.h>
120 #include <sys/device.h>
121 #include <sys/socket.h>
122
123 #include <net/if.h>
124 #include <net/if_dl.h>
125 #include <net/if_media.h>
126
127 #ifdef INET
128 #include <netinet/in.h>
129 #include <netinet/in_systm.h>
130 #include <netinet/in_var.h>
131 #include <netinet/ip.h>
132 #include <netinet/if_ether.h>
133 #endif
134
135 #if NVLAN > 0
136 #include <net/if_types.h>
137 #include <net/if_vlan_var.h>
138 #endif
139
140 #if NBPFILTER > 0
141 #include <net/bpf.h>
142 #endif
143
144 #include <dev/mii/mii.h>
145 #include <dev/mii/miivar.h>
146
147 #include <dev/pci/pcireg.h>
148 #include <dev/pci/pcivar.h>
149
150 #include <dev/ic/rtl81x9reg.h>
151
152 int redebug = 0;
153 #define DPRINTF(x) if (redebug) printf x
154
155 void re_attach_common (struct rl_softc *);
156
157 int re_encap (struct rl_softc *, struct mbuf *, int *);
158
159 int re_allocmem (struct rl_softc *);
160 int re_newbuf (struct rl_softc *, int, struct mbuf *);
161 int re_rx_list_init (struct rl_softc *);
162 int re_tx_list_init (struct rl_softc *);
163 void re_rxeof (struct rl_softc *);
164 void re_txeof (struct rl_softc *);
165 int re_intr (void *);
166 void re_tick (void *);
167 void re_start (struct ifnet *);
168 int re_ioctl (struct ifnet *, u_long, caddr_t);
169 int re_init (struct ifnet *);
170 void re_stop (struct rl_softc *);
171 void re_watchdog (struct ifnet *);
172 int re_ifmedia_upd (struct ifnet *);
173 void re_ifmedia_sts (struct ifnet *, struct ifmediareq *);
174
175 void re_eeprom_putbyte (struct rl_softc *, int);
176 void re_eeprom_getword (struct rl_softc *, int, u_int16_t *);
177 void re_read_eeprom (struct rl_softc *, caddr_t, int, int, int);
178
179 int re_gmii_readreg (struct device *, int, int);
180 void re_gmii_writereg (struct device *, int, int, int);
181
182 int re_miibus_readreg (struct device *, int, int);
183 void re_miibus_writereg (struct device *, int, int, int);
184 void re_miibus_statchg (struct device *);
185
186 void re_setmulti (struct rl_softc *);
187 void re_reset (struct rl_softc *);
188
189 int re_diag (struct rl_softc *);
190
191 struct cfdriver re_cd = {
192 0, "re", DV_IFNET
193 };
194
195 #define EE_SET(x) \
196 CSR_WRITE_1(sc, RL_EECMD, \
197 CSR_READ_1(sc, RL_EECMD) | x)
198
199 #define EE_CLR(x) \
200 CSR_WRITE_1(sc, RL_EECMD, \
201 CSR_READ_1(sc, RL_EECMD) & ~x)
202
203 /*
204 * Send a read command and address to the EEPROM, check for ACK.
205 */
206 void
re_eeprom_putbyte(sc,addr)207 re_eeprom_putbyte(sc, addr)
208 struct rl_softc *sc;
209 int addr;
210 {
211 register int d, i;
212
213 d = addr | sc->rl_eecmd_read;
214
215 /*
216 * Feed in each bit and strobe the clock.
217 */
218 for (i = 0x400; i; i >>= 1) {
219 if (d & i) {
220 EE_SET(RL_EE_DATAIN);
221 } else {
222 EE_CLR(RL_EE_DATAIN);
223 }
224 DELAY(100);
225 EE_SET(RL_EE_CLK);
226 DELAY(150);
227 EE_CLR(RL_EE_CLK);
228 DELAY(100);
229 }
230 }
231
232 /*
233 * Read a word of data stored in the EEPROM at address 'addr.'
234 */
235 void
re_eeprom_getword(sc,addr,dest)236 re_eeprom_getword(sc, addr, dest)
237 struct rl_softc *sc;
238 int addr;
239 u_int16_t *dest;
240 {
241 register int i;
242 u_int16_t word = 0;
243
244 /* Enter EEPROM access mode. */
245 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
246
247 /*
248 * Send address of word we want to read.
249 */
250 re_eeprom_putbyte(sc, addr);
251
252 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL);
253
254 /*
255 * Start reading bits from EEPROM.
256 */
257 for (i = 0x8000; i; i >>= 1) {
258 EE_SET(RL_EE_CLK);
259 DELAY(100);
260 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT)
261 word |= i;
262 EE_CLR(RL_EE_CLK);
263 DELAY(100);
264 }
265
266 /* Turn off EEPROM access mode. */
267 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
268
269 *dest = word;
270 }
271
272 /*
273 * Read a sequence of words from the EEPROM.
274 */
275 void
re_read_eeprom(sc,dest,off,cnt,swap)276 re_read_eeprom(sc, dest, off, cnt, swap)
277 struct rl_softc *sc;
278 caddr_t dest;
279 int off;
280 int cnt;
281 int swap;
282 {
283 int i;
284 u_int16_t word = 0, *ptr;
285
286 for (i = 0; i < cnt; i++) {
287 re_eeprom_getword(sc, off + i, &word);
288 ptr = (u_int16_t *)(dest + (i * 2));
289 if (swap)
290 *ptr = ntohs(word);
291 else
292 *ptr = word;
293 }
294 }
295
296 int
re_gmii_readreg(struct device * self,int phy,int reg)297 re_gmii_readreg(struct device *self, int phy, int reg)
298 {
299 struct rl_softc *sc = (struct rl_softc *)self;
300 u_int32_t rval;
301 int i;
302
303 if (phy != 7)
304 return (0);
305
306 /* Let the rgephy driver read the GMEDIASTAT register */
307
308 if (reg == RL_GMEDIASTAT) {
309 rval = CSR_READ_1(sc, RL_GMEDIASTAT);
310 return (rval);
311 }
312
313 CSR_WRITE_4(sc, RL_PHYAR, reg << 16);
314 DELAY(1000);
315
316 for (i = 0; i < RL_TIMEOUT; i++) {
317 rval = CSR_READ_4(sc, RL_PHYAR);
318 if (rval & RL_PHYAR_BUSY)
319 break;
320 DELAY(100);
321 }
322
323 if (i == RL_TIMEOUT) {
324 printf ("%s: PHY read failed\n", sc->sc_dev.dv_xname);
325 return (0);
326 }
327
328 return (rval & RL_PHYAR_PHYDATA);
329 }
330
331 void
re_gmii_writereg(struct device * dev,int phy,int reg,int data)332 re_gmii_writereg(struct device *dev, int phy, int reg, int data)
333 {
334 struct rl_softc *sc = (struct rl_softc *)dev;
335 u_int32_t rval;
336 int i;
337
338 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) |
339 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY);
340 DELAY(1000);
341
342 for (i = 0; i < RL_TIMEOUT; i++) {
343 rval = CSR_READ_4(sc, RL_PHYAR);
344 if (!(rval & RL_PHYAR_BUSY))
345 break;
346 DELAY(100);
347 }
348
349 if (i == RL_TIMEOUT) {
350 printf ("%s: PHY write failed\n", sc->sc_dev.dv_xname);
351 }
352 }
353
354 int
re_miibus_readreg(struct device * dev,int phy,int reg)355 re_miibus_readreg(struct device *dev, int phy, int reg)
356 {
357 struct rl_softc *sc = (struct rl_softc *)dev;
358 u_int16_t rval = 0;
359 u_int16_t re8139_reg = 0;
360 int s;
361
362 s = splimp();
363
364 if (sc->rl_type == RL_8169) {
365 rval = re_gmii_readreg(dev, phy, reg);
366 splx(s);
367 return (rval);
368 }
369
370 /* Pretend the internal PHY is only at address 0 */
371 if (phy) {
372 splx(s);
373 return (0);
374 }
375 switch(reg) {
376 case MII_BMCR:
377 re8139_reg = RL_BMCR;
378 break;
379 case MII_BMSR:
380 re8139_reg = RL_BMSR;
381 break;
382 case MII_ANAR:
383 re8139_reg = RL_ANAR;
384 break;
385 case MII_ANER:
386 re8139_reg = RL_ANER;
387 break;
388 case MII_ANLPAR:
389 re8139_reg = RL_LPAR;
390 break;
391 case MII_PHYIDR1:
392 case MII_PHYIDR2:
393 splx(s);
394 return (0);
395 /*
396 * Allow the rlphy driver to read the media status
397 * register. If we have a link partner which does not
398 * support NWAY, this is the register which will tell
399 * us the results of parallel detection.
400 */
401 case RL_MEDIASTAT:
402 rval = CSR_READ_1(sc, RL_MEDIASTAT);
403 splx(s);
404 return (rval);
405 default:
406 printf("%s: bad phy register\n", sc->sc_dev.dv_xname);
407 splx(s);
408 return (0);
409 }
410 rval = CSR_READ_2(sc, re8139_reg);
411 splx(s);
412 return (rval);
413 }
414
415 void
re_miibus_writereg(struct device * dev,int phy,int reg,int data)416 re_miibus_writereg(struct device *dev, int phy, int reg, int data)
417 {
418 struct rl_softc *sc = (struct rl_softc *)dev;
419 u_int16_t re8139_reg = 0;
420 int s;
421
422 s = splimp();
423
424 if (sc->rl_type == RL_8169) {
425 re_gmii_writereg(dev, phy, reg, data);
426 splx(s);
427 return;
428 }
429
430 /* Pretend the internal PHY is only at address 0 */
431 if (phy) {
432 splx(s);
433 return;
434 }
435 switch(reg) {
436 case MII_BMCR:
437 re8139_reg = RL_BMCR;
438 break;
439 case MII_BMSR:
440 re8139_reg = RL_BMSR;
441 break;
442 case MII_ANAR:
443 re8139_reg = RL_ANAR;
444 break;
445 case MII_ANER:
446 re8139_reg = RL_ANER;
447 break;
448 case MII_ANLPAR:
449 re8139_reg = RL_LPAR;
450 break;
451 case MII_PHYIDR1:
452 case MII_PHYIDR2:
453 splx(s);
454 return;
455 break;
456 default:
457 printf("%s: bad phy register\n", sc->sc_dev.dv_xname);
458 splx(s);
459 return;
460 }
461 CSR_WRITE_2(sc, re8139_reg, data);
462 splx(s);
463 }
464
465 void
re_miibus_statchg(struct device * dev)466 re_miibus_statchg(struct device *dev)
467 {
468 }
469
470 /*
471 * Program the 64-bit multicast hash filter.
472 */
473 void
re_setmulti(sc)474 re_setmulti(sc)
475 struct rl_softc *sc;
476 {
477 struct ifnet *ifp;
478 int h = 0;
479 u_int32_t hashes[2] = { 0, 0 };
480 u_int32_t rxfilt;
481 int mcnt = 0;
482 struct arpcom *ac = &sc->sc_arpcom;
483 struct ether_multi *enm;
484 struct ether_multistep step;
485
486 ifp = &sc->sc_arpcom.ac_if;
487
488 rxfilt = CSR_READ_4(sc, RL_RXCFG);
489
490 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
491 rxfilt |= RL_RXCFG_RX_MULTI;
492 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
493 CSR_WRITE_4(sc, RL_MAR0, 0xFFFFFFFF);
494 CSR_WRITE_4(sc, RL_MAR4, 0xFFFFFFFF);
495 return;
496 }
497
498 /* first, zot all the existing hash bits */
499 CSR_WRITE_4(sc, RL_MAR0, 0);
500 CSR_WRITE_4(sc, RL_MAR4, 0);
501
502 /* now program new ones */
503 ETHER_FIRST_MULTI(step, ac, enm);
504 while (enm != NULL) {
505 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
506 ifp->if_flags |= IFF_ALLMULTI;
507 mcnt = MAX_NUM_MULTICAST_ADDRESSES;
508 }
509 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
510 break;
511
512 h = (ether_crc32_be(enm->enm_addrlo,
513 ETHER_ADDR_LEN) >> 26) & 0x0000003F;
514 if (h < 32)
515 hashes[0] |= (1 << h);
516 else
517 hashes[1] |= (1 << (h - 32));
518 mcnt++;
519 ETHER_NEXT_MULTI(step, enm);
520 }
521
522 if (mcnt)
523 rxfilt |= RL_RXCFG_RX_MULTI;
524 else
525 rxfilt &= ~RL_RXCFG_RX_MULTI;
526
527 CSR_WRITE_4(sc, RL_RXCFG, rxfilt);
528 CSR_WRITE_4(sc, RL_MAR0, hashes[0]);
529 CSR_WRITE_4(sc, RL_MAR4, hashes[1]);
530 }
531
532 void
re_reset(sc)533 re_reset(sc)
534 struct rl_softc *sc;
535 {
536 register int i;
537
538 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);
539
540 for (i = 0; i < RL_TIMEOUT; i++) {
541 DELAY(10);
542 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET))
543 break;
544 }
545 if (i == RL_TIMEOUT)
546 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname);
547
548 CSR_WRITE_1(sc, 0x82, 1);
549 }
550
551 /*
552 * The following routine is designed to test for a defect on some
553 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
554 * lines connected to the bus, however for a 32-bit only card, they
555 * should be pulled high. The result of this defect is that the
556 * NIC will not work right if you plug it into a 64-bit slot: DMA
557 * operations will be done with 64-bit transfers, which will fail
558 * because the 64-bit data lines aren't connected.
559 *
560 * There's no way to work around this (short of talking a soldering
561 * iron to the board), however we can detect it. The method we use
562 * here is to put the NIC into digital loopback mode, set the receiver
563 * to promiscuous mode, and then try to send a frame. We then compare
564 * the frame data we sent to what was received. If the data matches,
565 * then the NIC is working correctly, otherwise we know the user has
566 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
567 * slot. In the latter case, there's no way the NIC can work correctly,
568 * so we print out a message on the console and abort the device attach.
569 */
570
571 int
re_diag(sc)572 re_diag(sc)
573 struct rl_softc *sc;
574 {
575 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
576 struct mbuf *m0;
577 struct ether_header *eh;
578 struct rl_desc *cur_rx;
579 bus_dmamap_t dmamap;
580 u_int16_t status;
581 u_int32_t rxstat;
582 int total_len, i, s, error = 0;
583 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
584 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
585
586 DPRINTF(("inside re_diag\n"));
587 /* Allocate a single mbuf */
588
589 MGETHDR(m0, M_DONTWAIT, MT_DATA);
590 if (m0 == NULL)
591 return (ENOBUFS);
592
593 /*
594 * Initialize the NIC in test mode. This sets the chip up
595 * so that it can send and receive frames, but performs the
596 * following special functions:
597 * - Puts receiver in promiscuous mode
598 * - Enables digital loopback mode
599 * - Leaves interrupts turned off
600 */
601
602 ifp->if_flags |= IFF_PROMISC;
603 sc->rl_testmode = 1;
604 re_init(ifp);
605 re_stop(sc);
606 DELAY(100000);
607 re_init(ifp);
608
609 /* Put some data in the mbuf */
610
611 eh = mtod(m0, struct ether_header *);
612 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN);
613 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN);
614 eh->ether_type = htons(ETHERTYPE_IP);
615 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
616
617 /*
618 * Queue the packet, start transmission.
619 */
620
621 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
622 s = splnet();
623 IFQ_ENQUEUE(&ifp->if_snd, m0, NULL, error);
624 re_start(ifp);
625 splx(s);
626 m0 = NULL;
627
628 DPRINTF(("re_diag: transmission started\n"));
629
630 /* Wait for it to propagate through the chip */
631
632 DELAY(100000);
633 for (i = 0; i < RL_TIMEOUT; i++) {
634 status = CSR_READ_2(sc, RL_ISR);
635 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) ==
636 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK))
637 break;
638 DELAY(10);
639 }
640 if (i == RL_TIMEOUT) {
641 printf("%s: diagnostic failed, failed to receive packet "
642 "in loopback mode\n", sc->sc_dev.dv_xname);
643 error = EIO;
644 goto done;
645 }
646
647 /*
648 * The packet should have been dumped into the first
649 * entry in the RX DMA ring. Grab it from there.
650 */
651
652 dmamap = sc->rl_ldata.rl_rx_list_map;
653 bus_dmamap_sync(sc->sc_dmat,
654 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
655 dmamap = sc->rl_ldata.rl_rx_dmamap[0];
656 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
657 BUS_DMASYNC_POSTWRITE);
658 bus_dmamap_unload(sc->sc_dmat,
659 sc->rl_ldata.rl_rx_dmamap[0]);
660
661 m0 = sc->rl_ldata.rl_rx_mbuf[0];
662 sc->rl_ldata.rl_rx_mbuf[0] = NULL;
663 eh = mtod(m0, struct ether_header *);
664
665 cur_rx = &sc->rl_ldata.rl_rx_list[0];
666 total_len = RL_RXBYTES(cur_rx);
667 rxstat = letoh32(cur_rx->rl_cmdstat);
668
669 if (total_len != ETHER_MIN_LEN) {
670 printf("%s: diagnostic failed, received short packet\n",
671 sc->sc_dev.dv_xname);
672 error = EIO;
673 goto done;
674 }
675
676 DPRINTF(("re_diag: packet received\n"));
677
678 /* Test that the received packet data matches what we sent. */
679
680 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) ||
681 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) ||
682 ntohs(eh->ether_type) != ETHERTYPE_IP) {
683 printf("%s: WARNING, DMA FAILURE!\n", sc->sc_dev.dv_xname);
684 printf("%s: expected TX data: %s",
685 sc->sc_dev.dv_xname, ether_sprintf(dst));
686 printf("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP);
687 printf("%s: received RX data: %s",
688 sc->sc_dev.dv_xname,
689 ether_sprintf(eh->ether_dhost));
690 printf("/%s/0x%x\n", ether_sprintf(eh->ether_shost),
691 ntohs(eh->ether_type));
692 printf("%s: You may have a defective 32-bit NIC plugged "
693 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname);
694 printf("%s: Please re-install the NIC in a 32-bit slot "
695 "for proper operation.\n", sc->sc_dev.dv_xname);
696 printf("%s: Read the re(4) man page for more details.\n",
697 sc->sc_dev.dv_xname);
698 error = EIO;
699 }
700
701 done:
702 /* Turn interface off, release resources */
703
704 sc->rl_testmode = 0;
705 ifp->if_flags &= ~IFF_PROMISC;
706 re_stop(sc);
707 if (m0 != NULL)
708 m_freem(m0);
709 DPRINTF(("leaving re_diag\n"));
710
711 return (error);
712 }
713
714 int
re_allocmem(struct rl_softc * sc)715 re_allocmem(struct rl_softc *sc)
716 {
717 int error;
718 int nseg, rseg;
719 int i;
720
721 nseg = 32;
722
723 /* Allocate DMA'able memory for the TX ring */
724
725 error = bus_dmamap_create(sc->sc_dmat, RL_TX_LIST_SZ, 1,
726 RL_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW,
727 &sc->rl_ldata.rl_tx_list_map);
728 if (error)
729 return (ENOMEM);
730 error = bus_dmamem_alloc(sc->sc_dmat, RL_TX_LIST_SZ,
731 ETHER_ALIGN, 0,
732 &sc->rl_ldata.rl_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT);
733 if (error)
734 return (ENOMEM);
735
736 /* Load the map for the TX ring. */
737 error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_tx_listseg,
738 1, RL_TX_LIST_SZ,
739 (caddr_t *)&sc->rl_ldata.rl_tx_list, BUS_DMA_NOWAIT);
740 if (error)
741 return (ENOMEM);
742 memset(sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ);
743
744 error = bus_dmamap_load(sc->sc_dmat, sc->rl_ldata.rl_tx_list_map,
745 sc->rl_ldata.rl_tx_list, RL_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
746 if (error)
747 return (ENOMEM);
748
749 /* Create DMA maps for TX buffers */
750
751 for (i = 0; i < RL_TX_DESC_CNT; i++) {
752 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg,
753 MCLBYTES, 0, BUS_DMA_ALLOCNOW,
754 &sc->rl_ldata.rl_tx_dmamap[i]);
755 if (error) {
756 printf("%s: can't create DMA map for TX\n",
757 sc->sc_dev.dv_xname);
758 return (ENOMEM);
759 }
760 }
761
762 /* Allocate DMA'able memory for the RX ring */
763
764 error = bus_dmamap_create(sc->sc_dmat, RL_RX_LIST_SZ, 1,
765 RL_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW,
766 &sc->rl_ldata.rl_rx_list_map);
767 if (error)
768 return (ENOMEM);
769
770 error = bus_dmamem_alloc(sc->sc_dmat, RL_RX_LIST_SZ, RL_RING_ALIGN,
771 0, &sc->rl_ldata.rl_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT);
772 if (error)
773 return (ENOMEM);
774
775 /* Load the map for the RX ring. */
776 error = bus_dmamem_map(sc->sc_dmat, &sc->rl_ldata.rl_rx_listseg,
777 1, RL_RX_LIST_SZ,
778 (caddr_t *)&sc->rl_ldata.rl_rx_list, BUS_DMA_NOWAIT);
779 if (error)
780 return (ENOMEM);
781 memset(sc->rl_ldata.rl_rx_list, 0, RL_RX_LIST_SZ);
782
783 error = bus_dmamap_load(sc->sc_dmat, sc->rl_ldata.rl_rx_list_map,
784 sc->rl_ldata.rl_rx_list, RL_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT);
785 if (error)
786 return (ENOMEM);
787
788 /* Create DMA maps for RX buffers */
789
790 for (i = 0; i < RL_RX_DESC_CNT; i++) {
791 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg,
792 MCLBYTES, 0, BUS_DMA_ALLOCNOW,
793 &sc->rl_ldata.rl_rx_dmamap[i]);
794 if (error) {
795 printf("%s: can't create DMA map for RX\n",
796 sc->sc_dev.dv_xname);
797 return (ENOMEM);
798 }
799 }
800
801 return (0);
802 }
803
804 /*
805 * Attach the interface. Allocate softc structures, do ifmedia
806 * setup and ethernet/BPF attach.
807 */
808 void
re_attach_common(struct rl_softc * sc)809 re_attach_common(struct rl_softc *sc)
810 {
811 u_char eaddr[ETHER_ADDR_LEN];
812 u_int16_t as[3];
813 struct ifnet *ifp;
814 u_int16_t re_did = 0;
815 int error = 0, i;
816
817 /* Reset the adapter. */
818 re_reset(sc);
819
820 sc->rl_type = RL_8169;
821
822 if (sc->rl_type == RL_8169) {
823
824 /* Set RX length mask */
825
826 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN;
827
828 /* Force station address autoload from the EEPROM */
829
830 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_AUTOLOAD);
831 for (i = 0; i < RL_TIMEOUT; i++) {
832 if (!(CSR_READ_1(sc, RL_EECMD) & RL_EEMODE_AUTOLOAD))
833 break;
834 DELAY(100);
835 }
836 if (i == RL_TIMEOUT)
837 printf ("%s: eeprom autoload timed out\n", sc->sc_dev.dv_xname);
838
839 for (i = 0; i < ETHER_ADDR_LEN; i++)
840 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i);
841 } else {
842
843 /* Set RX length mask */
844
845 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN;
846
847 sc->rl_eecmd_read = RL_EECMD_READ_6BIT;
848 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1, 0);
849 if (re_did != 0x8129)
850 sc->rl_eecmd_read = RL_EECMD_READ_8BIT;
851
852 /*
853 * Get station address from the EEPROM.
854 */
855 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3, 0);
856 for (i = 0; i < 3; i++) {
857 eaddr[(i * 2) + 0] = as[i] & 0xff;
858 eaddr[(i * 2) + 1] = as[i] >> 8;
859 }
860 }
861
862 bcopy(eaddr, (char *)&sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
863
864 printf(", address %s\n",
865 ether_sprintf(sc->sc_arpcom.ac_enaddr));
866
867 error = re_allocmem(sc);
868
869 if (error)
870 return;
871
872 ifp = &sc->sc_arpcom.ac_if;
873 ifp->if_softc = sc;
874 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ);
875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
876 ifp->if_ioctl = re_ioctl;
877 ifp->if_start = re_start;
878 ifp->if_watchdog = re_watchdog;
879 ifp->if_init = re_init;
880 if (sc->rl_type == RL_8169)
881 ifp->if_baudrate = 1000000000;
882 else
883 ifp->if_baudrate = 100000000;
884 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN);
885 IFQ_SET_READY(&ifp->if_snd);
886
887 ifp->if_capabilities = IFCAP_VLAN_MTU;
888
889 #ifdef RE_CSUM_OFFLOAD
890 ifp->if_capabilities |= IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4|
891 IFCAP_CSUM_UDPv4;
892 #endif
893
894 #ifdef RE_VLAN
895 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING;
896 #endif
897
898 timeout_set(&sc->timer_handle, re_tick, sc);
899
900 /* Do MII setup */
901 sc->sc_mii.mii_ifp = ifp;
902 sc->sc_mii.mii_readreg = re_miibus_readreg;
903 sc->sc_mii.mii_writereg = re_miibus_writereg;
904 sc->sc_mii.mii_statchg = re_miibus_statchg;
905 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, re_ifmedia_upd,
906 re_ifmedia_sts);
907 DPRINTF(("calling mii_attach\n"));
908 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
909 MII_OFFSET_ANY, 0);
910 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
911 printf("%s: no PHY found!\n", sc->sc_dev.dv_xname);
912 ifmedia_add(&sc->sc_mii.mii_media,
913 IFM_ETHER|IFM_NONE, 0, NULL);
914 ifmedia_set(&sc->sc_mii.mii_media,
915 IFM_ETHER|IFM_NONE);
916 } else
917 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
918
919 /*
920 * Call MI attach routine.
921 */
922 re_reset(sc);
923 if_attach(ifp);
924 ether_ifattach(ifp);
925
926 /* Perform hardware diagnostic. */
927 error = re_diag(sc);
928
929 if (error) {
930 printf("%s: attach aborted due to hardware diag failure\n",
931 sc->sc_dev.dv_xname);
932 ether_ifdetach(ifp);
933 return;
934 }
935
936 DPRINTF(("leaving re_attach\n"));
937 }
938
939
940 int
re_newbuf(sc,idx,m)941 re_newbuf(sc, idx, m)
942 struct rl_softc *sc;
943 int idx;
944 struct mbuf *m;
945 {
946 struct mbuf *n = NULL;
947 bus_dmamap_t map;
948 struct rl_desc *d;
949 u_int32_t cmdstat;
950 int error;
951
952 if (m == NULL) {
953 MGETHDR(n, M_DONTWAIT, MT_DATA);
954 if (n == NULL)
955 return (ENOBUFS);
956 m = n;
957
958 MCLGET(m, M_DONTWAIT);
959 if (! (m->m_flags & M_EXT)) {
960 m_freem(m);
961 return (ENOBUFS);
962 }
963 } else
964 m->m_data = m->m_ext.ext_buf;
965
966 /*
967 * Initialize mbuf length fields and fixup
968 * alignment so that the frame payload is
969 * longword aligned.
970 */
971 m->m_len = m->m_pkthdr.len = MCLBYTES;
972 m_adj(m, ETHER_ALIGN);
973
974 map = sc->rl_ldata.rl_rx_dmamap[idx];
975 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT);
976
977 if (map->dm_nsegs > 1)
978 goto out;
979 if (error)
980 goto out;
981
982 d = &sc->rl_ldata.rl_rx_list[idx];
983 if (letoh32(d->rl_cmdstat) & RL_RDESC_STAT_OWN)
984 goto out;
985
986 cmdstat = map->dm_segs[0].ds_len;
987 d->rl_bufaddr_lo = htole32(RL_ADDR_LO(map->dm_segs[0].ds_addr));
988 d->rl_bufaddr_hi = htole32(RL_ADDR_HI(map->dm_segs[0].ds_addr));
989 cmdstat |= RL_TDESC_CMD_SOF;
990 if (idx == (RL_RX_DESC_CNT - 1))
991 cmdstat |= RL_TDESC_CMD_EOR;
992 d->rl_cmdstat = htole32(cmdstat);
993
994 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
995
996 sc->rl_ldata.rl_rx_list[idx].rl_cmdstat |= htole32(RL_RDESC_CMD_OWN);
997 sc->rl_ldata.rl_rx_mbuf[idx] = m;
998
999 bus_dmamap_sync(sc->sc_dmat, sc->rl_ldata.rl_rx_dmamap[idx], 0,
1000 sc->rl_ldata.rl_rx_dmamap[idx]->dm_mapsize,
1001 BUS_DMASYNC_PREREAD);
1002
1003 return (0);
1004 out:
1005 if (n != NULL)
1006 m_freem(n);
1007 return (ENOMEM);
1008 }
1009
1010 int
re_tx_list_init(sc)1011 re_tx_list_init(sc)
1012 struct rl_softc *sc;
1013 {
1014 memset((char *)sc->rl_ldata.rl_tx_list, 0, RL_TX_LIST_SZ);
1015 memset((char *)&sc->rl_ldata.rl_tx_mbuf, 0,
1016 (RL_TX_DESC_CNT * sizeof(struct mbuf *)));
1017
1018 bus_dmamap_sync(sc->sc_dmat,
1019 sc->rl_ldata.rl_tx_list_map, 0,
1020 sc->rl_ldata.rl_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1021 sc->rl_ldata.rl_tx_prodidx = 0;
1022 sc->rl_ldata.rl_tx_considx = 0;
1023 sc->rl_ldata.rl_tx_free = RL_TX_DESC_CNT;
1024
1025 return (0);
1026 }
1027
1028 int
re_rx_list_init(sc)1029 re_rx_list_init(sc)
1030 struct rl_softc *sc;
1031 {
1032 int i;
1033
1034 memset((char *)sc->rl_ldata.rl_rx_list, 0, RL_RX_LIST_SZ);
1035 memset((char *)&sc->rl_ldata.rl_rx_mbuf, 0,
1036 (RL_RX_DESC_CNT * sizeof(struct mbuf *)));
1037
1038 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1039 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1040 return (ENOBUFS);
1041 }
1042
1043 /* Flush the RX descriptors */
1044
1045 bus_dmamap_sync(sc->sc_dmat,
1046 sc->rl_ldata.rl_rx_list_map,
1047 0, sc->rl_ldata.rl_rx_list_map->dm_mapsize,
1048 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1049
1050 sc->rl_ldata.rl_rx_prodidx = 0;
1051 sc->rl_head = sc->rl_tail = NULL;
1052
1053 return (0);
1054 }
1055
1056 /*
1057 * RX handler for C+ and 8169. For the gigE chips, we support
1058 * the reception of jumbo frames that have been fragmented
1059 * across multiple 2K mbuf cluster buffers.
1060 */
1061 void
re_rxeof(sc)1062 re_rxeof(sc)
1063 struct rl_softc *sc;
1064 {
1065 struct mbuf *m;
1066 struct ifnet *ifp;
1067 int i, total_len;
1068 struct rl_desc *cur_rx;
1069 #ifdef RE_VLAN
1070 struct m_tag *mtag;
1071 #endif
1072 u_int32_t rxstat, rxvlan;
1073
1074 ifp = &sc->sc_arpcom.ac_if;
1075 i = sc->rl_ldata.rl_rx_prodidx;
1076
1077 /* Invalidate the descriptor memory */
1078
1079 bus_dmamap_sync(sc->sc_dmat,
1080 sc->rl_ldata.rl_rx_list_map,
1081 0, sc->rl_ldata.rl_rx_list_map->dm_mapsize,
1082 BUS_DMASYNC_POSTREAD);
1083
1084 while (!RL_OWN(&sc->rl_ldata.rl_rx_list[i])) {
1085
1086 cur_rx = &sc->rl_ldata.rl_rx_list[i];
1087 m = sc->rl_ldata.rl_rx_mbuf[i];
1088 total_len = RL_RXBYTES(cur_rx);
1089 rxstat = letoh32(cur_rx->rl_cmdstat);
1090 rxvlan = letoh32(cur_rx->rl_vlanctl);
1091
1092 /* Invalidate the RX mbuf and unload its map */
1093
1094 bus_dmamap_sync(sc->sc_dmat,
1095 sc->rl_ldata.rl_rx_dmamap[i],
1096 0, sc->rl_ldata.rl_rx_dmamap[i]->dm_mapsize,
1097 BUS_DMASYNC_POSTWRITE);
1098 bus_dmamap_unload(sc->sc_dmat,
1099 sc->rl_ldata.rl_rx_dmamap[i]);
1100
1101 if (!(rxstat & RL_RDESC_STAT_EOF)) {
1102 m->m_len = MCLBYTES - ETHER_ALIGN;
1103 if (sc->rl_head == NULL)
1104 sc->rl_head = sc->rl_tail = m;
1105 else {
1106 m->m_flags &= ~M_PKTHDR;
1107 sc->rl_tail->m_next = m;
1108 sc->rl_tail = m;
1109 }
1110 re_newbuf(sc, i, NULL);
1111 RL_DESC_INC(i);
1112 continue;
1113 }
1114
1115 /*
1116 * NOTE: for the 8139C+, the frame length field
1117 * is always 12 bits in size, but for the gigE chips,
1118 * it is 13 bits (since the max RX frame length is 16K).
1119 * Unfortunately, all 32 bits in the status word
1120 * were already used, so to make room for the extra
1121 * length bit, RealTek took out the 'frame alignment
1122 * error' bit and shifted the other status bits
1123 * over one slot. The OWN, EOR, FS and LS bits are
1124 * still in the same places. We have already extracted
1125 * the frame length and checked the OWN bit, so rather
1126 * than using an alternate bit mapping, we shift the
1127 * status bits one space to the right so we can evaluate
1128 * them using the 8169 status as though it was in the
1129 * same format as that of the 8139C+.
1130 */
1131 if (sc->rl_type == RL_8169)
1132 rxstat >>= 1;
1133
1134 if (rxstat & RL_RDESC_STAT_RXERRSUM) {
1135 ifp->if_ierrors++;
1136 /*
1137 * If this is part of a multi-fragment packet,
1138 * discard all the pieces.
1139 */
1140 if (sc->rl_head != NULL) {
1141 m_freem(sc->rl_head);
1142 sc->rl_head = sc->rl_tail = NULL;
1143 }
1144 re_newbuf(sc, i, m);
1145 RL_DESC_INC(i);
1146 continue;
1147 }
1148
1149 /*
1150 * If allocating a replacement mbuf fails,
1151 * reload the current one.
1152 */
1153
1154 if (re_newbuf(sc, i, NULL)) {
1155 ifp->if_ierrors++;
1156 if (sc->rl_head != NULL) {
1157 m_freem(sc->rl_head);
1158 sc->rl_head = sc->rl_tail = NULL;
1159 }
1160 re_newbuf(sc, i, m);
1161 RL_DESC_INC(i);
1162 continue;
1163 }
1164
1165 RL_DESC_INC(i);
1166
1167 if (sc->rl_head != NULL) {
1168 m->m_len = total_len % (MCLBYTES - ETHER_ALIGN);
1169 /*
1170 * Special case: if there's 4 bytes or less
1171 * in this buffer, the mbuf can be discarded:
1172 * the last 4 bytes is the CRC, which we don't
1173 * care about anyway.
1174 */
1175 if (m->m_len <= ETHER_CRC_LEN) {
1176 sc->rl_tail->m_len -=
1177 (ETHER_CRC_LEN - m->m_len);
1178 m_freem(m);
1179 } else {
1180 m->m_len -= ETHER_CRC_LEN;
1181 m->m_flags &= ~M_PKTHDR;
1182 sc->rl_tail->m_next = m;
1183 }
1184 m = sc->rl_head;
1185 sc->rl_head = sc->rl_tail = NULL;
1186 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1187 } else
1188 m->m_pkthdr.len = m->m_len =
1189 (total_len - ETHER_CRC_LEN);
1190
1191 ifp->if_ipackets++;
1192 m->m_pkthdr.rcvif = ifp;
1193
1194 /* Do RX checksumming */
1195
1196 /* Check IP header checksum */
1197 if ((rxstat & RL_RDESC_STAT_PROTOID) &&
1198 !(rxstat & RL_RDESC_STAT_IPSUMBAD))
1199 m->m_pkthdr.csum |= M_IPV4_CSUM_IN_OK;
1200
1201 /* Check TCP/UDP checksum */
1202 if ((RL_TCPPKT(rxstat) &&
1203 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) ||
1204 (RL_UDPPKT(rxstat) &&
1205 !(rxstat & RL_RDESC_STAT_UDPSUMBAD)))
1206 m->m_pkthdr.csum |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK;
1207
1208 #ifdef RE_VLAN
1209 if (rxvlan & RL_RDESC_VLANCTL_TAG) {
1210 mtag = m_tag_get(PACKET_TAG_VLAN, sizeof(u_int),
1211 M_NOWAIT);
1212 if (mtag == NULL) {
1213 ifp->if_ierrors++;
1214 m_freem(m);
1215 continue;
1216 }
1217 *(u_int *)(mtag + 1) =
1218 be16toh(rxvlan & RL_RDESC_VLANCTL_DATA);
1219 m_tag_prepend(m, mtag);
1220 }
1221 #endif
1222 #if NBPFILTER > 0
1223 if (ifp->if_bpf)
1224 bpf_mtap(ifp->if_bpf, m);
1225 #endif
1226 ether_input_mbuf(ifp, m);
1227 }
1228
1229 /* Flush the RX DMA ring */
1230
1231 bus_dmamap_sync(sc->sc_dmat,
1232 sc->rl_ldata.rl_rx_list_map,
1233 0, sc->rl_ldata.rl_rx_list_map->dm_mapsize,
1234 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1235
1236 sc->rl_ldata.rl_rx_prodidx = i;
1237 }
1238
1239 void
re_txeof(sc)1240 re_txeof(sc)
1241 struct rl_softc *sc;
1242 {
1243 struct ifnet *ifp;
1244 u_int32_t txstat;
1245 int idx;
1246
1247 ifp = &sc->sc_arpcom.ac_if;
1248 idx = sc->rl_ldata.rl_tx_considx;
1249
1250 /* Invalidate the TX descriptor list */
1251
1252 bus_dmamap_sync(sc->sc_dmat,
1253 sc->rl_ldata.rl_tx_list_map,
1254 0, sc->rl_ldata.rl_tx_list_map->dm_mapsize,
1255 BUS_DMASYNC_POSTREAD);
1256
1257 while (idx != sc->rl_ldata.rl_tx_prodidx) {
1258
1259 txstat = letoh32(sc->rl_ldata.rl_tx_list[idx].rl_cmdstat);
1260 if (txstat & RL_TDESC_CMD_OWN)
1261 break;
1262
1263 /*
1264 * We only stash mbufs in the last descriptor
1265 * in a fragment chain, which also happens to
1266 * be the only place where the TX status bits
1267 * are valid.
1268 */
1269
1270 if (txstat & RL_TDESC_CMD_EOF) {
1271 m_freem(sc->rl_ldata.rl_tx_mbuf[idx]);
1272 sc->rl_ldata.rl_tx_mbuf[idx] = NULL;
1273 bus_dmamap_unload(sc->sc_dmat,
1274 sc->rl_ldata.rl_tx_dmamap[idx]);
1275 if (txstat & (RL_TDESC_STAT_EXCESSCOL|
1276 RL_TDESC_STAT_COLCNT))
1277 ifp->if_collisions++;
1278 if (txstat & RL_TDESC_STAT_TXERRSUM)
1279 ifp->if_oerrors++;
1280 else
1281 ifp->if_opackets++;
1282 }
1283 sc->rl_ldata.rl_tx_free++;
1284 RL_DESC_INC(idx);
1285 }
1286
1287 /* No changes made to the TX ring, so no flush needed */
1288
1289 if (idx != sc->rl_ldata.rl_tx_considx) {
1290 sc->rl_ldata.rl_tx_considx = idx;
1291 ifp->if_flags &= ~IFF_OACTIVE;
1292 ifp->if_timer = 0;
1293 }
1294
1295 /*
1296 * If not all descriptors have been released reaped yet,
1297 * reload the timer so that we will eventually get another
1298 * interrupt that will cause us to re-enter this routine.
1299 * This is done in case the transmitter has gone idle.
1300 */
1301 if (sc->rl_ldata.rl_tx_free != RL_TX_DESC_CNT)
1302 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1303 }
1304
1305 void
re_tick(xsc)1306 re_tick(xsc)
1307 void *xsc;
1308 {
1309 struct rl_softc *sc = xsc;
1310 int s = splnet();
1311
1312 mii_tick(&sc->sc_mii);
1313 splx(s);
1314
1315 timeout_add(&sc->timer_handle, hz);
1316 }
1317
1318 #ifdef DEVICE_POLLING
1319 void
re_poll(struct ifnet * ifp,enum poll_cmd cmd,int count)1320 re_poll (struct ifnet *ifp, enum poll_cmd cmd, int count)
1321 {
1322 struct rl_softc *sc = ifp->if_softc;
1323
1324 RL_LOCK(sc);
1325 if (!(ifp->if_capenable & IFCAP_POLLING)) {
1326 ether_poll_deregister(ifp);
1327 cmd = POLL_DEREGISTER;
1328 }
1329 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */
1330 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1331 goto done;
1332 }
1333
1334 sc->rxcycles = count;
1335 re_rxeof(sc);
1336 re_txeof(sc);
1337
1338 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1339 (*ifp->if_start)(ifp);
1340
1341 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
1342 u_int16_t status;
1343
1344 status = CSR_READ_2(sc, RL_ISR);
1345 if (status == 0xffff)
1346 goto done;
1347 if (status)
1348 CSR_WRITE_2(sc, RL_ISR, status);
1349
1350 /*
1351 * XXX check behaviour on receiver stalls.
1352 */
1353
1354 if (status & RL_ISR_SYSTEM_ERR) {
1355 re_reset(sc);
1356 re_init(ifp);
1357 }
1358 }
1359 done:
1360 RL_UNLOCK(sc);
1361 }
1362 #endif /* DEVICE_POLLING */
1363
1364 int
re_intr(arg)1365 re_intr(arg)
1366 void *arg;
1367 {
1368 struct rl_softc *sc = arg;
1369 struct ifnet *ifp;
1370 u_int16_t status;
1371 int claimed = 0;
1372
1373 ifp = &sc->sc_arpcom.ac_if;
1374
1375 if (!(ifp->if_flags & IFF_UP))
1376 return (0);
1377
1378 #ifdef DEVICE_POLLING
1379 if (ifp->if_flags & IFF_POLLING)
1380 goto done;
1381 if ((ifp->if_capenable & IFCAP_POLLING) &&
1382 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */
1383 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1384 re_poll(ifp, 0, 1);
1385 goto done;
1386 }
1387 #endif /* DEVICE_POLLING */
1388
1389 for (;;) {
1390
1391 status = CSR_READ_2(sc, RL_ISR);
1392 /* If the card has gone away the read returns 0xffff. */
1393 if (status == 0xffff)
1394 break;
1395 if (status) {
1396 claimed = 1;
1397 CSR_WRITE_2(sc, RL_ISR, status);
1398 }
1399
1400 if ((status & RL_INTRS_CPLUS) == 0)
1401 break;
1402
1403 if ((status & RL_ISR_RX_OK) ||
1404 (status & RL_ISR_RX_ERR))
1405 re_rxeof(sc);
1406
1407 if ((status & RL_ISR_TIMEOUT_EXPIRED) ||
1408 (status & RL_ISR_TX_ERR) ||
1409 (status & RL_ISR_TX_DESC_UNAVAIL))
1410 re_txeof(sc);
1411
1412 if (status & RL_ISR_SYSTEM_ERR) {
1413 re_reset(sc);
1414 re_init(ifp);
1415 }
1416
1417 if (status & RL_ISR_LINKCHG) {
1418 timeout_del(&sc->timer_handle);
1419 re_tick(sc);
1420 }
1421 }
1422
1423 if (!IFQ_IS_EMPTY(&ifp->if_snd))
1424 (*ifp->if_start)(ifp);
1425
1426 #ifdef DEVICE_POLLING
1427 done:
1428 #endif
1429
1430 return (claimed);
1431 }
1432
1433 int
re_encap(sc,m_head,idx)1434 re_encap(sc, m_head, idx)
1435 struct rl_softc *sc;
1436 struct mbuf *m_head;
1437 int *idx;
1438 {
1439 bus_dmamap_t map;
1440 int error, i, curidx;
1441 #ifdef RE_VLAN
1442 struct m_tag *mtag;
1443 #endif
1444 struct rl_desc *d;
1445 u_int32_t cmdstat, rl_flags = 0;
1446
1447 if (sc->rl_ldata.rl_tx_free <= 4)
1448 return (EFBIG);
1449
1450 #ifdef RE_CSUM_OFFLOAD
1451 /*
1452 * Set up checksum offload. Note: checksum offload bits must
1453 * appear in all descriptors of a multi-descriptor transmit
1454 * attempt. (This is according to testing done with an 8169
1455 * chip. I'm not sure if this is a requirement or a bug.)
1456 */
1457
1458 /*
1459 * Set RL_TDESC_CMD_IPCSUM if any checksum offloading
1460 * is requested. Otherwise, RL_TDESC_CMD_TCPCSUM/
1461 * RL_TDESC_CMD_UDPCSUM does not take affect.
1462 */
1463
1464 if ((m_head->m_pkthdr.csum &
1465 (M_IPV4_CSUM_OUT|M_TCPV4_CSUM_OUT|M_UDPV4_CSUM_OUT)) != 0) {
1466 rl_flags |= RL_TDESC_CMD_IPCSUM;
1467 if (m_head->m_pkthdr.csum & M_TCPV4_CSUM_OUT)
1468 rl_flags |= RL_TDESC_CMD_TCPCSUM;
1469 if (m_head->m_pkthdr.csum & M_UDPV4_CSUM_OUT)
1470 rl_flags |= RL_TDESC_CMD_UDPCSUM;
1471 }
1472 #endif
1473
1474 map = sc->rl_ldata.rl_tx_dmamap[*idx];
1475 error = bus_dmamap_load_mbuf(sc->sc_dmat, map,
1476 m_head, BUS_DMA_NOWAIT);
1477
1478 if (error) {
1479 printf("%s: can't map mbuf (error %d)\n",
1480 sc->sc_dev.dv_xname, error);
1481 return (ENOBUFS);
1482 }
1483
1484 if (map->dm_nsegs > sc->rl_ldata.rl_tx_free - 4)
1485 return (ENOBUFS);
1486 /*
1487 * Map the segment array into descriptors. Note that we set the
1488 * start-of-frame and end-of-frame markers for either TX or RX, but
1489 * they really only have meaning in the TX case. (In the RX case,
1490 * it's the chip that tells us where packets begin and end.)
1491 * We also keep track of the end of the ring and set the
1492 * end-of-ring bits as needed, and we set the ownership bits
1493 * in all except the very first descriptor. (The caller will
1494 * set this descriptor later when it start transmission or
1495 * reception.)
1496 */
1497 i = 0;
1498 curidx = *idx;
1499 while (1) {
1500 d = &sc->rl_ldata.rl_tx_list[curidx];
1501 if (letoh32(d->rl_cmdstat) & RL_RDESC_STAT_OWN)
1502 return (ENOBUFS);
1503
1504 cmdstat = map->dm_segs[i].ds_len;
1505 d->rl_bufaddr_lo =
1506 htole32(RL_ADDR_LO(map->dm_segs[i].ds_addr));
1507 d->rl_bufaddr_hi =
1508 htole32(RL_ADDR_HI(map->dm_segs[i].ds_addr));
1509 if (i == 0)
1510 cmdstat |= RL_TDESC_CMD_SOF;
1511 else
1512 cmdstat |= RL_TDESC_CMD_OWN;
1513 if (curidx == (RL_RX_DESC_CNT - 1))
1514 cmdstat |= RL_TDESC_CMD_EOR;
1515 d->rl_cmdstat = htole32(cmdstat | rl_flags);
1516 i++;
1517 if (i == map->dm_nsegs)
1518 break;
1519 RL_DESC_INC(curidx);
1520 }
1521
1522 d->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF);
1523
1524 /*
1525 * Ensure that the map for this transmission
1526 * is placed at the array index of the last descriptor
1527 * in this chain.
1528 */
1529 sc->rl_ldata.rl_tx_dmamap[*idx] =
1530 sc->rl_ldata.rl_tx_dmamap[curidx];
1531 sc->rl_ldata.rl_tx_dmamap[curidx] = map;
1532 sc->rl_ldata.rl_tx_mbuf[curidx] = m_head;
1533 sc->rl_ldata.rl_tx_free -= map->dm_nsegs;
1534
1535 /*
1536 * Set up hardware VLAN tagging. Note: vlan tag info must
1537 * appear in the first descriptor of a multi-descriptor
1538 * transmission attempt.
1539 */
1540
1541 #ifdef RE_VLAN
1542 if (sc->ethercom.ec_nvlans &&
1543 (mtag = m_tag_find(m_head, PACKET_TAG_VLAN, NULL)) != NULL)
1544 sc->rl_ldata.rl_tx_list[*idx].rl_vlanctl =
1545 htole32(htons(*(u_int *)(mtag + 1)) |
1546 RL_TDESC_VLANCTL_TAG);
1547 #endif
1548
1549 /* Transfer ownership of packet to the chip. */
1550
1551 sc->rl_ldata.rl_tx_list[curidx].rl_cmdstat |=
1552 htole32(RL_TDESC_CMD_OWN);
1553 if (*idx != curidx)
1554 sc->rl_ldata.rl_tx_list[*idx].rl_cmdstat |=
1555 htole32(RL_TDESC_CMD_OWN);
1556
1557 RL_DESC_INC(curidx);
1558 *idx = curidx;
1559
1560 return (0);
1561 }
1562
1563 /*
1564 * Main transmit routine for C+ and gigE NICs.
1565 */
1566
1567 void
re_start(ifp)1568 re_start(ifp)
1569 struct ifnet *ifp;
1570 {
1571 struct rl_softc *sc;
1572 struct mbuf *m_head = NULL;
1573 int idx;
1574
1575 sc = ifp->if_softc;
1576
1577 idx = sc->rl_ldata.rl_tx_prodidx;
1578 while (sc->rl_ldata.rl_tx_mbuf[idx] == NULL) {
1579 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1580 if (m_head == NULL)
1581 break;
1582
1583 if (re_encap(sc, m_head, &idx)) {
1584 IF_PREPEND(&ifp->if_snd, m_head);
1585 ifp->if_flags |= IFF_OACTIVE;
1586 break;
1587 }
1588 #if NBPFILTER > 0
1589 /*
1590 * If there's a BPF listener, bounce a copy of this frame
1591 * to him.
1592 */
1593 if (ifp->if_bpf)
1594 bpf_mtap(ifp->if_bpf, m_head);
1595 #endif
1596 }
1597
1598 /* Flush the TX descriptors */
1599
1600 bus_dmamap_sync(sc->sc_dmat,
1601 sc->rl_ldata.rl_tx_list_map,
1602 0, sc->rl_ldata.rl_tx_list_map->dm_mapsize,
1603 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
1604
1605 sc->rl_ldata.rl_tx_prodidx = idx;
1606
1607 /*
1608 * RealTek put the TX poll request register in a different
1609 * location on the 8169 gigE chip. I don't know why.
1610 */
1611
1612 if (sc->rl_type == RL_8169)
1613 CSR_WRITE_2(sc, RL_GTXSTART, RL_TXSTART_START);
1614 else
1615 CSR_WRITE_2(sc, RL_TXSTART, RL_TXSTART_START);
1616
1617 /*
1618 * Use the countdown timer for interrupt moderation.
1619 * 'TX done' interrupts are disabled. Instead, we reset the
1620 * countdown timer, which will begin counting until it hits
1621 * the value in the TIMERINT register, and then trigger an
1622 * interrupt. Each time we write to the TIMERCNT register,
1623 * the timer count is reset to 0.
1624 */
1625 CSR_WRITE_4(sc, RL_TIMERCNT, 1);
1626
1627 /*
1628 * Set a timeout in case the chip goes out to lunch.
1629 */
1630 ifp->if_timer = 5;
1631 }
1632
1633 int
re_init(struct ifnet * ifp)1634 re_init(struct ifnet *ifp)
1635 {
1636 struct rl_softc *sc = ifp->if_softc;
1637 u_int32_t rxcfg = 0;
1638 u_int32_t reg;
1639 int s;
1640
1641 s = splimp();
1642
1643 /*
1644 * Cancel pending I/O and free all RX/TX buffers.
1645 */
1646 re_stop(sc);
1647
1648 /*
1649 * Enable C+ RX and TX mode, as well as VLAN stripping and
1650 * RX checksum offload. We must configure the C+ register
1651 * before all others.
1652 */
1653 CSR_WRITE_2(sc, RL_CPLUS_CMD, RL_CPLUSCMD_RXENB|
1654 RL_CPLUSCMD_TXENB|RL_CPLUSCMD_PCI_MRW|
1655 RL_CPLUSCMD_VLANSTRIP|RL_CPLUSCMD_RXCSUM_ENB);
1656
1657 /*
1658 * Init our MAC address. Even though the chipset
1659 * documentation doesn't mention it, we need to enter "Config
1660 * register write enable" mode to modify the ID registers.
1661 */
1662 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
1663 memcpy(®, LLADDR(ifp->if_sadl), 4);
1664 CSR_WRITE_4(sc, RL_IDR0, htole32(reg));
1665 reg = 0;
1666 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4);
1667 CSR_WRITE_4(sc, RL_IDR4, htole32(reg));
1668 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
1669
1670 /*
1671 * For C+ mode, initialize the RX descriptors and mbufs.
1672 */
1673 re_rx_list_init(sc);
1674 re_tx_list_init(sc);
1675
1676 /*
1677 * Enable transmit and receive.
1678 */
1679 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1680
1681 /*
1682 * Set the initial TX and RX configuration.
1683 */
1684 if (sc->rl_testmode) {
1685 if (sc->rl_type == RL_8169)
1686 CSR_WRITE_4(sc, RL_TXCFG,
1687 RL_TXCFG_CONFIG|RL_LOOPTEST_ON);
1688 else
1689 CSR_WRITE_4(sc, RL_TXCFG,
1690 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS);
1691 } else
1692 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG);
1693 CSR_WRITE_4(sc, RL_RXCFG, RL_RXCFG_CONFIG);
1694
1695 /* Set the individual bit to receive frames for this host only. */
1696 rxcfg = CSR_READ_4(sc, RL_RXCFG);
1697 rxcfg |= RL_RXCFG_RX_INDIV;
1698
1699 /* If we want promiscuous mode, set the allframes bit. */
1700 if (ifp->if_flags & IFF_PROMISC)
1701 rxcfg |= RL_RXCFG_RX_ALLPHYS;
1702 else
1703 rxcfg &= ~RL_RXCFG_RX_ALLPHYS;
1704 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1705
1706 /*
1707 * Set capture broadcast bit to capture broadcast frames.
1708 */
1709 if (ifp->if_flags & IFF_BROADCAST)
1710 rxcfg |= RL_RXCFG_RX_BROAD;
1711 else
1712 rxcfg &= ~RL_RXCFG_RX_BROAD;
1713 CSR_WRITE_4(sc, RL_RXCFG, rxcfg);
1714
1715 /*
1716 * Program the multicast filter, if necessary.
1717 */
1718 re_setmulti(sc);
1719
1720 #ifdef DEVICE_POLLING
1721 /*
1722 * Disable interrupts if we are polling.
1723 */
1724 if (ifp->if_flags & IFF_POLLING)
1725 CSR_WRITE_2(sc, RL_IMR, 0);
1726 else /* otherwise ... */
1727 #endif /* DEVICE_POLLING */
1728 /*
1729 * Enable interrupts.
1730 */
1731 if (sc->rl_testmode)
1732 CSR_WRITE_2(sc, RL_IMR, 0);
1733 else
1734 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
1735
1736 /* Start RX/TX process. */
1737 CSR_WRITE_4(sc, RL_MISSEDPKT, 0);
1738 #ifdef notdef
1739 /* Enable receiver and transmitter. */
1740 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB);
1741 #endif
1742 /*
1743 * Load the addresses of the RX and TX lists into the chip.
1744 */
1745
1746 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI,
1747 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr));
1748 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO,
1749 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_map->dm_segs[0].ds_addr));
1750
1751 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI,
1752 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr));
1753 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO,
1754 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_map->dm_segs[0].ds_addr));
1755
1756 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);
1757
1758 /*
1759 * Initialize the timer interrupt register so that
1760 * a timer interrupt will be generated once the timer
1761 * reaches a certain number of ticks. The timer is
1762 * reloaded on each transmit. This gives us TX interrupt
1763 * moderation, which dramatically improves TX frame rate.
1764 */
1765
1766 if (sc->rl_type == RL_8169)
1767 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800);
1768 else
1769 CSR_WRITE_4(sc, RL_TIMERINT, 0x400);
1770
1771 /*
1772 * For 8169 gigE NICs, set the max allowed RX packet
1773 * size so we can receive jumbo frames.
1774 */
1775 if (sc->rl_type == RL_8169)
1776 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383);
1777
1778 if (sc->rl_testmode)
1779 return (0);
1780
1781 mii_mediachg(&sc->sc_mii);
1782
1783 CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
1784
1785 ifp->if_flags |= IFF_RUNNING;
1786 ifp->if_flags &= ~IFF_OACTIVE;
1787
1788 splx(s);
1789
1790 timeout_add(&sc->timer_handle, hz);
1791
1792 return (0);
1793 }
1794
1795 /*
1796 * Set media options.
1797 */
1798 int
re_ifmedia_upd(ifp)1799 re_ifmedia_upd(ifp)
1800 struct ifnet *ifp;
1801 {
1802 struct rl_softc *sc;
1803
1804 sc = ifp->if_softc;
1805
1806 return (mii_mediachg(&sc->sc_mii));
1807 }
1808
1809 /*
1810 * Report current media status.
1811 */
1812 void
re_ifmedia_sts(ifp,ifmr)1813 re_ifmedia_sts(ifp, ifmr)
1814 struct ifnet *ifp;
1815 struct ifmediareq *ifmr;
1816 {
1817 struct rl_softc *sc;
1818
1819 sc = ifp->if_softc;
1820
1821 mii_pollstat(&sc->sc_mii);
1822 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1823 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1824 }
1825
1826 int
re_ioctl(ifp,command,data)1827 re_ioctl(ifp, command, data)
1828 struct ifnet *ifp;
1829 u_long command;
1830 caddr_t data;
1831 {
1832 struct rl_softc *sc = ifp->if_softc;
1833 struct ifreq *ifr = (struct ifreq *) data;
1834 struct ifaddr *ifa = (struct ifaddr *)data;
1835 int s, error = 0;
1836
1837 s = splimp();
1838
1839 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, command,
1840 data)) > 0) {
1841 splx(s);
1842 return (error);
1843 }
1844
1845 switch(command) {
1846 case SIOCSIFADDR:
1847 ifp->if_flags |= IFF_UP;
1848 switch (ifa->ifa_addr->sa_family) {
1849 #ifdef INET
1850 case AF_INET:
1851 re_init(ifp);
1852 arp_ifinit(&sc->sc_arpcom, ifa);
1853 break;
1854 #endif /* INET */
1855 default:
1856 re_init(ifp);
1857 break;
1858 }
1859 break;
1860 case SIOCSIFMTU:
1861 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RL_JUMBO_MTU)
1862 error = EINVAL;
1863 else if (ifp->if_mtu != ifr->ifr_mtu)
1864 ifp->if_mtu = ifr->ifr_mtu;
1865 break;
1866 case SIOCSIFFLAGS:
1867 if (ifp->if_flags & IFF_UP) {
1868 re_init(ifp);
1869 } else {
1870 if (ifp->if_flags & IFF_RUNNING)
1871 re_stop(sc);
1872 }
1873 error = 0;
1874 break;
1875 case SIOCADDMULTI:
1876 case SIOCDELMULTI:
1877 error = (command == SIOCADDMULTI) ?
1878 ether_addmulti(ifr, &sc->sc_arpcom) :
1879 ether_delmulti(ifr, &sc->sc_arpcom);
1880 if (error == ENETRESET) {
1881 /*
1882 * Multicast list has changed; set the hardware
1883 * filter accordingly.
1884 */
1885 if (ifp->if_flags & IFF_RUNNING)
1886 re_setmulti(sc);
1887 error = 0;
1888 }
1889 break;
1890 case SIOCGIFMEDIA:
1891 case SIOCSIFMEDIA:
1892 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command);
1893 break;
1894 default:
1895 error = EINVAL;
1896 break;
1897 }
1898
1899 splx(s);
1900
1901 return (error);
1902 }
1903
1904 void
re_watchdog(ifp)1905 re_watchdog(ifp)
1906 struct ifnet *ifp;
1907 {
1908 struct rl_softc *sc;
1909 int s;
1910
1911 sc = ifp->if_softc;
1912 s = splnet();
1913 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname);
1914 ifp->if_oerrors++;
1915
1916 re_txeof(sc);
1917 re_rxeof(sc);
1918
1919 re_init(ifp);
1920
1921 splx(s);
1922 }
1923
1924 /*
1925 * Stop the adapter and free any mbufs allocated to the
1926 * RX and TX lists.
1927 */
1928 void
re_stop(sc)1929 re_stop(sc)
1930 struct rl_softc *sc;
1931 {
1932 register int i;
1933 struct ifnet *ifp;
1934
1935 ifp = &sc->sc_arpcom.ac_if;
1936 ifp->if_timer = 0;
1937
1938 timeout_del(&sc->timer_handle);
1939 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1940 #ifdef DEVICE_POLLING
1941 ether_poll_deregister(ifp);
1942 #endif /* DEVICE_POLLING */
1943
1944 CSR_WRITE_1(sc, RL_COMMAND, 0x00);
1945 CSR_WRITE_2(sc, RL_IMR, 0x0000);
1946
1947 if (sc->rl_head != NULL) {
1948 m_freem(sc->rl_head);
1949 sc->rl_head = sc->rl_tail = NULL;
1950 }
1951
1952 /* Free the TX list buffers. */
1953
1954 for (i = 0; i < RL_TX_DESC_CNT; i++) {
1955 if (sc->rl_ldata.rl_tx_mbuf[i] != NULL) {
1956 bus_dmamap_unload(sc->sc_dmat,
1957 sc->rl_ldata.rl_tx_dmamap[i]);
1958 m_freem(sc->rl_ldata.rl_tx_mbuf[i]);
1959 sc->rl_ldata.rl_tx_mbuf[i] = NULL;
1960 }
1961 }
1962
1963 /* Free the RX list buffers. */
1964
1965 for (i = 0; i < RL_RX_DESC_CNT; i++) {
1966 if (sc->rl_ldata.rl_rx_mbuf[i] != NULL) {
1967 bus_dmamap_unload(sc->sc_dmat,
1968 sc->rl_ldata.rl_rx_dmamap[i]);
1969 m_freem(sc->rl_ldata.rl_rx_mbuf[i]);
1970 sc->rl_ldata.rl_rx_mbuf[i] = NULL;
1971 }
1972 }
1973 }
1974