1 /* $OpenBSD: pdqreg.h,v 1.9 2002/06/02 22:50:00 deraadt Exp $ */ 2 /* $NetBSD: pdqreg.h,v 1.6 1996/08/28 16:01:29 cgd Exp $ */ 3 4 /*- 5 * Copyright (c) 1995, 1996 Matt Thomas <matt@3am-software.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. The name of the author may not be used to endorse or promote products 14 * derived from this software without specific prior written permission 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Id: pdqreg.h,v 1.9 1996/05/16 14:25:26 thomas Exp 28 * 29 */ 30 31 /* 32 * DEC PDQ FDDI Controller; PDQ port driver definitions 33 * 34 */ 35 36 #ifndef _PDQREG_H 37 #define _PDQREG_H 38 39 #if !defined(__NetBSD__) && !defined(__OpenBSD__) 40 #include <stddef.h> 41 #if defined(PDQTEST) && !defined(PDQ_NDEBUG) 42 #include <assert.h> 43 #define PDQ_ASSERT assert 44 #else 45 #define PDQ_ASSERT(x) do { } while(0) 46 #endif 47 #else /* __NetBSD__ || __OpenBSD__*/ 48 49 /* 50 * Can't directly use "assert", because apparently cpp won't expand it 51 * unless it has an argument, which loses. 52 */ 53 #ifdef PDQ_NDEBUG 54 #define PDQ_ASSERT(e) ((void)0) 55 #else 56 #ifdef __STDC__ 57 #define PDQ_ASSERT(e) ((e) ? (void)0 : \ 58 __assert("PDQ ", __FILE__, __LINE__, #e)) 59 #else 60 #define PDQ_ASSERT(e) ((e) ? (void)0 : \ 61 __assert("PDQ ", __FILE__, __LINE__, "e")) 62 #endif 63 #endif 64 #endif /* __NetBSD__ || __OpenBSD__ */ 65 66 #define PDQ_RING_SIZE(array) ((sizeof(array) / sizeof(array[0]))) 67 #define PDQ_ARRAY_SIZE(array) ((sizeof(array) / sizeof(array[0]))) 68 #define PDQ_RING_MASK(array) (PDQ_RING_SIZE(array) - 1) 69 #define PDQ_BITMASK(n) (1L << (pdq_uint32_t) (n)) 70 71 #define PDQ_FDDI_MAX 4495 72 #define PDQ_FDDI_LLC_MIN 20 73 #define PDQ_FDDI_SMT_MIN 37 74 75 #define PDQ_FDDI_SMT 0x40 76 #define PDQ_FDDI_LLC_ASYNC 0x50 77 #define PDQ_FDDI_LLC_SYNC 0xD0 78 #define PDQ_FDDI_IMP_ASYNC 0x60 79 #define PDQ_FDDI_IMP_SYNC 0xE0 80 81 #define PDQ_FDDIFC_C 0x80 82 #define PDQ_FDDIFC_L 0x40 83 #define PDQ_FDDIFC_F 0x30 84 #define PDQ_FDDIFC_Z 0x0F 85 86 #define PDQ_FDDI_PH0 0x20 87 #define PDQ_FDDI_PH1 0x38 88 #define PDQ_FDDI_PH2 0x00 89 90 typedef pdq_uint32_t pdq_physaddr_t; 91 92 struct _pdq_lanaddr_t { 93 pdq_uint8_t lanaddr_bytes[8]; 94 }; 95 96 typedef struct { 97 pdq_uint8_t fwrev_bytes[4]; 98 } pdq_fwrev_t; 99 100 enum _pdq_state_t { 101 PDQS_RESET=0, 102 PDQS_UPGRADE=1, 103 PDQS_DMA_UNAVAILABLE=2, 104 PDQS_DMA_AVAILABLE=3, 105 PDQS_LINK_AVAILABLE=4, 106 PDQS_LINK_UNAVAILABLE=5, 107 PDQS_HALTED=6, 108 PDQS_RING_MEMBER=7 109 }; 110 111 struct _pdq_csrs_t { 112 pdq_bus_memoffset_t csr_port_reset; /* 0x00 [RW] */ 113 pdq_bus_memoffset_t csr_host_data; /* 0x04 [R] */ 114 pdq_bus_memoffset_t csr_port_control; /* 0x08 [RW] */ 115 pdq_bus_memoffset_t csr_port_data_a; /* 0x0C [RW] */ 116 pdq_bus_memoffset_t csr_port_data_b; /* 0x10 [RW] */ 117 pdq_bus_memoffset_t csr_port_status; /* 0x14 [R] */ 118 pdq_bus_memoffset_t csr_host_int_type_0; /* 0x18 [RW] */ 119 pdq_bus_memoffset_t csr_host_int_enable; /* 0x1C [RW] */ 120 pdq_bus_memoffset_t csr_type_2_producer; /* 0x20 [RW] */ 121 pdq_bus_memoffset_t csr_cmd_response_producer; /* 0x28 [RW] */ 122 pdq_bus_memoffset_t csr_cmd_request_producer; /* 0x2C [RW] */ 123 pdq_bus_memoffset_t csr_host_smt_producer; /* 0x30 [RW] */ 124 pdq_bus_memoffset_t csr_unsolicited_producer; /* 0x34 [RW] */ 125 pdq_bus_t csr_bus; 126 pdq_bus_memaddr_t csr_base; 127 }; 128 129 struct _pdq_pci_csrs_t { 130 pdq_bus_memoffset_t csr_pfi_mode_control; /* 0x40 [RW] */ 131 pdq_bus_memoffset_t csr_pfi_status; /* 0x44 [RW] */ 132 pdq_bus_memoffset_t csr_fifo_write; /* 0x48 [RW] */ 133 pdq_bus_memoffset_t csr_fifo_read; /* 0x4C [RW] */ 134 pdq_bus_t csr_bus; 135 pdq_bus_memaddr_t csr_base; 136 }; 137 138 #define PDQ_PFI_MODE_DMA_ENABLE 0x01 /* DMA Enable */ 139 #define PDQ_PFI_MODE_PFI_PCI_INTR 0x02 /* PFI-to-PCI Int Enable */ 140 #define PDQ_PFI_MODE_PDQ_PCI_INTR 0x04 /* PDQ-to-PCI Int Enable */ 141 142 #define PDQ_PFI_STATUS_PDQ_INTR 0x10 /* PDQ Int received */ 143 #define PDQ_PFI_STATUS_DMA_ABORT 0x08 /* PDQ DMA Abort asserted */ 144 145 #define PDQ_EISA_BURST_HOLDOFF 0x0040 146 #define PDQ_EISA_SLOT_ID 0x0C80 147 #define PDQ_EISA_SLOT_CTRL 0x0C84 148 #define PDQ_EISA_MEM_ADD_CMP_0 0x0C85 149 #define PDQ_EISA_MEM_ADD_CMP_1 0x0C86 150 #define PDQ_EISA_MEM_ADD_CMP_2 0x0C87 151 #define PDQ_EISA_MEM_ADD_HI_CMP_0 0x0C88 152 #define PDQ_EISA_MEM_ADD_HI_CMP_1 0x0C89 153 #define PDQ_EISA_MEM_ADD_HI_CMP_2 0x0C8A 154 #define PDQ_EISA_MEM_ADD_MASK_0 0x0C8B 155 #define PDQ_EISA_MEM_ADD_MASK_1 0x0C8C 156 #define PDQ_EISA_MEM_ADD_MASK_2 0x0C8D 157 #define PDQ_EISA_MEM_ADD_LO_CMP_0 0x0C8E 158 #define PDQ_EISA_MEM_ADD_LO_CMP_1 0x0C8F 159 #define PDQ_EISA_MEM_ADD_LO_CMP_2 0x0C90 160 #define PDQ_EISA_IO_CMP_0_0 0x0C91 161 #define PDQ_EISA_IO_CMP_0_1 0x0C92 162 #define PDQ_EISA_IO_CMP_1_0 0x0C93 163 #define PDQ_EISA_IO_CMP_1_1 0x0C94 164 #define PDQ_EISA_IO_CMP_2_0 0x0C95 165 #define PDQ_EISA_IO_CMP_2_1 0x0C96 166 #define PDQ_EISA_IO_CMP_3_0 0x0C97 167 #define PDQ_EISA_IO_CMP_3_1 0x0C98 168 #define PDQ_EISA_IO_ADD_MASK_0_0 0x0C99 169 #define PDQ_EISA_IO_ADD_MASK_0_1 0x0C9A 170 #define PDQ_EISA_IO_ADD_MASK_1_0 0x0C9B 171 #define PDQ_EISA_IO_ADD_MASK_1_1 0x0C9C 172 #define PDQ_EISA_IO_ADD_MASK_2_0 0x0C9D 173 #define PDQ_EISA_IO_ADD_MASK_2_1 0x0C9E 174 #define PDQ_EISA_IO_ADD_MASK_3_0 0x0C9F 175 #define PDQ_EISA_IO_ADD_MASK_3_1 0x0CA0 176 #define PDQ_EISA_MOD_CONFIG_1 0x0CA1 177 #define PDQ_EISA_MOD_CONFIG_2 0x0CA2 178 #define PDQ_EISA_MOD_CONFIG_3 0x0CA3 179 #define PDQ_EISA_MOD_CONFIG_4 0x0CA4 180 #define PDQ_EISA_MOD_CONFIG_5 0x0CA5 181 #define PDQ_EISA_MOD_CONFIG_6 0x0CA6 182 #define PDQ_EISA_MOD_CONFIG_7 0x0CA7 183 #define PDQ_EISA_DIP_SWITCH 0x0CA8 184 #define PDQ_EISA_IO_CONFIG_STAT_0 0x0CA9 185 #define PDQ_EISA_IO_CONFIG_STAT_1 0x0CAA 186 #define PDQ_EISA_DMA_CONFIG 0x0CAB 187 #define PDQ_EISA_INPUT_PORT 0x0CAC 188 #define PDQ_EISA_OUTPUT_PORT 0x0CAD 189 #define PDQ_EISA_FUNCTION_CTRL 0x0CAE 190 191 #define PDQ_TC_CSR_OFFSET 0x00100000 192 #define PDQ_TC_CSR_SPACE 0x0040 193 #define PDQ_FBUS_CSR_OFFSET 0x00200000 194 #define PDQ_FBUS_CSR_SPACE 0x0080 195 196 /* 197 * Port Reset Data A Definitions 198 */ 199 #define PDQ_PRESET_SKIP_SELFTEST 0x0004 200 #define PDQ_PRESET_SOFT_RESET 0x0002 201 #define PDQ_PRESET_UPGRADE 0x0001 202 /* 203 * Port Control Register Definitions 204 */ 205 #define PDQ_PCTL_CMD_ERROR 0x8000 206 #define PDQ_PCTL_FLASH_BLAST 0x4000 207 #define PDQ_PCTL_HALT 0x2000 208 #define PDQ_PCTL_COPY_DATA 0x1000 209 #define PDQ_PCTL_ERROR_LOG_START 0x0800 210 #define PDQ_PCTL_ERROR_LOG_READ 0x0400 211 #define PDQ_PCTL_XMT_DATA_FLUSH_DONE 0x0200 212 #define PDQ_PCTL_DMA_INIT 0x0100 213 #define PDQ_DMA_INIT_LW_BSWAP_DATA 0x02 214 #define PDQ_DMA_INIT_LW_BSWAP_LITERAL 0x01 215 #define PDQ_PCTL_INIT_START 0x0080 216 #define PDQ_PCTL_CONSUMER_BLOCK 0x0040 217 #define PDQ_PCTL_DMA_UNINIT 0x0020 218 #define PDQ_PCTL_RING_MEMBER 0x0010 219 #define PDQ_PCTL_MLA_READ 0x0008 220 #define PDQ_PCTL_FW_REV_READ 0x0004 221 #define PDQ_PCTL_DEVICE_SPECIFIC 0x0002 222 #define PDQ_PCTL_SUB_CMD 0x0001 223 224 typedef enum { 225 PDQ_SUB_CMD_LINK_UNINIT=1, 226 PDQ_SUB_CMD_DMA_BURST_SIZE_SET=2, 227 PDQ_SUB_CMD_PDQ_REV_GET=4 228 } pdq_sub_cmd_t; 229 230 typedef enum { 231 PDQ_DMA_BURST_4LW=0, 232 PDQ_DMA_BURST_8LW=1, 233 PDQ_DMA_BURST_16LW=2, 234 PDQ_DMA_BURST_32LW=3 235 } pdq_dma_burst_size_t; 236 237 typedef enum { 238 PDQ_CHIP_REV_A_B_OR_C=0, 239 PDQ_CHIP_REV_D=2, 240 PDQ_CHIP_REV_E=4 241 } pdq_chip_rev_t; 242 /* 243 * Port Status Register Definitions 244 */ 245 #define PDQ_PSTS_RCV_DATA_PENDING 0x80000000ul 246 #define PDQ_PSTS_XMT_DATA_PENDING 0x40000000ul 247 #define PDQ_PSTS_HOST_SMT_PENDING 0x20000000ul 248 #define PDQ_PSTS_UNSOL_PENDING 0x10000000ul 249 #define PDQ_PSTS_CMD_RSP_PENDING 0x08000000ul 250 #define PDQ_PSTS_CMD_REQ_PENDING 0x04000000ul 251 #define PDQ_PSTS_TYPE_0_PENDING 0x02000000ul 252 #define PDQ_PSTS_INTR_PENDING 0xFE000000ul 253 #define PDQ_PSTS_ADAPTER_STATE(sts) ((pdq_state_t) (((sts) >> 8) & 0x07)) 254 #define PDQ_PSTS_HALT_ID(sts) ((pdq_halt_code_t) ((sts) & 0xFF)) 255 /* 256 * Host Interrupt Register Definitions 257 */ 258 #define PDQ_HOST_INT_TX_ENABLE 0x80000000ul 259 #define PDQ_HOST_INT_RX_ENABLE 0x40000000ul 260 #define PDQ_HOST_INT_UNSOL_ENABLE 0x20000000ul 261 #define PDQ_HOST_INT_HOST_SMT_ENABLE 0x10000000ul 262 #define PDQ_HOST_INT_CMD_RSP_ENABLE 0x08000000ul 263 #define PDQ_HOST_INT_CMD_RQST_ENABLE 0x04000000ul 264 265 #define PDQ_HOST_INT_1MS 0x80 266 #define PDQ_HOST_INT_20MS 0x40 267 #define PDQ_HOST_INT_CSR_CMD_DONE 0x20 268 #define PDQ_HOST_INT_STATE_CHANGE 0x10 269 #define PDQ_HOST_INT_XMT_DATA_FLUSH 0x08 270 #define PDQ_HOST_INT_NXM 0x04 271 #define PDQ_HOST_INT_PM_PARITY_ERROR 0x02 272 #define PDQ_HOST_INT_HOST_BUS_PARITY_ERROR 0x01 273 #define PDQ_HOST_INT_FATAL_ERROR 0x07 274 275 typedef enum { 276 PDQH_SELFTEST_TIMEOUT=0, 277 PDQH_HOST_BUS_PARITY_ERROR=1, 278 PDQH_HOST_DIRECTED_HALT=2, 279 PDQH_SOFTWARE_FAULT=3, 280 PDQH_HARDWARE_FAULT=4, 281 PDQH_PC_TRACE_PATH_TEST=5, 282 PDQH_DMA_ERROR=6, 283 PDQH_IMAGE_CRC_ERROR=7, 284 PDQH_ADAPTER_PROCESSOR_ERROR=8, 285 PDQH_MAX=9 286 } pdq_halt_code_t; 287 288 typedef struct { 289 pdq_uint16_t pdqcb_receives; 290 pdq_uint16_t pdqcb_transmits; 291 pdq_uint32_t pdqcb__filler1; 292 pdq_uint32_t pdqcb_host_smt; 293 pdq_uint32_t pdqcb__filler2; 294 pdq_uint32_t pdqcb_unsolicited_event; 295 pdq_uint32_t pdqcb__filler3; 296 pdq_uint32_t pdqcb_command_response; 297 pdq_uint32_t pdqcb__filler4; 298 pdq_uint32_t pdqcb_command_request; 299 pdq_uint32_t pdqcb__filler5[7]; 300 } pdq_consumer_block_t; 301 302 #if defined(BYTE_ORDER) && BYTE_ORDER == BIG_ENDIAN 303 #define PDQ_BITFIELD2(a, b) b, a 304 #define PDQ_BITFIELD3(a, b, c) c, b, a 305 #define PDQ_BITFIELD4(a, b, c, d) d, c, b, a 306 #define PDQ_BITFIELD5(a, b, c, d, e) e, d, c, b, a 307 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \ 308 l, k, j, i, h, g, f, e, d, c, b, a 309 #else 310 #define PDQ_BITFIELD2(a, b) a, b 311 #define PDQ_BITFIELD3(a, b, c) a, b, c 312 #define PDQ_BITFIELD4(a, b, c, d) a, b, c, d 313 #define PDQ_BITFIELD5(a, b, c, d, e) a, b, c, d, e 314 #define PDQ_BITFIELD12(a, b, c, d, e, f, g, h, i, j, k, l) \ 315 a, b, c, d, e, f, g, h, i, j, k, l 316 #endif 317 318 typedef struct { 319 pdq_uint32_t PDQ_BITFIELD5(rxd_pa_hi : 16, 320 rxd_seg_cnt : 4, 321 rxd_seg_len_hi : 9, 322 rxd_seg_len_lo : 2, 323 rxd_sop : 1); 324 pdq_uint32_t rxd_pa_lo; 325 } pdq_rxdesc_t; 326 327 typedef union { 328 pdq_uint32_t rxs_status; 329 pdq_uint32_t PDQ_BITFIELD12(rxs_len : 13, 330 rxs_rcc_ss : 2, 331 rxs_rcc_dd : 2, 332 rxs_rcc_reason : 3, 333 rxs_rcc_badcrc : 1, 334 rxs_rcc_badpdu : 1, 335 rxs_fsb__reserved : 2, 336 rxs_fsb_c : 1, 337 rxs_fsb_a : 1, 338 rxs_fsb_e : 1, 339 rxs_fsc : 3, 340 rxs__reserved : 2); 341 } pdq_rxstatus_t; 342 343 typedef struct { 344 pdq_uint32_t PDQ_BITFIELD5(txd_pa_hi : 16, 345 txd_seg_len : 13, 346 txd_mbz : 1, 347 txd_eop : 1, 348 txd_sop : 1); 349 pdq_uint32_t txd_pa_lo; 350 } pdq_txdesc_t; 351 352 typedef struct { 353 pdq_rxdesc_t pdqdb_receives[256]; /* 2048; 0x0000..0x07FF */ 354 pdq_txdesc_t pdqdb_transmits[256]; /* 2048; 0x0800..0x0FFF */ 355 pdq_rxdesc_t pdqdb_host_smt[64]; /* 512; 0x1000..0x11FF */ 356 pdq_rxdesc_t pdqdb_unsolicited_events[16]; /* 128; 0x1200..0x127F */ 357 pdq_rxdesc_t pdqdb_command_responses[16]; /* 128; 0x1280..0x12FF */ 358 pdq_txdesc_t pdqdb_command_requests[16]; /* 128; 0x1300..0x137F */ 359 /* 360 * The rest of the descriptor block is unused. 361 * As such we could use it for other things. 362 */ 363 pdq_consumer_block_t pdqdb_consumer; /* 64; 0x1380..0x13BF */ 364 void *pdqdb_receive_buffers[256]; /* 1024/2048; 0x13C0..0x17BF 0x13C0..0x1BBF */ 365 void *pdqdb_host_smt_buffers[64]; /* 256/ 512; 0x17C0..0x18BF 0x1BC0..0x1DBF */ 366 /* 367 * The maximum command size is 512 so as long as thes 368 * command is at least that long all will be fine. 369 */ 370 #if defined(__alpha) || defined(__alpha__) 371 pdq_uint32_t pdqdb_command_pool[144]; 372 #else 373 pdq_uint32_t pdqdb_command_pool[464]; 374 #endif 375 } pdq_descriptor_block_t; 376 377 typedef struct { 378 /* 379 * These value manage the available space in command/response 380 * buffer area. 381 */ 382 pdq_physaddr_t ci_pa_bufstart; 383 pdq_uint8_t *ci_bufstart; 384 /* 385 * Bitmask of commands to sent to the PDQ 386 */ 387 pdq_uint32_t ci_pending_commands; 388 /* 389 * Variables to maintain the PDQ queues. 390 */ 391 pdq_uint32_t ci_command_active; 392 pdq_uint32_t ci_request_producer; 393 pdq_uint32_t ci_response_producer; 394 pdq_uint32_t ci_request_completion; 395 pdq_uint32_t ci_response_completion; 396 } pdq_command_info_t; 397 398 #define PDQ_SIZE_UNSOLICITED_EVENT 512 399 #define PDQ_NUM_UNSOLICITED_EVENTS (PDQ_OS_PAGESIZE / PDQ_SIZE_UNSOLICITED_EVENT) 400 401 typedef struct _pdq_unsolicited_event_t pdq_unsolicited_event_t; 402 403 typedef struct { 404 pdq_physaddr_t ui_pa_bufstart; 405 pdq_unsolicited_event_t *ui_events; 406 407 pdq_uint32_t ui_free; 408 pdq_uint32_t ui_producer; 409 pdq_uint32_t ui_completion; 410 } pdq_unsolicited_info_t; 411 412 #define PDQ_RX_FC_OFFSET (sizeof(pdq_rxstatus_t) + 3) 413 #define PDQ_RX_SEGCNT ((PDQ_FDDI_MAX + PDQ_OS_DATABUF_SIZE - 1) / PDQ_OS_DATABUF_SIZE) 414 #define PDQ_DO_TYPE2_PRODUCER(pdq) \ 415 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_type_2_producer, \ 416 ((pdq)->pdq_rx_info.rx_producer << 0) \ 417 | ((pdq)->pdq_tx_info.tx_producer << 8) \ 418 | ((pdq)->pdq_rx_info.rx_completion << 16) \ 419 | ((pdq)->pdq_tx_info.tx_completion << 24)) 420 421 #define PDQ_DO_HOST_SMT_PRODUCER(pdq) \ 422 PDQ_CSR_WRITE(&(pdq)->pdq_csrs, csr_host_smt_producer, \ 423 ((pdq)->pdq_host_smt_info.rx_producer << 0) \ 424 | ((pdq)->pdq_host_smt_info.rx_completion << 8))\ 425 426 #define PDQ_ADVANCE(n, a, m) ((n) = ((n) + (a)) & (m)) 427 428 typedef struct { 429 void *q_head; 430 void *q_tail; 431 } pdq_databuf_queue_t; 432 433 typedef struct { 434 void *rx_buffers; 435 436 pdq_uint32_t rx_target; 437 pdq_uint32_t rx_free; 438 pdq_uint32_t rx_producer; 439 pdq_uint32_t rx_completion; 440 } pdq_rx_info_t; 441 442 typedef struct { 443 pdq_databuf_queue_t tx_txq; 444 pdq_txdesc_t tx_hdrdesc; 445 pdq_uint8_t tx_descriptor_count[256]; 446 447 pdq_uint32_t tx_free; 448 pdq_uint32_t tx_producer; 449 pdq_uint32_t tx_completion; 450 } pdq_tx_info_t; 451 452 struct _pdq_t { 453 pdq_csrs_t pdq_csrs; 454 pdq_pci_csrs_t pdq_pci_csrs; 455 pdq_type_t pdq_type; 456 pdq_chip_rev_t pdq_chip_rev; 457 pdq_lanaddr_t pdq_hwaddr; 458 pdq_fwrev_t pdq_fwrev; 459 pdq_descriptor_block_t *pdq_dbp; 460 volatile pdq_consumer_block_t *pdq_cbp; 461 pdq_uint32_t pdq_flags; 462 #define PDQ_PROMISC 0x0001 463 #define PDQ_ALLMULTI 0x0002 464 #define PDQ_PASS_SMT 0x0004 465 #define PDQ_RUNNING 0x0008 466 #define PDQ_PRINTCHARS 0x0010 467 #define PDQ_TXOK 0x0020 468 const char *pdq_os_name; 469 void *pdq_os_ctx; 470 pdq_uint32_t pdq_unit; 471 pdq_command_info_t pdq_command_info; 472 pdq_unsolicited_info_t pdq_unsolicited_info; 473 pdq_tx_info_t pdq_tx_info; 474 pdq_rx_info_t pdq_rx_info; 475 pdq_rx_info_t pdq_host_smt_info; 476 pdq_uint8_t pdq_tx_hdr[3]; 477 }; 478 479 typedef enum { 480 PDQC_START=0, 481 PDQC_FILTER_SET=1, 482 PDQC_FILTER_GET=2, 483 PDQC_CHARS_SET=3, 484 PDQC_STATUS_CHARS_GET=4, 485 PDQC_COUNTERS_GET=5, 486 PDQC_COUNTERS_SET=6, 487 PDQC_ADDR_FILTER_SET=7, 488 PDQC_ADDR_FILTER_GET=8, 489 PDQC_ERROR_LOG_CLEAR=9, 490 PDQC_ERROR_LOG_GET=10, 491 PDQC_FDDI_MIB_GET=11, 492 PDQC_DEC_EXT_MIB_GET=12, 493 PDQC_DEV_SPECIFIC_GET=13, 494 PDQC_SNMP_SET=14, 495 PDQC_SMT_MIB_GET=16, 496 PDQC_SMT_MIB_SET=17 497 } pdq_cmd_code_t; 498 499 typedef enum { 500 PDQR_SUCCESS=0, 501 PDQR_FAILURE=1, 502 PDQR_WARNING=2, 503 PDQR_LOOP_MODE_BAD=3, 504 PDQR_ITEM_CODE_BAD=4, 505 PDQR_TVX_BAD=5, 506 PDQR_TREQ_BAD=6, 507 PDQR_RESTRICTED_TOKEN_BAD=7, 508 PDQR_NO_EOL=12, 509 PDQR_FILTER_STATE_BAD=13, 510 PDQR_CMD_TYPE_BAD=14, 511 PDQR_ADAPTER_STATE_BAD=15, 512 PDQR_RING_PURGER_BAD=16, 513 PDQR_LEM_THRESHOLD_BAD=17, 514 PDQR_LOOP_NOT_SUPPORTED=18, 515 PDQR_FLUSH_TIME_BAD=19, 516 PDQR_NOT_YET_IMPLEMENTED=20, 517 PDQR_CONFIG_POLICY_BAD=21, 518 PDQR_STATION_ACTION_BAD=22, 519 PDQR_MAC_ACTION_BAD=23, 520 PDQR_CON_POLICIES_BAD=24, 521 PDQR_MAC_LOOP_TIME_BAD=25, 522 PDQR_TB_MAX_BAD=26, 523 PDQR_LER_CUTOFF_BAD=27, 524 PDQR_LER_ALARM_BAD=28, 525 PDQR_MAC_PATHS_REQ_BAD=29, 526 PDQR_MAC_T_REQ_BAD=30, 527 PDQR_EMAC_RING_PURGER_BAD=31, 528 PDQR_EMAC_RTOKEN_TIMOUT_AD=32, 529 PDQR_NO_SUCH_ENTRY=33, 530 PDQR_T_NOTIFY_BAD=34, 531 PDQR_TR_MAX_EXP_BAD=35, 532 PDQR_FRAME_ERR_THRESHOLD_BAD=36, 533 PDQR_MAX_TREQ_BAD=37, 534 PDQR_FULL_DUPLEX_ENABLE_BAD=38, 535 PDQR_ITEM_INDEX_BAD=39 536 } pdq_response_code_t; 537 538 typedef enum { 539 PDQI_EOL=0, 540 PDQI_T_REQ=1, 541 PDQI_TVX=2, 542 PDQI_RESTRICTED_TOKEN=3, 543 PDQI_LEM_THRESHOLD=4, 544 PDQI_RING_PURGER=5, 545 PDQI_COUNTER_INTERVAL=6, 546 PDQI_IND_GROUP_PROM=7, 547 PDQI_GROUP_PROM=8, 548 PDQI_BROADCAST=9, 549 PDQI_SMT_PROM=10, 550 PDQI_SMT_USER=11, 551 PDQI_RESERVED=12, 552 PDQI_IMPLEMENTOR=13, 553 PDQI_LOOPBACK_MODE=14, 554 PDQI_SMT_CONFIG_POLICY=16, 555 PDQI_SMT_CONNECTION_POLICY=17, 556 PDQI_SMT_T_NOTIFY=18, 557 PDQI_SMT_STATION_ACTION=19, 558 PDQI_MAC_PATHS_REQUESTED=21, 559 PDQI_MAC_ACTION=23, 560 PDQI_PORT_CONNECTION_POLICIES=24, 561 PDQI_PORT_PATHS_REQUESTED=25, 562 PDQI_PORT_MAC_LOOP_TIME=26, 563 PDQI_PORT_TB_MAX=27, 564 PDQI_PORT_LER_CUTOFF=28, 565 PDQI_PORT_LER_ALARM=29, 566 PDQI_PORT_ACTION=30, 567 PDQI_FLUSH_TIME=32, 568 PDQI_SMT_USER_DATA=33, 569 PDQI_SMT_STATUS_REPORT_POLICY=34, 570 PDQI_SMT_TRACE_MAX_EXPIRATION=35, 571 PDQI_MAC_FRAME_ERR_THRESHOLD=36, 572 PDQI_MAC_UNIT_DATA_ENABLE=37, 573 PDQI_PATH_TVX_LOWER_BOUND=38, 574 PDQI_PATH_TMAX_LOWER_BOUND=39, 575 PDQI_PATH_MAX_TREQ=40, 576 PDQI_MAC_TREQ=41, 577 PDQI_EMAC_RING_PURGER=42, 578 PDQI_EMAC_RTOKEN_TIMEOUT=43, 579 PDQI_FULL_DUPLEX_ENABLE=44 580 } pdq_item_code_t; 581 582 enum _pdq_boolean_t { 583 PDQ_FALSE=0, 584 PDQ_TRUE=1 585 }; 586 587 typedef enum { 588 PDQ_FILTER_BLOCK=0, 589 PDQ_FILTER_PASS=1 590 } pdq_filter_state_t; 591 592 typedef enum { 593 PDQ_STATION_TYPE_SAS=0, 594 PDQ_STATION_TYPE_DAC=1, 595 PDQ_STATION_TYPE_SAC=2, 596 PDQ_STATION_TYPE_NAC=3, 597 PDQ_STATION_TYPE_DAS=4 598 } pdq_station_type_t; 599 600 typedef enum { 601 PDQ_STATION_STATE_OFF=0, 602 PDQ_STATION_STATE_ON=1, 603 PDQ_STATION_STATE_LOOPBACK=2 604 } pdq_station_state_t; 605 606 typedef enum { 607 PDQ_LINK_STATE_OFF_READY=1, 608 PDQ_LINK_STATE_OFF_FAULT_RECOVERY=2, 609 PDQ_LINK_STATE_ON_RING_INIT=3, 610 PDQ_LINK_STATE_ON_RING_RUN=4, 611 PDQ_LINK_STATE_BROKEN=5 612 } pdq_link_state_t; 613 614 typedef enum { 615 PDQ_DA_TEST_STATE_UNKNOWN=0, 616 PDQ_DA_TEST_STATE_SUCCESS=1, 617 PDQ_DA_TEST_STATE_DUPLICATE=2 618 } pdq_da_test_state_t; 619 620 typedef enum { 621 PDQ_RING_PURGER_STATE_OFF=0, 622 PDQ_RING_PURGER_STATE_CANDIDATE=1, 623 PDQ_RING_PURGER_STATE_NON_PURGER=2, 624 PDQ_RING_PURGER_STATE_PURGER=3 625 } pdq_ring_purger_state_t; 626 627 typedef enum { 628 PDQ_FRAME_STRING_MODE_SA_MATCH=0, 629 PDQ_FRAME_STRING_MODE_FCI_STRIP=1 630 } pdq_frame_strip_mode_t; 631 632 typedef enum { 633 PDQ_RING_ERROR_REASON_NO_ERROR=0, 634 PDQ_RING_ERROR_REASON_RING_INIT_INITIATED=5, 635 PDQ_RING_ERROR_REASON_RING_INIT_RECEIVED=6, 636 PDQ_RING_ERROR_REASON_RING_BEACONING_INITIATED=7, 637 PDQ_RING_ERROR_REASON_DUPLICATE_ADDRESS_DETECTED=8, 638 PDQ_RING_ERROR_REASON_DUPLICATE_TOKEN_DETECTED=9, 639 PDQ_RING_ERROR_REASON_RING_PURGER_ERROR=10, 640 PDQ_RING_ERROR_REASON_FCI_STRIP_ERROR=11, 641 PDQ_RING_ERROR_REASON_RING_OP_OSCILLATION=12, 642 PDQ_RING_ERROR_REASON_DIRECTED_BEACON_RECEVIED=13, 643 PDQ_RING_ERROR_REASON_PC_TRACE_INITIATED=14, 644 PDQ_RING_ERROR_REASON_PC_TRACE_RECEVIED=15 645 } pdq_ring_error_reason_t; 646 647 typedef enum { 648 PDQ_STATION_MODE_NORMAL=0, 649 PDQ_STATION_MODE_INTERNAL_LOOPBACK=1 650 } pdq_station_mode_t; 651 652 typedef enum { 653 PDQ_PHY_TYPE_A=0, 654 PDQ_PHY_TYPE_B=1, 655 PDQ_PHY_TYPE_S=2, 656 PDQ_PHY_TYPE_M=3, 657 PDQ_PHY_TYPE_UNKNOWN=4 658 } pdq_phy_type_t; 659 660 typedef enum { 661 PDQ_PMD_TYPE_ANSI_MUTLI_MODE=0, 662 PDQ_PMD_TYPE_ANSI_SINGLE_MODE_TYPE_1=1, 663 PDQ_PMD_TYPE_ANSI_SIGNLE_MODE_TYPE_2=2, 664 PDQ_PMD_TYPE_ANSI_SONET=3, 665 PDQ_PMD_TYPE_LOW_POWER=100, 666 PDQ_PMD_TYPE_THINWIRE=101, 667 PDQ_PMD_TYPE_SHIELDED_TWISTED_PAIR=102, 668 PDQ_PMD_TYPE_UNSHIELDED_TWISTED_PAIR=103 669 } pdq_pmd_type_t; 670 671 typedef enum { 672 PDQ_PMD_CLASS_ANSI_MULTI_MODE=0, 673 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_1=1, 674 PDQ_PMD_CLASS_SINGLE_MODE_TYPE_2=2, 675 PDQ_PMD_CLASS_SONET=3, 676 PDQ_PMD_CLASS_LOW_COST_POWER_FIBER=4, 677 PDQ_PMD_CLASS_TWISTED_PAIR=5, 678 PDQ_PMD_CLASS_UNKNOWN=6, 679 PDQ_PMD_CLASS_UNSPECIFIED=7 680 } pdq_pmd_class_t; 681 682 typedef enum { 683 PDQ_PHY_STATE_INTERNAL_LOOPBACK=0, 684 PDQ_PHY_STATE_BROKEN=1, 685 PDQ_PHY_STATE_OFF_READY=2, 686 PDQ_PHY_STATE_WAITING=3, 687 PDQ_PHY_STATE_STARTING=4, 688 PDQ_PHY_STATE_FAILED=5, 689 PDQ_PHY_STATE_WATCH=6, 690 PDQ_PHY_STATE_INUSE=7 691 } pdq_phy_state_t; 692 693 typedef enum { 694 PDQ_REJECT_REASON_NONE=0, 695 PDQ_REJECT_REASON_LOCAL_LCT=1, 696 PDQ_REJECT_REASON_REMOTE_LCT=2, 697 PDQ_REJECT_REASON_LCT_BOTH_SIDES=3, 698 PDQ_REJECT_REASON_LEM_REJECT=4, 699 PDQ_REJECT_REASON_TOPOLOGY_ERROR=5, 700 PDQ_REJECT_REASON_NOISE_REJECT=6, 701 PDQ_REJECT_REASON_REMOTE_REJECT=7, 702 PDQ_REJECT_REASON_TRACE_IN_PROGRESS=8, 703 PDQ_REJECT_REASON_TRACE_RECEIVED_DISABLED=9, 704 PDQ_REJECT_REASON_STANDBY=10, 705 PDQ_REJECT_REASON_LCT_PROTOCOL_ERROR=11 706 } pdq_reject_reason_t; 707 708 typedef enum { 709 PDQ_BROKEN_REASON_NONE=0 710 } pdq_broken_reason_t; 711 712 typedef enum { 713 PDQ_RI_REASON_TVX_EXPIRED=0, 714 PDQ_RI_REASON_TRT_EXPIRED=1, 715 PDQ_RI_REASON_RING_PURGER_ELECTION_ATTEMPT_LIMIT_EXCEEDED=2, 716 PDQ_RI_REASON_PURGE_ERROR_LIMIT_EXCEEDED=3, 717 PDQ_RI_REASON_RESTRICTED_TOKEN_TIMEOUT=4 718 } pdq_ri_reason_t; 719 720 typedef enum { 721 PDQ_LCT_DIRECTION_LOCAL_LCT=0, 722 PDQ_LCT_DIRECTION_REMOTE_LCT=1, 723 PDQ_LCT_DIRECTION_LCT_BOTH_SIDES=2 724 } pdq_lct_direction_t; 725 726 typedef enum { 727 PDQ_PORT_A=0, 728 PDQ_PORT_B=1 729 } pdq_port_type_t; 730 731 typedef struct { 732 pdq_uint8_t station_id_bytes[8]; 733 } pdq_station_id_t; 734 735 typedef pdq_uint32_t pdq_fdditimer_t; 736 /* 737 * Command format for Start, Filter_Get, ... commands 738 */ 739 typedef struct { 740 pdq_cmd_code_t generic_op; 741 } pdq_cmd_generic_t; 742 743 /* 744 * Response format for Start, Filter_Set, ... commands 745 */ 746 typedef struct { 747 pdq_uint32_t generic_reserved; 748 pdq_cmd_code_t generic_op; 749 pdq_response_code_t generic_status; 750 } pdq_response_generic_t; 751 752 /* 753 * Command format for Filter_Set command 754 */ 755 typedef struct { 756 pdq_cmd_code_t filter_set_op; 757 struct { 758 pdq_item_code_t item_code; 759 pdq_filter_state_t filter_state; 760 } filter_set_items[7]; 761 pdq_item_code_t filter_set_eol_item_code; 762 } pdq_cmd_filter_set_t; 763 764 /* 765 * Response format for Filter_Get command. 766 */ 767 typedef struct { 768 pdq_uint32_t filter_get_reserved; 769 pdq_cmd_code_t filter_get_op; 770 pdq_response_code_t filter_get_status; 771 pdq_filter_state_t filter_get_ind_group_prom; 772 pdq_filter_state_t filter_get_group_prom; 773 pdq_filter_state_t filter_get_broadcast_all; 774 pdq_filter_state_t filter_get_smt_prom; 775 pdq_filter_state_t filter_get_smt_user; 776 pdq_filter_state_t filter_get_reserved_all; 777 pdq_filter_state_t filter_get_implementor_all; 778 } pdq_response_filter_get_t; 779 780 #define PDQ_SIZE_RESPONSE_FILTER_GET 0x28 781 782 typedef struct { 783 pdq_cmd_code_t chars_set_op; 784 struct { 785 pdq_item_code_t item_code; 786 pdq_uint32_t item_value; 787 pdq_port_type_t item_port; 788 } chars_set_items[1]; 789 pdq_item_code_t chars_set_eol_item_code; 790 } pdq_cmd_chars_set_t; 791 792 typedef struct { 793 pdq_cmd_code_t addr_filter_set_op; 794 pdq_lanaddr_t addr_filter_set_addresses[62]; 795 } pdq_cmd_addr_filter_set_t; 796 797 #define PDQ_SIZE_CMD_ADDR_FILTER_SET 0x1F4 798 799 typedef struct { 800 pdq_uint32_t addr_filter_get_reserved; 801 pdq_cmd_code_t addr_filter_get_op; 802 pdq_response_code_t addr_filter_get_status; 803 pdq_lanaddr_t addr_filter_get_addresses[62]; 804 } pdq_response_addr_filter_get_t; 805 806 #define PDQ_SIZE_RESPONSE_ADDR_FILTER_GET 0x1FC 807 808 typedef struct { 809 pdq_uint32_t status_chars_get_reserved; 810 pdq_cmd_code_t status_chars_get_op; 811 pdq_response_code_t status_chars_get_status; 812 struct { 813 /* Station Characteristic Attributes */ 814 pdq_station_id_t station_id; 815 pdq_station_type_t station_type; 816 pdq_uint32_t smt_version_id; 817 pdq_uint32_t smt_max_version_id; 818 pdq_uint32_t smt_min_version_id; 819 /* Station Status Attributes */ 820 pdq_station_state_t station_state; 821 /* Link Characteristic Attributes */ 822 pdq_lanaddr_t link_address; 823 pdq_fdditimer_t t_req; 824 pdq_fdditimer_t tvx; 825 pdq_fdditimer_t restricted_token_timeout; 826 pdq_boolean_t ring_purger_enable; 827 pdq_link_state_t link_state; 828 pdq_fdditimer_t negotiated_trt; 829 pdq_da_test_state_t dup_addr_flag; 830 /* Link Status Attributes */ 831 pdq_lanaddr_t upstream_neighbor; 832 pdq_lanaddr_t old_upstream_neighbor; 833 pdq_boolean_t upstream_neighbor_dup_addr_flag; 834 pdq_lanaddr_t downstream_neighbor; 835 pdq_lanaddr_t old_downstream_neighbor; 836 pdq_ring_purger_state_t ring_purger_state; 837 pdq_frame_strip_mode_t frame_strip_mode; 838 pdq_ring_error_reason_t ring_error_reason; 839 pdq_boolean_t loopback; 840 pdq_fdditimer_t ring_latency; 841 pdq_lanaddr_t last_dir_beacon_sa; 842 pdq_lanaddr_t last_dir_beacon_una; 843 /* Phy Characteristic Attributes */ 844 pdq_phy_type_t phy_type[2]; 845 pdq_pmd_type_t pmd_type[2]; 846 pdq_uint32_t lem_threshold[2]; 847 /* Phy Status Attributes */ 848 pdq_phy_state_t phy_state[2]; 849 pdq_phy_type_t neighbor_phy_type[2]; 850 pdq_uint32_t link_error_estimate[2]; 851 pdq_broken_reason_t broken_reason[2]; 852 pdq_reject_reason_t reject_reason[2]; 853 /* Miscellaneous */ 854 pdq_uint32_t counter_interval; 855 pdq_fwrev_t module_rev; 856 pdq_fwrev_t firmware_rev; 857 pdq_uint32_t mop_device_type; 858 pdq_uint32_t fddi_led[2]; 859 pdq_uint32_t flush; 860 } status_chars_get; 861 } pdq_response_status_chars_get_t; 862 863 #define PDQ_SIZE_RESPONSE_STATUS_CHARS_GET 0xF0 864 865 typedef struct { 866 pdq_uint32_t fddi_mib_get_reserved; 867 pdq_cmd_code_t fddi_mib_get_op; 868 pdq_response_code_t fddi_mib_get_status; 869 struct { 870 /* SMT Objects */ 871 pdq_station_id_t smt_station_id; 872 pdq_uint32_t smt_op_version_id; 873 pdq_uint32_t smt_hi_version_id; 874 pdq_uint32_t smt_lo_version_id; 875 pdq_uint32_t smt_mac_ct; 876 pdq_uint32_t smt_non_master_ct; 877 pdq_uint32_t smt_master_ct; 878 pdq_uint32_t smt_paths_available; 879 pdq_uint32_t smt_config_capabilities; 880 pdq_uint32_t smt_config_policy; 881 pdq_uint32_t smt_connection_policy; 882 pdq_uint32_t smt_t_notify; 883 pdq_uint32_t smt_status_reporting; 884 pdq_uint32_t smt_ecm_state; 885 pdq_uint32_t smt_cf_state; 886 pdq_uint32_t smt_hold_state; 887 pdq_uint32_t smt_remote_disconnect_flag; 888 pdq_uint32_t smt_station_action; 889 /* MAC Objects */ 890 pdq_uint32_t mac_frame_status_capabilities; 891 pdq_uint32_t mac_t_max_greatest_lower_bound; 892 pdq_uint32_t mac_tvx_greatest_lower_bound; 893 pdq_uint32_t mac_paths_available; 894 pdq_uint32_t mac_current_path; 895 pdq_lanaddr_t mac_upstream_neighbor; 896 pdq_lanaddr_t mac_old_upstream_neighbor; 897 pdq_uint32_t mac_dup_addr_test; 898 pdq_uint32_t mac_paths_requested; 899 pdq_uint32_t mac_downstream_port_type; 900 pdq_lanaddr_t mac_smt_address; 901 pdq_uint32_t mac_t_req; 902 pdq_uint32_t mac_t_neg; 903 pdq_uint32_t mac_t_max; 904 pdq_uint32_t mac_tvx_value; 905 pdq_uint32_t mac_t_min; 906 pdq_uint32_t mac_current_frame_status; 907 pdq_uint32_t mac_frame_error_threshold; 908 pdq_uint32_t mac_frame_error_ratio; 909 pdq_uint32_t mac_rmt_state; 910 pdq_uint32_t mac_da_flag; 911 pdq_uint32_t mac_una_da_flag; 912 pdq_uint32_t mac_frame_condition; 913 pdq_uint32_t mac_chip_set; 914 pdq_uint32_t mac_action; 915 /* Port Objects */ 916 pdq_uint32_t port_pc_type[2]; 917 pdq_uint32_t port_pc_neighbor[2]; 918 pdq_uint32_t port_connection_policies[2]; 919 pdq_uint32_t port_remote_mac_indicated[2]; 920 pdq_uint32_t port_ce_state[2]; 921 pdq_uint32_t port_paths_requested[2]; 922 pdq_uint32_t port_mac_placement[2]; 923 pdq_uint32_t port_available_paths[2]; 924 pdq_uint32_t port_mac_loop_time[2]; 925 pdq_uint32_t port_tb_max[2]; 926 pdq_uint32_t port_bs_flag[2]; 927 pdq_uint32_t port_ler_estimate[2]; 928 pdq_uint32_t port_ler_cutoff[2]; 929 pdq_uint32_t port_ler_alarm[2]; 930 pdq_uint32_t port_connect_state[2]; 931 pdq_uint32_t port_pcm_state[2]; 932 pdq_uint32_t port_pc_withhold[2]; 933 pdq_uint32_t port_ler_condition[2]; 934 pdq_uint32_t port_chip_set[2]; 935 pdq_uint32_t port_action[2]; 936 /* Attachment Objects */ 937 pdq_uint32_t attachment_class; 938 pdq_uint32_t attachment_optical_bypass_present; 939 pdq_uint32_t attachment_imax_expiration; 940 pdq_uint32_t attachment_inserted_status; 941 pdq_uint32_t attachment_insert_policy; 942 } fddi_mib_get; 943 } pdq_response_fddi_mib_get_t; 944 945 #define PDQ_SIZE_RESPONSE_FDDI_MIB_GET 0x17C 946 947 typedef enum { 948 PDQ_FDX_STATE_IDLE=0, 949 PDQ_FDX_STATE_REQUEST=1, 950 PDQ_FDX_STATE_CONFIRM=2, 951 PDQ_FDX_STATE_OPERATION=3 952 } pdq_fdx_state_t; 953 954 typedef struct { 955 pdq_uint32_t dec_ext_mib_get_reserved; 956 pdq_cmd_code_t dec_ext_mib_get_op; 957 pdq_response_code_t dec_ext_mib_get_response; 958 struct { 959 /* SMT Objects */ 960 pdq_uint32_t esmt_station_type; 961 /* MAC Objects */ 962 pdq_uint32_t emac_link_state; 963 pdq_uint32_t emac_ring_purger_state; 964 pdq_uint32_t emac_ring_purger_enable; 965 pdq_uint32_t emac_frame_strip_mode; 966 pdq_uint32_t emac_ring_error_reason; 967 pdq_uint32_t emac_upstream_nbr_dupl_address_flag; 968 pdq_uint32_t emac_restricted_token_timeout; 969 /* Port Objects */ 970 pdq_uint32_t eport_pmd_type[2]; 971 pdq_uint32_t eport_phy_state[2]; 972 pdq_uint32_t eport_reject_reason[2]; 973 /* Full Duplex Objects */ 974 pdq_boolean_t fdx_enable; 975 pdq_boolean_t fdx_operational; 976 pdq_fdx_state_t fdx_state; 977 } dec_ext_mib_get; 978 } pdq_response_dec_ext_mib_get_t; 979 980 #define PDQ_SIZE_RESPONSE_DEC_EXT_MIB_GET 0x50 981 982 typedef enum { 983 PDQ_CALLER_ID_NONE=0, 984 PDQ_CALLER_ID_SELFTEST=1, 985 PDQ_CALLER_ID_MFG=2, 986 PDQ_CALLER_ID_FIRMWARE=5, 987 PDQ_CALLER_ID_CONSOLE=8 988 } pdq_caller_id_t; 989 990 typedef struct { 991 pdq_uint32_t error_log_get__reserved; 992 pdq_cmd_code_t error_log_get_op; 993 pdq_response_code_t error_log_get_status; 994 /* Error Header */ 995 pdq_uint32_t error_log_get_event_status; 996 /* Event Information Block */ 997 pdq_caller_id_t error_log_get_caller_id; 998 pdq_uint32_t error_log_get_timestamp[2]; 999 pdq_uint32_t error_log_get_write_count; 1000 /* Diagnostic Information */ 1001 pdq_uint32_t error_log_get_fru_implication_mask; 1002 pdq_uint32_t error_log_get_test_id; 1003 pdq_uint32_t error_log_get_diag_reserved[6]; 1004 /* Firmware Information */ 1005 pdq_uint32_t error_log_get_fw_reserved[112]; 1006 } pdq_response_error_log_get_t; 1007 1008 1009 /* 1010 * Definitions for the Unsolicited Event Queue. 1011 */ 1012 typedef enum { 1013 PDQ_UNSOLICITED_EVENT=0, 1014 PDQ_UNSOLICITED_COUNTERS=1 1015 } pdq_event_t; 1016 1017 typedef enum { 1018 PDQ_ENTITY_STATION=0, 1019 PDQ_ENTITY_LINK=1, 1020 PDQ_ENTITY_PHY_PORT=2 1021 } pdq_entity_t; 1022 1023 typedef enum { 1024 PDQ_STATION_EVENT_TRACE_RECEIVED=1 1025 } pdq_station_event_t; 1026 1027 typedef enum { 1028 PDQ_STATION_EVENT_ARGUMENT_REASON=0, /* pdq_uint32_t */ 1029 PDQ_STATION_EVENT_ARGUMENT_EOL=0xFF 1030 } pdq_station_event_argument_t; 1031 1032 typedef enum { 1033 PDQ_LINK_EVENT_TRANSMIT_UNDERRUN=0, 1034 PDQ_LINK_EVENT_TRANSMIT_FAILED=1, 1035 PDQ_LINK_EVENT_BLOCK_CHECK_ERROR=2, 1036 PDQ_LINK_EVENT_FRAME_STATUS_ERROR=3, 1037 PDQ_LINK_EVENT_PDU_LENGTH_ERROR=4, 1038 PDQ_LINK_EVENT_RECEIVE_DATA_OVERRUN=7, 1039 PDQ_LINK_EVENT_NO_USER_BUFFER=9, 1040 PDQ_LINK_EVENT_RING_INITIALIZATION_INITIATED=10, 1041 PDQ_LINK_EVENT_RING_INITIALIZATION_RECEIVED=11, 1042 PDQ_LINK_EVENT_RING_BEACON_INITIATED=12, 1043 PDQ_LINK_EVENT_DUPLICATE_ADDRESS_FAILURE=13, 1044 PDQ_LINK_EVENT_DUPLICATE_TOKEN_DETECTED=14, 1045 PDQ_LINK_EVENT_RING_PURGE_ERROR=15, 1046 PDQ_LINK_EVENT_FCI_STRIP_ERROR=16, 1047 PDQ_LINK_EVENT_TRACE_INITIATED=17, 1048 PDQ_LINK_EVENT_DIRECTED_BEACON_RECEIVED=18 1049 } pdq_link_event_t; 1050 1051 typedef enum { 1052 PDQ_LINK_EVENT_ARGUMENT_REASON=0, /* pdq_rireason_t */ 1053 PDQ_LINK_EVENT_ARGUMENT_DATA_LINK_HEADER=1, /* pdq_dlhdr_t */ 1054 PDQ_LINK_EVENT_ARGUMENT_SOURCE=2, /* pdq_lanaddr_t */ 1055 PDQ_LINK_EVENT_ARGUMENT_UPSTREAM_NEIGHBOR=3,/* pdq_lanaddr_t */ 1056 PDQ_LINK_EVENT_ARGUMENT_EOL=0xFF 1057 } pdq_link_event_argument_t; 1058 1059 typedef enum { 1060 PDQ_PHY_EVENT_LEM_ERROR_MONITOR_REJECT=0, 1061 PDQ_PHY_EVENT_ELASTICITY_BUFFER_ERROR=1, 1062 PDQ_PHY_EVENT_LINK_CONFIDENCE_TEST_REJECT=2 1063 } pdq_phy_event_t; 1064 1065 typedef enum { 1066 PDQ_PHY_EVENT_ARGUMENT_DIRECTION=0, /* pdq_lct_direction_t */ 1067 PDQ_PHY_EVENT_ARGUMENT_EOL=0xFF 1068 } pdq_phy_event_arguments; 1069 1070 struct _pdq_unsolicited_event_t { 1071 pdq_uint32_t rvent_reserved; 1072 pdq_event_t event_type; 1073 pdq_entity_t event_entity; 1074 pdq_uint32_t event_index; 1075 union { 1076 pdq_station_event_t station_event; 1077 pdq_link_event_t link_event; 1078 pdq_phy_event_t phy_event; 1079 pdq_uint32_t value; 1080 } event_code; 1081 /* 1082 * The remainder of this event is an argument list. 1083 */ 1084 pdq_uint32_t event__filler[123]; 1085 }; 1086 1087 #endif /* _PDQREG_H */ 1088