1 /* $OpenBSD: mtd8xxvar.h,v 1.2 2003/10/21 18:58:49 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Oleg Safiullin <form@pdp11.org.ru> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 */ 30 31 #ifndef __DEV_IC_MTD8XXVAR_H__ 32 #define __DEV_IC_MTD8XXVAR_H__ 33 34 #define MTD_RX_LIST_CNT 64 35 #define MTD_TX_LIST_CNT 128 36 #define MTD_RXLEN 1536 37 38 39 /* 40 * Transmit descriptor structure. 41 */ 42 struct mtd_tx_desc { 43 u_int32_t td_tsw; /* Transmit status word */ 44 #define TSW_OWN 0x80000000U /* Descriptor owned by NIC */ 45 #define TSW_TXERR 0x00008000U /* Transmission error */ 46 #define TSW_ABORT 0x00002000U /* Transmission aborted */ 47 #define TSW_CSL 0x00001000U /* Carrier sense lost */ 48 #define TSW_LC 0x00000800U /* Late collision occurs */ 49 #define TSW_EC 0x00000400U /* Excessive collisions */ 50 #define TSW_DFR 0x00000200U /* Deferred */ 51 #define TSW_HF 0x00000100U /* Heart beat failure */ 52 #define TSW_NCR_MASK 0x000000FFU 53 #define TSW_NCR_SHIFT 0 54 #define TSW_NCR_GET(x) (((x) & TSW_NCR_MASK) >> TSW_NCR_SHIFT) 55 /* Collision retry count */ 56 #define TSW_UNSENT 0x00001234U /* Unsent packet magic */ 57 u_int32_t td_tcw; /* Transmit configure word */ 58 #define TCW_IC 0x80000000U /* Interrupt control */ 59 #define TCW_EIC 0x40000000U /* Early interrupt control */ 60 #define TCW_LD 0x20000000U /* Last descriptor */ 61 #define TCW_FD 0x10000000U /* First descriptor */ 62 #define TCW_CRC 0x08000000U /* Append CRC field to packet */ 63 #define TCW_PAD 0x04000000U /* Pad zeroes to the end of packet */ 64 #define TCW_RTLC 0x02000000U /* Retry late collision */ 65 #define TCW_PKTS_MASK 0x00003FF8U 66 #define TCW_PKTS_SHIFT 11 67 #define TCW_PKTS_GET(x) (((x) & TCW_PKTS_MASK) >> TCW_PKTS_SHIFT) 68 /* Packet size */ 69 #define TCW_TBS_MASK 0x000007FFU 70 #define TCW_TBS_SHIFT 0 71 #define TCW_TBS_GET(x) (((x) & TCW_TBS_MASK) >> TCW_TBS_SHIFT) 72 /* Transmit buffer size */ 73 u_int32_t td_buf; /* Transmit buffer address */ 74 u_int32_t td_next; /* Next descriptor address */ 75 }; 76 77 78 /* 79 * Receive descriptor structure. 80 */ 81 struct mtd_rx_desc { 82 u_int32_t rd_rsr; /* Receive status register */ 83 #define RSR_OWN 0x80000000U /* Descriptor owned by NIC */ 84 #define RSR_FLNG_MASK 0x0FFF0000U 85 #define RSR_FLNG_SHIFT 16 86 #define RSR_FLNG_GET(x) (((x) & RSR_FLNG_MASK) >> RSR_FLNG_SHIFT) 87 /* Frame length */ 88 #define RSR_MAR 0x00004000U /* Multicast address received */ 89 #define RSR_BAR 0x00002000U /* Broadcast address received */ 90 #define RSR_PHY 0x00001000U /* Physical address received */ 91 #define RSR_FSD 0x00000800U /* First descriptor */ 92 #define RSR_LSD 0x00000400U /* Last descriptor */ 93 #define RSR_ES 0x00000080U /* Error summary */ 94 #define RSR_RUNT 0x00000040U /* Runt packet received */ 95 #define RSR_LONG 0x00000020U /* Long packet received */ 96 #define RSR_FAE 0x00000010U /* Frame alignment error */ 97 #define RSR_CRC 0x00000008U /* CRC error */ 98 #define RSR_RXER 0x00000004U /* Receive error */ 99 u_int32_t rd_rcw; /* Receive configure word */ 100 #define RCW_RBS_MASK 0x000007FFU 101 #define RCW_RBS_SHIFT 0 102 #define RCW_RBS_GET(x) (((x) & RCW_RBS_MASK) >> RCW_RBS_SHIFT) 103 u_int32_t rd_buf; /* Receive buffer address */ 104 u_int32_t rd_next; /* Next descriptor address */ 105 }; 106 107 108 struct mtd_list_data { 109 struct mtd_rx_desc mtd_rx_list[MTD_RX_LIST_CNT]; 110 struct mtd_tx_desc mtd_tx_list[MTD_TX_LIST_CNT]; 111 }; 112 113 114 struct mtd_swdesc { 115 bus_dmamap_t sd_map; 116 struct mbuf *sd_mbuf; 117 }; 118 119 120 struct mtd_chain_data { 121 struct mtd_swdesc mtd_rx_chain[MTD_RX_LIST_CNT]; 122 struct mtd_swdesc mtd_tx_chain[MTD_TX_LIST_CNT]; 123 int mtd_tx_prod; 124 int mtd_tx_cons; 125 int mtd_tx_cnt; 126 int mtd_rx_prod; 127 }; 128 129 130 struct mtd_softc { 131 struct device sc_dev; 132 struct arpcom sc_arpcom; 133 struct mii_data sc_mii; 134 pci_product_id_t sc_devid; 135 136 bus_space_handle_t sc_bush; 137 bus_space_tag_t sc_bust; 138 139 struct mtd_list_data *mtd_ldata; 140 struct mtd_chain_data mtd_cdata; 141 142 bus_dma_tag_t sc_dmat; 143 bus_dmamap_t sc_listmap; 144 bus_dma_segment_t sc_listseg[1]; 145 int sc_listnseg; 146 caddr_t sc_listkva; 147 bus_dmamap_t sc_rx_sparemap; 148 bus_dmamap_t sc_tx_sparemap; 149 }; 150 151 __BEGIN_DECLS 152 void mtd_attach(struct mtd_softc *); 153 int mtd_intr(void *); 154 __END_DECLS 155 156 #endif /* __DEV_IC_MTD8XXVAR_H__ */ 157