1 /* ISDN4BSD code */ 2 /* 3 * Copyright (c) 1996, 1998 Gary Jennejohn. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 4. Altered versions must be plainly marked as such, and must not be 18 * misrepresented as being the original software and/or documentation. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 * 32 *--------------------------------------------------------------------------- 33 * 34 * $Id: isac.h,v 1.1 2003/04/06 04:37:26 tg Stab $ 35 * 36 * last edit-date: [Sun Feb 14 10:27:13 1999] 37 * 38 * -hm split up for rewrite of Siemens chipset driver 39 * 40 *--------------------------------------------------------------------------- 41 */ 42 43 #ifndef I4B_ISAC_H_ 44 #define I4B_ISAC_H_ 45 46 /* 47 * The ISAC databook specifies a delay of 2.5 DCL clock cycles between 48 * writes to the ISAC command register CMDR. This is the delay used to 49 * satisfy this requirement. 50 */ 51 52 #define I4B_ISAC_CMDRWRDELAY 30 53 54 #if (I4B_ISAC_CMDRWRDELAY > 0) 55 #define ISACCMDRWRDELAY() DELAY(I4B_ISAC_CMDRWRDELAY) 56 #else 57 #warning "I4B_ISAC_CMDRWRDELAY set to 0!" 58 #define ISACCMDRWRDELAY() 59 #endif 60 61 enum ISAC_VERSIONS { 62 ISAC_VA, /* 2085 A1 or A2, 2086/2186 V1.1 */ 63 ISAC_VB1, /* 2085 B1 */ 64 ISAC_VB2, /* 2085 B2 */ 65 ISAC_VB3, /* 2085 B3/V2.3 */ 66 ISAC_UNKN /* unknown version */ 67 }; 68 69 #define ISAC_FIFO_LEN 32 /* 32 bytes FIFO on chip */ 70 71 /* 72 * definitions of registers and bits for the ISAC ISDN chip. 73 */ 74 75 typedef struct isac_reg { 76 77 /* 32 byte deep FIFO always first */ 78 79 unsigned char isac_fifo [ISAC_FIFO_LEN]; 80 81 /* most registers can be read/written, but have different names */ 82 /* so define a union with read/write names to make that clear */ 83 84 union { 85 struct { 86 unsigned char isac_ista; 87 unsigned char isac_star; 88 unsigned char isac_mode; 89 unsigned char isac_timr; 90 unsigned char isac_exir; 91 unsigned char isac_rbcl; 92 unsigned char isac_sapr; 93 unsigned char isac_rsta; 94 unsigned char dummy_28; 95 unsigned char isac_rhcr; 96 unsigned char isac_rbch; 97 unsigned char isac_star2; 98 unsigned char dummy_2c; 99 unsigned char dummy_2d; 100 unsigned char dummy_2e; 101 unsigned char dummt_2f; 102 unsigned char isac_spcr; 103 unsigned char isac_cirr; 104 unsigned char isac_mor; 105 unsigned char isac_sscr; 106 unsigned char isac_sfcr; 107 unsigned char isac_c1r; 108 unsigned char isac_c2r; 109 unsigned char isac_b1cr; 110 unsigned char isac_b2cr; 111 unsigned char isac_adf2; 112 unsigned char isac_mosr; 113 unsigned char isac_sqrr; 114 } isac_r; 115 struct { 116 unsigned char isac_mask; 117 unsigned char isac_cmdr; 118 unsigned char isac_mode; 119 unsigned char isac_timr; 120 unsigned char isac_xad1; 121 unsigned char isac_xad2; 122 unsigned char isac_sap1; 123 unsigned char isac_sap2; 124 unsigned char isac_tei1; 125 unsigned char isac_tei2; 126 unsigned char dummy_2a; 127 unsigned char isac_star2; 128 unsigned char dummy_2c; 129 unsigned char dummy_2d; 130 unsigned char dummy_2e; 131 unsigned char dummt_2f; 132 unsigned char isac_spcr; 133 unsigned char isac_cixr; 134 unsigned char isac_mox; 135 unsigned char isac_sscx; 136 unsigned char isac_sfcw; 137 unsigned char isac_c1r; 138 unsigned char isac_c2r; 139 unsigned char isac_stcr; 140 unsigned char isac_adf1; 141 unsigned char isac_adf2; 142 unsigned char isac_mocr; 143 unsigned char isac_sqxr; 144 } isac_w; 145 } isac_rw; 146 } isac_reg_t; 147 148 #define REG_OFFSET(type, field) (int)(&(((type *)0)->field)) 149 150 /* ISAC read registers */ 151 152 #define i_ista isac_rw.isac_r.isac_ista 153 #define I_ISTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_ista) 154 #define i_star isac_rw.isac_r.isac_star 155 #define I_STAR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star) 156 #define i_mode isac_rw.isac_r.isac_mode 157 #define I_MODE REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mode) 158 #define i_timr isac_rw.isac_r.isac_timr 159 #define I_TIMR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_timr) 160 #define i_exir isac_rw.isac_r.isac_exir 161 #define I_EXIR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_exir) 162 #define i_rbcl isac_rw.isac_r.isac_rbcl 163 #define I_RBCL REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbcl) 164 #define i_sapr isac_rw.isac_r.isac_sapr 165 #define I_SAPR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sapr) 166 #define i_rsta isac_rw.isac_r.isac_rsta 167 #define I_RSTA REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rsta) 168 #define i_rhcr isac_rw.isac_r.isac_rhcr 169 #define I_RHCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rhcr) 170 #define i_rbch isac_rw.isac_r.isac_rbch 171 #define I_RBCH REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_rbch) 172 #define i_star2 isac_rw.isac_r.isac_star2 173 #define I_STAR2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_star2) 174 #define i_spcr isac_rw.isac_r.isac_spcr 175 #define I_SPCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_spcr) 176 #define i_cirr isac_rw.isac_r.isac_cirr 177 #define I_CIRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_cirr) 178 #define i_mor isac_rw.isac_r.isac_mor 179 #define I_MOR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mor) 180 #define i_sscr isac_rw.isac_r.isac_sscr 181 #define I_SSCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sscr) 182 #define i_sfcr isac_rw.isac_r.isac_sfcr 183 #define I_SFCR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sfcr) 184 #define i_c1r isac_rw.isac_r.isac_c1r 185 #define I_C1R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c1r) 186 #define i_c2r isac_rw.isac_r.isac_c2r 187 #define I_C2R REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_c2r) 188 #define i_b1cr isac_rw.isac_r.isac_b1cr 189 #define I_B1CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b1cr) 190 #define i_b2cr isac_rw.isac_r.isac_b2cr 191 #define I_B2CR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_b2cr) 192 #define i_adf2 isac_rw.isac_r.isac_adf2 193 #define I_ADF2 REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_adf2) 194 #define i_mosr isac_rw.isac_r.isac_mosr 195 #define I_MOSR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_mosr) 196 #define i_sqrr isac_rw.isac_r.isac_sqrr 197 #define I_SQRR REG_OFFSET(isac_reg_t, isac_rw.isac_r.isac_sqrr) 198 199 /* ISAC write registers - isac_mode, isac_timr, isac_star2, isac_spcr, */ 200 /* isac_c1r, isac_c2r, isac_adf2 see read registers */ 201 202 #define i_mask isac_rw.isac_w.isac_mask 203 #define I_MASK REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mask) 204 #define i_cmdr isac_rw.isac_w.isac_cmdr 205 #define I_CMDR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cmdr) 206 #define i_xad1 isac_rw.isac_w.isac_xad1 207 #define I_XAD1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad1) 208 #define i_xad2 isac_rw.isac_w.isac_xad2 209 #define I_XAD2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_xad2) 210 #define i_sap1 isac_rw.isac_w.isac_sap1 211 #define I_SAP1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap1) 212 #define i_sap2 isac_rw.isac_w.isac_sap2 213 #define I_SAP2 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sap2) 214 #define i_tei1 isac_rw.isac_w.isac_tei1 215 #define i_tei2 isac_rw.isac_w.isac_tei2 216 #define i_cixr isac_rw.isac_w.isac_cixr 217 #define I_CIXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_cixr) 218 #define I_CIX0 I_CIXR 219 #define i_mox isac_rw.isac_w.isac_mox 220 #define I_MOX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mox) 221 #define i_sscx isac_rw.isac_w.isac_sscx 222 #define I_SSCX REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sscx) 223 #define i_sfcw isac_rw.isac_w.isac_sfcw 224 #define I_SFCW REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sfcw) 225 #define i_stcr isac_rw.isac_w.isac_stcr 226 #define I_STCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_stcr) 227 #define i_adf1 isac_rw.isac_w.isac_adf1 228 #define I_ADF1 REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_adf1) 229 #define i_mocr isac_rw.isac_w.isac_mocr 230 #define I_MOCR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_mocr) 231 #define i_sqxr isac_rw.isac_w.isac_sqxr 232 #define I_SQXR REG_OFFSET(isac_reg_t, isac_rw.isac_w.isac_sqxr) 233 234 #define ISAC_ISTA_RME 0x80 235 #define ISAC_ISTA_RPF 0x40 236 #define ISAC_ISTA_RSC 0x20 237 #define ISAC_ISTA_XPR 0x10 238 #define ISAC_ISTA_TIN 0x08 239 #define ISAC_ISTA_CISQ 0x04 240 #define ISAC_ISTA_SIN 0x02 241 #define ISAC_ISTA_EXI 0x01 242 243 #define ISAC_MASK_RME 0x80 244 #define ISAC_MASL_RPF 0x40 245 #define ISAC_MASK_RSC 0x20 246 #define ISAC_MASK_XPR 0x10 247 #define ISAC_MASK_TIN 0x08 248 #define ISAC_MASK_CISQ 0x04 249 #define ISAC_MASK_SIN 0x02 250 #define ISAC_MASK_EXI 0x01 251 #define ISAC_MASK_ALL 0xff 252 253 #define ISAC_STAR_XDOV 0x80 254 #define ISAC_STAR_XFW 0x40 255 #define ISAC_STAR_XRNR 0x20 256 #define ISAC_STAR_RRNR 0x10 257 #define ISAC_STAR_MBR 0x08 258 #define ISAC_STAR_MAC1 0x04 259 #define ISAC_STAR_BVS 0x02 260 #define ISAC_STAR_MAC0 0x01 261 262 #define ISAC_CMDR_RMC 0x80 263 #define ISAC_CMDR_RRES 0x40 264 #define ISAC_CMDR_RNR 0x20 265 #define ISAC_CMDR_STI 0x10 266 #define ISAC_CMDR_XTF 0x08 267 #define ISAC_CMDR_XIF 0x04 268 #define ISAC_CMDR_XME 0x02 269 #define ISAC_CMDR_XRES 0x01 270 271 #define ISAC_MODE_MDS2 0x80 272 #define ISAC_MODE_MDS1 0x40 273 #define ISAC_MODE_MDS0 0x20 274 #define ISAC_MODE_TMD 0x10 275 #define ISAC_MODE_RAC 0x08 276 #define ISAC_MODE_DIM2 0x04 277 #define ISAC_MODE_DIM1 0x02 278 #define ISAC_MODE_DIM0 0x01 279 280 #define ISAC_EXIR_XMR 0x80 281 #define ISAC_EXIR_XDU 0x40 282 #define ISAC_EXIR_PCE 0x20 283 #define ISAC_EXIR_RFO 0x10 284 #define ISAC_EXIR_SOV 0x08 285 #define ISAC_EXIR_MOS 0x04 286 #define ISAC_EXIR_SAW 0x02 287 #define ISAC_EXIR_WOV 0x01 288 289 #define ISAC_RSTA_RDA 0x80 290 #define ISAC_RSTA_RDO 0x40 291 #define ISAC_RSTA_CRC 0x20 292 #define ISAC_RSTA_RAB 0x10 293 #define ISAC_RSTA_SA1 0x08 294 #define ISAC_RSTA_SA0 0x04 295 #define ISAC_RSTA_CR 0x02 296 #define ISAC_RSTA_TA 0x01 297 298 #define ISAC_RSTA_MASK 0x70 /* the interesting bits */ 299 300 #define ISAC_RBCH_XAC 0x80 301 #define ISAC_RBCH_VN1 0x40 302 #define ISAC_RBCH_VN0 0x20 303 #define ISAC_RBCH_OV 0x10 304 /* the other 4 bits are the high bits of the receive byte count */ 305 306 #define ISAC_SPCR_SPU 0x80 307 #define ISAC_SPCR_SAC 0x40 308 #define ISAC_SPCR_SPM 0x20 309 #define ISAC_SPCR_TLP 0x10 310 #define ISAC_SPCR_C1C1 0x08 311 #define ISAC_SPCR_C1C0 0x04 312 #define ISAC_SPCR_C2C1 0x02 313 #define ISAC_SPCR_C2C0 0x01 314 315 #define ISAC_CIRR_SQC 0x80 316 #define ISAC_CIRR_BAS 0x40 317 /* bits 5-2 CODR */ 318 #define ISAC_CIRR_CIC0 0x02 319 /* bit 0 is always 0 */ 320 /* C/I codes from bits 5-2 (>> 2 & 0xf) */ 321 /* the indications */ 322 #define ISAC_CIRR_IPU 0x07 323 #define ISAC_CIRR_IDR 0x00 324 #define ISAC_CIRR_ISD 0x02 325 #define ISAC_CIRR_IDIS 0x03 326 #define ISAC_CIRR_IEI 0x06 327 #define ISAC_CIRR_IRSY 0x04 328 #define ISAC_CIRR_IARD 0x08 329 #define ISAC_CIRR_ITI 0x0a 330 #define ISAC_CIRR_IATI 0x0b 331 #define ISAC_CIRR_IAI8 0x0c 332 #define ISAC_CIRR_IAI10 0x0d 333 #define ISAC_CIRR_IDID 0x0f 334 335 #define ISAC_CI_MASK 0x0f 336 337 #define ISAC_CIXR_RSS 0x80 338 #define ISAC_CIXR_BAC 0x40 339 /* bits 5-2 CODX */ 340 #define ISAC_CIXR_TCX 0x02 341 #define ISAC_CIXR_ECX 0x01 342 /* in IOM-2 mode the low bits are always 1 */ 343 #define ISAC_CIX0_LOW 0x03 344 /* C/I codes from bits 5-2 (>> 2 & 0xf) */ 345 /* the commands */ 346 #define ISAC_CIXR_CTIM 0 347 #define ISAC_CIXR_CRS 0x01 348 #define ISAC_CIXR_CSCZ 0x04 349 #define ISAC_CIXR_CSSZ 0x02 350 #define ISAC_CIXR_CAR8 0x08 351 #define ISAC_CIXR_CAR10 0x09 352 #define ISAC_CIXR_CARL 0x0a 353 #define ISAC_CIXR_CDIU 0x0f 354 355 #define ISAC_STCR_TSF 0x80 356 #define ISAC_STCR_TBA2 0x40 357 #define ISAC_STCR_TBA1 0x20 358 #define ISAC_STCR_TBA0 0x10 359 #define ISAC_STCR_ST1 0x08 360 #define ISAC_STCR_ST0 0x04 361 #define ISAC_STCR_SC1 0x02 362 #define ISAC_STCR_SC0 0x01 363 364 #define ISAC_ADF1_WTC1 0x80 365 #define ISAC_ADF1_WTC2 0x40 366 #define ISAC_ADF1_TEM 0x20 367 #define ISAC_ADF1_PFS 0x10 368 #define ISAC_ADF1_CFS 0x08 369 #define ISAC_ADF1_FC2 0x04 370 #define ISAC_ADF1_FC1 0x02 371 #define ISAC_ADF1_ITF 0x01 372 373 #define ISAC_ADF2_IMS 0x80 374 /* all other bits are 0 */ 375 376 /* bits 7-5 are always 0 */ 377 #define ISAC_SQRR_SYN 0x10 378 #define ISAC_SQRR_SQR1 0x08 379 #define ISAC_SQRR_SQR2 0x04 380 #define ISAC_SQRR_SQR3 0x02 381 #define ISAC_SQRR_SQR4 0x01 382 383 #define ISAC_SQXR_IDC 0x80 384 #define ISAC_SQXR_CFS 0x40 385 #define ISAC_SQXR_CI1E 0x20 386 #define ISAC_SQXR_SQIE 0x10 387 #define ISAC_SQXR_SQX1 0x08 388 #define ISAC_SQXR_SQX2 0x04 389 #define ISAC_SQXR_SQX3 0x02 390 #define ISAC_SQXR_SQX4 0x01 391 392 #endif /* I4B_ISAC_H_ */ 393