1 /* ISDN4BSD code */
2 /*
3 * Copyright (c) 1997, 2000 Hellmuth Michaelis. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 *---------------------------------------------------------------------------
27 *
28 * i4b_isac.c - i4b siemens isdn chipset driver ISAC handler
29 *
30 *---------------------------------------------------------------------------*/
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$MirOS: src/sys/dev/ic/isac.c,v 1.1.7.1 2005/03/06 16:33:43 tg Exp $");
34
35 #ifdef __FreeBSD__
36 #include "opt_i4b.h"
37 #endif
38 #include <sys/param.h>
39 #if defined(__FreeBSD__) && __FreeBSD__ >= 3
40 #include <sys/ioccom.h>
41 #else
42 #include <sys/ioctl.h>
43 #endif
44 #include <sys/kernel.h>
45 #include <sys/systm.h>
46 #include <sys/mbuf.h>
47 #include <sys/stdarg.h>
48
49 #ifdef __FreeBSD__
50 #include <machine/clock.h>
51 #include <i386/isa/isa_device.h>
52 #else
53 #ifndef __bsdi__
54 #include <machine/bus.h>
55 #endif
56 #include <sys/device.h>
57 #endif
58
59 #include <sys/socket.h>
60 #include <net/if.h>
61
62 #include <sys/timeout.h>
63
64 #ifdef __FreeBSD__
65 #include <machine/i4b_debug.h>
66 #include <machine/i4b_ioctl.h>
67 #include <machine/i4b_trace.h>
68 #else
69 #include <netisdn/i4b_debug.h>
70 #include <netisdn/i4b_ioctl.h>
71 #include <netisdn/i4b_trace.h>
72 #endif
73
74 #include <netisdn/i4b_global.h>
75 #include <netisdn/i4b_l2.h>
76 #include <netisdn/i4b_l1l2.h>
77 #include <netisdn/i4b_mbuf.h>
78
79 #include <dev/ic/isic_l1.h>
80 #include <dev/ic/isac.h>
81 #include <dev/ic/ipac.h>
82 #include <dev/ic/hscx.h>
83
84 static u_char isic_isac_exir_hdlr(register struct isic_softc *sc, u_char exir);
85 static void isic_isac_ind_hdlr(register struct isic_softc *sc, int ind);
86
87 /*---------------------------------------------------------------------------*
88 * ISAC interrupt service routine
89 *---------------------------------------------------------------------------*/
90 void
isic_isac_irq(struct isic_softc * sc,int ista)91 isic_isac_irq(struct isic_softc *sc, int ista)
92 {
93 register u_char c = 0;
94 NDBGL1(L1_F_MSG, "%s: ista = 0x%02x", sc->sc_dev.dv_xname, ista);
95
96 if(ista & ISAC_ISTA_EXI) /* extended interrupt */
97 {
98 u_int8_t exirstat = ISAC_READ(I_EXIR);
99 if (sc->sc_intr_valid == ISIC_INTR_VALID)
100 c |= isic_isac_exir_hdlr(sc, exirstat);
101 }
102
103 if(ista & ISAC_ISTA_RME) /* receive message end */
104 {
105 register int rest;
106 u_char rsta;
107
108 /* get rx status register */
109
110 rsta = ISAC_READ(I_RSTA);
111
112 if((rsta & ISAC_RSTA_MASK) != 0x20)
113 {
114 int error = 0;
115
116 if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
117 {
118 error++;
119 NDBGL1(L1_I_ERR, "%s: CRC error", sc->sc_dev.dv_xname);
120 }
121
122 if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
123 {
124 error++;
125 NDBGL1(L1_I_ERR, "%s: Data Overrun error", sc->sc_dev.dv_xname);
126 }
127
128 if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
129 {
130 error++;
131 NDBGL1(L1_I_ERR, "%s: Receive Aborted error", sc->sc_dev.dv_xname);
132 }
133
134 if(error == 0)
135 {
136 NDBGL1(L1_I_ERR, "%s: RME unknown error, RSTA = 0x%02x!", sc->sc_dev.dv_xname, rsta);
137 }
138
139 i4b_Dfreembuf(sc->sc_ibuf);
140
141 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
142
143 sc->sc_ibuf = NULL;
144 sc->sc_ib = NULL;
145 sc->sc_ilen = 0;
146
147 ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
148 ISACCMDRWRDELAY();
149
150 return;
151 }
152
153 rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
154
155 if(rest == 0)
156 rest = ISAC_FIFO_LEN;
157
158 if(sc->sc_ibuf == NULL)
159 {
160 if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
161 sc->sc_ib = sc->sc_ibuf->m_data;
162 else
163 panic("isic_isac_irq: RME, i4b_Dgetmbuf returns NULL!");
164 sc->sc_ilen = 0;
165 }
166
167 if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
168 {
169 ISAC_RDFIFO(sc->sc_ib, rest);
170 sc->sc_ilen += rest;
171
172 sc->sc_ibuf->m_pkthdr.len =
173 sc->sc_ibuf->m_len = sc->sc_ilen;
174
175 if(sc->sc_trace & TRACE_D_RX)
176 {
177 i4b_trace_hdr hdr;
178 memset(&hdr, 0, sizeof hdr);
179 hdr.type = TRC_CH_D;
180 hdr.dir = FROM_NT;
181 hdr.count = ++sc->sc_trace_dcount;
182 isdn_layer2_trace_ind(&sc->sc_l2, sc->sc_l3token, &hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
183 }
184
185 c |= ISAC_CMDR_RMC;
186
187 if(sc->sc_intr_valid == ISIC_INTR_VALID &&
188 (((struct isdn_l3_driver*)sc->sc_l3token)->protocol != PROTOCOL_D64S))
189 {
190 isdn_layer2_data_ind(&sc->sc_l2, sc->sc_l3token, sc->sc_ibuf);
191 }
192 else
193 {
194 i4b_Dfreembuf(sc->sc_ibuf);
195 }
196 }
197 else
198 {
199 NDBGL1(L1_I_ERR, "RME, input buffer overflow!");
200 i4b_Dfreembuf(sc->sc_ibuf);
201 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
202 }
203
204 sc->sc_ibuf = NULL;
205 sc->sc_ib = NULL;
206 sc->sc_ilen = 0;
207 }
208
209 if(ista & ISAC_ISTA_RPF) /* receive fifo full */
210 {
211 if(sc->sc_ibuf == NULL)
212 {
213 if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
214 sc->sc_ib= sc->sc_ibuf->m_data;
215 else
216 panic("isic_isac_irq: RPF, i4b_Dgetmbuf returns NULL!");
217 sc->sc_ilen = 0;
218 }
219
220 if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
221 {
222 ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
223 sc->sc_ilen += ISAC_FIFO_LEN;
224 sc->sc_ib += ISAC_FIFO_LEN;
225 c |= ISAC_CMDR_RMC;
226 }
227 else
228 {
229 NDBGL1(L1_I_ERR, "RPF, input buffer overflow!");
230 i4b_Dfreembuf(sc->sc_ibuf);
231 sc->sc_ibuf = NULL;
232 sc->sc_ib = NULL;
233 sc->sc_ilen = 0;
234 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
235 }
236 }
237
238 if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
239 {
240 if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
241 {
242 sc->sc_freeflag = sc->sc_freeflag2;
243 sc->sc_obuf = sc->sc_obuf2;
244 sc->sc_op = sc->sc_obuf->m_data;
245 sc->sc_ol = sc->sc_obuf->m_len;
246 sc->sc_obuf2 = NULL;
247 #ifdef NOTDEF
248 printf("ob2=%x, op=%x, ol=%d, f=%d #",
249 sc->sc_obuf,
250 sc->sc_op,
251 sc->sc_ol,
252 sc->sc_state);
253 #endif
254 }
255 else
256 {
257 #ifdef NOTDEF
258 printf("ob=%x, op=%x, ol=%d, f=%d #",
259 sc->sc_obuf,
260 sc->sc_op,
261 sc->sc_ol,
262 sc->sc_state);
263 #endif
264 }
265
266 if(sc->sc_obuf)
267 {
268 ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
269
270 if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
271 {
272 sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
273 sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
274 c |= ISAC_CMDR_XTF; /* set XTF bit */
275 }
276 else
277 {
278 if(sc->sc_freeflag)
279 {
280 i4b_Dfreembuf(sc->sc_obuf);
281 sc->sc_freeflag = 0;
282 }
283 sc->sc_obuf = NULL;
284 sc->sc_op = NULL;
285 sc->sc_ol = 0;
286
287 c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
288 }
289 }
290 else
291 {
292 sc->sc_state &= ~ISAC_TX_ACTIVE;
293 }
294 }
295
296 if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
297 {
298 register u_char ci;
299
300 /* get command/indication rx register*/
301
302 ci = ISAC_READ(I_CIRR);
303
304 /* if S/Q IRQ, read SQC reg to clr SQC IRQ */
305
306 if(ci & ISAC_CIRR_SQC)
307 (void) ISAC_READ(I_SQRR);
308
309 /* C/I code change IRQ (flag already cleared by CIRR read) */
310
311 if(ci & ISAC_CIRR_CIC0)
312 isic_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
313 }
314
315 if(c)
316 {
317 ISAC_WRITE(I_CMDR, c);
318 ISACCMDRWRDELAY();
319 }
320 }
321
322 /*---------------------------------------------------------------------------*
323 * ISAC L1 Extended IRQ handler
324 *---------------------------------------------------------------------------*/
325 static u_char
isic_isac_exir_hdlr(register struct isic_softc * sc,u_char exir)326 isic_isac_exir_hdlr(register struct isic_softc *sc, u_char exir)
327 {
328 u_char c = 0;
329
330 if(exir & ISAC_EXIR_XMR)
331 {
332 NDBGL1(L1_I_ERR, "EXIRQ Tx Message Repeat");
333
334 c |= ISAC_CMDR_XRES;
335 }
336
337 if(exir & ISAC_EXIR_XDU)
338 {
339 NDBGL1(L1_I_ERR, "EXIRQ Tx Data Underrun");
340
341 c |= ISAC_CMDR_XRES;
342 }
343
344 if(exir & ISAC_EXIR_PCE)
345 {
346 NDBGL1(L1_I_ERR, "EXIRQ Protocol Error");
347 }
348
349 if(exir & ISAC_EXIR_RFO)
350 {
351 NDBGL1(L1_I_ERR, "EXIRQ Rx Frame Overflow");
352
353 c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
354 }
355
356 if(exir & ISAC_EXIR_SOV)
357 {
358 NDBGL1(L1_I_ERR, "EXIRQ Sync Xfer Overflow");
359 }
360
361 if(exir & ISAC_EXIR_MOS)
362 {
363 NDBGL1(L1_I_ERR, "EXIRQ Monitor Status");
364 }
365
366 if(exir & ISAC_EXIR_SAW)
367 {
368 /* cannot happen, STCR:TSF is set to 0 */
369
370 NDBGL1(L1_I_ERR, "EXIRQ Subscriber Awake");
371 }
372
373 if(exir & ISAC_EXIR_WOV)
374 {
375 /* cannot happen, STCR:TSF is set to 0 */
376
377 NDBGL1(L1_I_ERR, "EXIRQ Watchdog Timer Overflow");
378 }
379
380 return(c);
381 }
382
383 /*---------------------------------------------------------------------------*
384 * ISAC L1 Indication handler
385 *---------------------------------------------------------------------------*/
386 static void
isic_isac_ind_hdlr(register struct isic_softc * sc,int ind)387 isic_isac_ind_hdlr(register struct isic_softc *sc, int ind)
388 {
389 register int event;
390
391 switch(ind)
392 {
393 case ISAC_CIRR_IAI8:
394 NDBGL1(L1_I_CICO, "rx AI8 in state %s", isic_printstate(sc));
395 if(sc->sc_bustyp == BUS_TYPE_IOM2)
396 isic_isac_l1_cmd(sc, CMD_AR8);
397 event = EV_INFO48;
398 isdn_layer2_status_ind(&sc->sc_l2, sc->sc_l3token, STI_L1STAT, LAYER_ACTIVE);
399 break;
400
401 case ISAC_CIRR_IAI10:
402 NDBGL1(L1_I_CICO, "rx AI10 in state %s", isic_printstate(sc));
403 if(sc->sc_bustyp == BUS_TYPE_IOM2)
404 isic_isac_l1_cmd(sc, CMD_AR10);
405 event = EV_INFO410;
406 isdn_layer2_status_ind(&sc->sc_l2, sc->sc_l3token, STI_L1STAT, LAYER_ACTIVE);
407 break;
408
409 case ISAC_CIRR_IRSY:
410 NDBGL1(L1_I_CICO, "rx RSY in state %s", isic_printstate(sc));
411 event = EV_RSY;
412 break;
413
414 case ISAC_CIRR_IPU:
415 NDBGL1(L1_I_CICO, "rx PU in state %s", isic_printstate(sc));
416 event = EV_PU;
417 break;
418
419 case ISAC_CIRR_IDR:
420 NDBGL1(L1_I_CICO, "rx DR in state %s", isic_printstate(sc));
421 isic_isac_l1_cmd(sc, CMD_DIU);
422 event = EV_DR;
423 break;
424
425 case ISAC_CIRR_IDID:
426 NDBGL1(L1_I_CICO, "rx DID in state %s", isic_printstate(sc));
427 event = EV_INFO0;
428 isdn_layer2_status_ind(&sc->sc_l2, sc->sc_l3token, STI_L1STAT, LAYER_IDLE);
429 break;
430
431 case ISAC_CIRR_IDIS:
432 NDBGL1(L1_I_CICO, "rx DIS in state %s", isic_printstate(sc));
433 event = EV_DIS;
434 break;
435
436 case ISAC_CIRR_IEI:
437 NDBGL1(L1_I_CICO, "rx EI in state %s", isic_printstate(sc));
438 isic_isac_l1_cmd(sc, CMD_DIU);
439 event = EV_EI;
440 break;
441
442 case ISAC_CIRR_IARD:
443 NDBGL1(L1_I_CICO, "rx ARD in state %s", isic_printstate(sc));
444 event = EV_INFO2;
445 break;
446
447 case ISAC_CIRR_ITI:
448 NDBGL1(L1_I_CICO, "rx TI in state %s", isic_printstate(sc));
449 event = EV_INFO0;
450 break;
451
452 case ISAC_CIRR_IATI:
453 NDBGL1(L1_I_CICO, "rx ATI in state %s", isic_printstate(sc));
454 event = EV_INFO0;
455 break;
456
457 case ISAC_CIRR_ISD:
458 NDBGL1(L1_I_CICO, "rx SD in state %s", isic_printstate(sc));
459 event = EV_INFO0;
460 break;
461
462 default:
463 NDBGL1(L1_I_ERR, "UNKNOWN Indication 0x%x in state %s", ind, isic_printstate(sc));
464 event = EV_INFO0;
465 break;
466 }
467 isic_next_state(sc, event);
468 }
469
470 /*---------------------------------------------------------------------------*
471 * execute a layer 1 command
472 *---------------------------------------------------------------------------*/
473 void
isic_isac_l1_cmd(struct isic_softc * sc,int command)474 isic_isac_l1_cmd(struct isic_softc *sc, int command)
475 {
476 u_char cmd;
477
478 #ifdef I4B_SMP_WORKAROUND
479
480 /* XXXXXXXXXXXXXXXXXXX */
481
482 /*
483 * patch from Wolfgang Helbig:
484 *
485 * Here is a patch that makes i4b work on an SMP:
486 * The card (TELES 16.3) didn't interrupt on an SMP machine.
487 * This is a gross workaround, but anyway it works *and* provides
488 * some information as how to finally fix this problem.
489 */
490
491 HSCX_WRITE(0, H_MASK, 0xff);
492 HSCX_WRITE(1, H_MASK, 0xff);
493 ISAC_WRITE(I_MASK, 0xff);
494 DELAY(100);
495 HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
496 HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
497 ISAC_WRITE(I_MASK, ISAC_IMASK);
498
499 /* XXXXXXXXXXXXXXXXXXX */
500
501 #endif /* I4B_SMP_WORKAROUND */
502
503 if(command < 0 || command > CMD_ILL)
504 {
505 NDBGL1(L1_I_ERR, "illegal cmd 0x%x in state %s", command, isic_printstate(sc));
506 return;
507 }
508
509 if(sc->sc_bustyp == BUS_TYPE_IOM2)
510 cmd = ISAC_CIX0_LOW;
511 else
512 cmd = 0;
513
514 switch(command)
515 {
516 case CMD_TIM:
517 NDBGL1(L1_I_CICO, "tx TIM in state %s", isic_printstate(sc));
518 cmd |= (ISAC_CIXR_CTIM << 2);
519 break;
520
521 case CMD_RS:
522 NDBGL1(L1_I_CICO, "tx RS in state %s", isic_printstate(sc));
523 cmd |= (ISAC_CIXR_CRS << 2);
524 break;
525
526 case CMD_AR8:
527 NDBGL1(L1_I_CICO, "tx AR8 in state %s", isic_printstate(sc));
528 cmd |= (ISAC_CIXR_CAR8 << 2);
529 break;
530
531 case CMD_AR10:
532 NDBGL1(L1_I_CICO, "tx AR10 in state %s", isic_printstate(sc));
533 cmd |= (ISAC_CIXR_CAR10 << 2);
534 break;
535
536 case CMD_DIU:
537 NDBGL1(L1_I_CICO, "tx DIU in state %s", isic_printstate(sc));
538 cmd |= (ISAC_CIXR_CDIU << 2);
539 break;
540 }
541 ISAC_WRITE(I_CIXR, cmd);
542 }
543
544 /*---------------------------------------------------------------------------*
545 * L1 ISAC initialization
546 *---------------------------------------------------------------------------*/
547 int
isic_isac_init(struct isic_softc * sc)548 isic_isac_init(struct isic_softc *sc)
549 {
550 ISAC_IMASK = 0xff; /* disable all irqs */
551
552 ISAC_WRITE(I_MASK, ISAC_IMASK);
553
554 if(sc->sc_bustyp != BUS_TYPE_IOM2)
555 {
556 NDBGL1(L1_I_SETUP, "configuring for IOM-1 mode");
557
558 /* ADF2: Select mode IOM-1 */
559 ISAC_WRITE(I_ADF2, 0x00);
560
561 /* SPCR: serial port control register:
562 * SPU - software power up = 0
563 * SAC - SIP port high Z
564 * SPM - timing mode 0
565 * TLP - test loop = 0
566 * C1C, C2C - B1 and B2 switched to/from SPa
567 */
568 ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
569
570 /* SQXR: S/Q channel xmit register:
571 * SQIE - S/Q IRQ enable = 0
572 * SQX1-4 - Fa bits = 1
573 */
574 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
575
576 /* ADF1: additional feature reg 1:
577 * WTC - watchdog = 0
578 * TEM - test mode = 0
579 * PFS - pre-filter = 0
580 * CFS - IOM clock/frame always active
581 * FSC1/2 - polarity of 8kHz strobe
582 * ITF - interframe fill = idle
583 */
584 ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2); /* ADF1 */
585
586 /* STCR: sync transfer control reg:
587 * TSF - terminal secific functions = 0
588 * TBA - TIC bus address = 7
589 * STx/SCx = 0
590 */
591 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
592 }
593 else
594 {
595 NDBGL1(L1_I_SETUP, "configuring for IOM-2 mode");
596
597 /* ADF2: Select mode IOM-2 */
598 ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
599
600 /* SPCR: serial port control register:
601 * SPU - software power up = 0
602 * SPM - timing mode 0
603 * TLP - test loop = 0
604 * C1C, C2C - B1 + C1 and B2 + IC2 monitoring
605 */
606 ISAC_WRITE(I_SPCR, 0x00);
607
608 /* SQXR: S/Q channel xmit register:
609 * IDC - IOM direction = 0 (master)
610 * CFS - Config Select = 0 (clock always active)
611 * CI1E - C/I channel 1 IRQ enable = 0
612 * SQIE - S/Q IRQ enable = 0
613 * SQX1-4 - Fa bits = 1
614 */
615 ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
616
617 /* ADF1: additional feature reg 1:
618 * WTC - watchdog = 0
619 * TEM - test mode = 0
620 * PFS - pre-filter = 0
621 * IOF - IOM i/f off = 0
622 * ITF - interframe fill = idle
623 */
624 ISAC_WRITE(I_ADF1, 0x00);
625
626 /* STCR: sync transfer control reg:
627 * TSF - terminal secific functions = 0
628 * TBA - TIC bus address = 7
629 * STx/SCx = 0
630 */
631 ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
632 }
633
634
635 /* MODE: Mode Register:
636 * MDSx - transparent mode 2
637 * TMD - timer mode = external
638 * RAC - Receiver enabled
639 * DIMx - digital i/f mode
640 */
641 ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
642
643 /* enabled interrupts:
644 * ===================
645 * RME - receive message end
646 * RPF - receive pool full
647 * XPR - transmit pool ready
648 * CISQ - CI or S/Q channel change
649 * EXI - extended interrupt
650 */
651
652 ISAC_IMASK = ISAC_MASK_RSC | /* auto mode only */
653 ISAC_MASK_TIN | /* timer irq */
654 ISAC_MASK_SIN; /* sync xfer irq */
655
656 ISAC_WRITE(I_MASK, ISAC_IMASK);
657
658 ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
659 ISACCMDRWRDELAY();
660
661 return(0);
662 }
663
664 /*---------------------------------------------------------------------------*
665 * isic_recovery - try to recover from irq lockup
666 *---------------------------------------------------------------------------*/
667 void
isic_recover(struct isic_softc * sc)668 isic_recover(struct isic_softc *sc)
669 {
670 u_char byte;
671
672 /* get hscx irq status from hscx b ista */
673
674 byte = HSCX_READ(HSCX_CH_B, H_ISTA);
675
676 NDBGL1(L1_ERROR, "HSCX B: ISTA = 0x%x", byte);
677
678 if(byte & HSCX_ISTA_ICA)
679 NDBGL1(L1_ERROR, "HSCX A: ISTA = 0x%x", (u_char)HSCX_READ(HSCX_CH_A, H_ISTA));
680
681 if(byte & HSCX_ISTA_EXB)
682 NDBGL1(L1_ERROR, "HSCX B: EXIR = 0x%x", (u_char)HSCX_READ(HSCX_CH_B, H_EXIR));
683
684 if(byte & HSCX_ISTA_EXA)
685 NDBGL1(L1_ERROR, "HSCX A: EXIR = 0x%x", (u_char)HSCX_READ(HSCX_CH_A, H_EXIR));
686
687 /* get isac irq status */
688
689 byte = ISAC_READ(I_ISTA);
690
691 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
692
693 if(byte & ISAC_ISTA_EXI)
694 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
695
696 if(byte & ISAC_ISTA_CISQ)
697 {
698 byte = ISAC_READ(I_CIRR);
699
700 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
701
702 if(byte & ISAC_CIRR_SQC)
703 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
704 }
705
706 NDBGL1(L1_ERROR, "HSCX B: IMASK = 0x%x", HSCX_B_IMASK);
707 NDBGL1(L1_ERROR, "HSCX A: IMASK = 0x%x", HSCX_A_IMASK);
708
709 HSCX_WRITE(0, H_MASK, 0xff);
710 HSCX_WRITE(1, H_MASK, 0xff);
711 DELAY(100);
712 HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
713 HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
714 DELAY(100);
715
716 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISAC_IMASK);
717
718 ISAC_WRITE(I_MASK, 0xff);
719 DELAY(100);
720 ISAC_WRITE(I_MASK, ISAC_IMASK);
721 }
722