1 /* ISDN4BSD code */
2 /* $NetBSD: iavcreg.h,v 1.1 2003/09/25 15:53:26 pooka Exp $ */
3
4 /*
5 * Copyright (c) 2001-2003 Cubical Solutions Ltd. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * capi/iavc/iavc.h The AVM ISDN controllers' common declarations.
29 *
30 * $FreeBSD: src/sys/i4b/capi/iavc/iavc.h,v 1.1.2.1 2001/08/10 14:08:34 obrien Exp $
31 */
32
33 /*
34 // AMCC_{READ,WRITE}
35 // Routines to access the memory mapped registers of the
36 // S5933 DMA controller.
37 */
38
AMCC_READ(iavc_softc_t * sc,int off)39 static __inline u_int32_t AMCC_READ(iavc_softc_t *sc, int off)
40 {
41 return bus_space_read_4(sc->sc_mem_bt, sc->sc_mem_bh, off);
42 }
43
AMCC_WRITE(iavc_softc_t * sc,int off,u_int32_t value)44 static __inline void AMCC_WRITE(iavc_softc_t *sc, int off, u_int32_t value)
45 {
46 bus_space_write_4(sc->sc_mem_bt, sc->sc_mem_bh, off, value);
47 }
48
49 /*
50 // amcc_{put,get}_{byte,word}
51 // Routines to access the DMA buffers byte- or wordwise.
52 */
53
amcc_put_byte(u_int8_t * buf,u_int8_t value)54 static __inline u_int8_t* amcc_put_byte(u_int8_t *buf, u_int8_t value)
55 {
56 *buf++ = value;
57 return buf;
58 }
59
amcc_get_byte(u_int8_t * buf,u_int8_t * value)60 static __inline u_int8_t* amcc_get_byte(u_int8_t *buf, u_int8_t *value)
61 {
62 *value = *buf++;
63 return buf;
64 }
65
amcc_put_word(u_int8_t * buf,u_int32_t value)66 static __inline u_int8_t* amcc_put_word(u_int8_t *buf, u_int32_t value)
67 {
68 *buf++ = (value & 0xff);
69 *buf++ = (value >> 8) & 0xff;
70 *buf++ = (value >> 16) & 0xff;
71 *buf++ = (value >> 24) & 0xff;
72 return buf;
73 }
74
amcc_get_word(u_int8_t * buf,u_int32_t * value)75 static __inline u_int8_t* amcc_get_word(u_int8_t *buf, u_int32_t *value)
76 {
77 *value = *buf++;
78 *value |= (*buf++ << 8);
79 *value |= (*buf++ << 16);
80 *value |= (*buf++ << 24);
81 return buf;
82 }
83
84 /*
85 // Controller LLI message numbers.
86 */
87
88 #define SEND_POLL 0x72
89 #define SEND_INIT 0x11
90 #define SEND_REGISTER 0x12
91 #define SEND_DATA_B3_REQ 0x13
92 #define SEND_RELEASE 0x14
93 #define SEND_MESSAGE 0x15
94 #define SEND_CONFIG 0x71
95 #define SEND_POLLACK 0x73
96
97 #define RECEIVE_POLL 0x32
98 #define RECEIVE_INIT 0x27
99 #define RECEIVE_MESSAGE 0x21
100 #define RECEIVE_DATA_B3_IND 0x22
101 #define RECEIVE_START 0x23
102 #define RECEIVE_STOP 0x24
103 #define RECEIVE_NEW_NCCI 0x25
104 #define RECEIVE_FREE_NCCI 0x26
105 #define RECEIVE_RELEASE 0x26
106 #define RECEIVE_TASK_READY 0x31
107 #define RECEIVE_DEBUGMSG 0x71
108 #define RECEIVE_POLLDWORD 0x75
109
110 /* Operation constants */
111
112 #define WRITE_REGISTER 0x00
113 #define READ_REGISTER 0x01
114
115 /* Port offsets in I/O space */
116
117 #define B1_READ 0x00
118 #define B1_WRITE 0x01
119 #define B1_INSTAT 0x02
120 #define B1_OUTSTAT 0x03
121 #define B1_ANALYSE 0x04
122 #define B1_REVISION 0x05
123 #define B1_RESET 0x10
124
125 #define T1_FASTLINK 0x00
126 #define T1_SLOWLINK 0x08
127
128 #define T1_READ B1_READ
129 #define T1_WRITE B1_WRITE
130 #define T1_INSTAT B1_INSTAT
131 #define T1_OUTSTAT B1_OUTSTAT
132 #define T1_IRQENABLE 0x05
133 #define T1_FIFOSTAT 0x06
134 #define T1_RESETLINK 0x10
135 #define T1_ANALYSE 0x11
136 #define T1_IRQMASTER 0x12
137 #define T1_IDENT 0x17
138 #define T1_RESETBOARD 0x1f
139
140 #define T1F_IREADY 0x01
141 #define T1F_IHALF 0x02
142 #define T1F_IFULL 0x04
143 #define T1F_IEMPTY 0x08
144 #define T1F_IFLAGS 0xf0
145
146 #define T1F_OREADY 0x10
147 #define T1F_OHALF 0x20
148 #define T1F_OEMPTY 0x40
149 #define T1F_OFULL 0x80
150 #define T1F_OFLAGS 0xf0
151
152 #define FIFO_OUTBSIZE 256
153 #define FIFO_INPBSIZE 512
154
155 #define HEMA_VERSION_ID 0
156 #define HEMA_PAL_ID 0
157
158 /*
159 // S5933 DMA controller register offsets in memory, and bitmasks.
160 */
161
162 #define AMCC_RXPTR 0x24
163 #define AMCC_RXLEN 0x28
164 #define AMCC_TXPTR 0x2c
165 #define AMCC_TXLEN 0x30
166
167 #define AMCC_INTCSR 0x38
168 #define EN_READ_TC_INT 0x00008000
169 #define EN_WRITE_TC_INT 0x00004000
170 #define EN_TX_TC_INT EN_READ_TC_INT
171 #define EN_RX_TC_INT EN_WRITE_TC_INT
172 #define AVM_FLAG 0x30000000
173
174 #define ANY_S5933_INT 0x00800000
175 #define READ_TC_INT 0x00080000
176 #define WRITE_TC_INT 0x00040000
177 #define TX_TC_INT READ_TC_INT
178 #define RX_TC_INT WRITE_TC_INT
179 #define MASTER_ABORT_INT 0x00100000
180 #define TARGET_ABORT_INT 0x00200000
181 #define BUS_MASTER_INT 0x00200000
182 #define ALL_INT 0x000c0000
183
184 #define AMCC_MCSR 0x3c
185 #define A2P_HI_PRIORITY 0x00000100
186 #define EN_A2P_TRANSFERS 0x00000400
187 #define P2A_HI_PRIORITY 0x00001000
188 #define EN_P2A_TRANSFERS 0x00004000
189 #define RESET_A2P_FLAGS 0x04000000
190 #define RESET_P2A_FLAGS 0x02000000
191
192 /*
193 // (B1IO_WAIT_MAX * B1IO_WAIT_DLY) is the max wait in us for the card
194 // to become ready after an I/O operation. The default is 1 ms.
195 */
196
197 #define B1IO_WAIT_MAX 1000
198 #define B1IO_WAIT_DLY 1
199
200 /*
201 // b1io_outp
202 // Diagnostic output routine, returns the written value via
203 // the device's analysis register.
204 //
205 // b1io_rx_full
206 // Returns nonzero if data is readable from the card via the
207 // I/O ports.
208 //
209 // b1io_tx_empty
210 // Returns nonzero if data can be written to the card via the
211 // I/O ports.
212 */
213
b1io_outp(iavc_softc_t * sc,int off,u_int8_t val)214 static __inline u_int8_t b1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
215 {
216 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
217 DELAY(1);
218 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_ANALYSE);
219 }
220
b1io_rx_full(iavc_softc_t * sc)221 static __inline int b1io_rx_full(iavc_softc_t *sc)
222 {
223 u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_INSTAT);
224 return (val & 0x01);
225 }
226
b1io_tx_empty(iavc_softc_t * sc)227 static __inline int b1io_tx_empty(iavc_softc_t *sc)
228 {
229 u_int8_t val = bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_OUTSTAT);
230 return (val & 0x01);
231 }
232
233 /*
234 // b1io_{get,put}_{byte,word}
235 // Routines to read and write the device I/O registers byte- or
236 // wordwise.
237 //
238 // b1io_{get,put}_slice
239 // Routines to read and write sequential bytes to the device
240 // I/O registers.
241 */
242
b1io_get_byte(iavc_softc_t * sc)243 static __inline u_int8_t b1io_get_byte(iavc_softc_t *sc)
244 {
245 int spin = 0;
246 while (!b1io_rx_full(sc) && spin < B1IO_WAIT_MAX) {
247 spin++; DELAY(B1IO_WAIT_DLY);
248 }
249 if (b1io_rx_full(sc))
250 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, B1_READ);
251 printf("iavc%d: rx not completed\n", sc->sc_unit);
252 return 0xff;
253 }
254
b1io_put_byte(iavc_softc_t * sc,u_int8_t val)255 static __inline int b1io_put_byte(iavc_softc_t *sc, u_int8_t val)
256 {
257 int spin = 0;
258 while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
259 spin++; DELAY(B1IO_WAIT_DLY);
260 }
261 if (b1io_tx_empty(sc)) {
262 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, B1_WRITE, val);
263 return 0;
264 }
265 printf("iavc%d: tx not emptied\n", sc->sc_unit);
266 return -1;
267 }
268
b1io_save_put_byte(iavc_softc_t * sc,u_int8_t val)269 static __inline int b1io_save_put_byte(iavc_softc_t *sc, u_int8_t val)
270 {
271 int spin = 0;
272 while (!b1io_tx_empty(sc) && spin < B1IO_WAIT_MAX) {
273 spin++; DELAY(B1IO_WAIT_DLY);
274 }
275 if (b1io_tx_empty(sc)) {
276 b1io_outp(sc, B1_WRITE, val);
277 return 0;
278 }
279 printf("iavc%d: tx not emptied\n", sc->sc_unit);
280 return -1;
281 }
282
b1io_get_word(iavc_softc_t * sc)283 static __inline u_int32_t b1io_get_word(iavc_softc_t *sc)
284 {
285 u_int32_t val = 0;
286 val |= b1io_get_byte(sc);
287 val |= (b1io_get_byte(sc) << 8);
288 val |= (b1io_get_byte(sc) << 16);
289 val |= (b1io_get_byte(sc) << 24);
290 return val;
291 }
292
b1io_put_word(iavc_softc_t * sc,u_int32_t val)293 static __inline void b1io_put_word(iavc_softc_t *sc, u_int32_t val)
294 {
295 b1io_put_byte(sc, (val & 0xff));
296 b1io_put_byte(sc, (val >> 8) & 0xff);
297 b1io_put_byte(sc, (val >> 16) & 0xff);
298 b1io_put_byte(sc, (val >> 24) & 0xff);
299 }
300
b1io_get_slice(iavc_softc_t * sc,u_int8_t * dp)301 static __inline int b1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
302 {
303 int len, i;
304 len = i = b1io_get_word(sc);
305 while (i--) *dp++ = b1io_get_byte(sc);
306 return len;
307 }
308
b1io_put_slice(iavc_softc_t * sc,u_int8_t * dp,int len)309 static __inline void b1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
310 {
311 b1io_put_word(sc, len);
312 while (len--) b1io_put_byte(sc, *dp++);
313 }
314
315 /*
316 // b1io_{read,write}_reg
317 // Routines to read and write the device registers via the I/O
318 // ports.
319 */
320
b1io_read_reg(iavc_softc_t * sc,int reg)321 static __inline u_int32_t b1io_read_reg(iavc_softc_t *sc, int reg)
322 {
323 b1io_put_byte(sc, READ_REGISTER);
324 b1io_put_word(sc, reg);
325 return b1io_get_word(sc);
326 }
327
b1io_write_reg(iavc_softc_t * sc,int reg,u_int32_t val)328 static __inline u_int32_t b1io_write_reg(iavc_softc_t *sc, int reg, u_int32_t val)
329 {
330 b1io_put_byte(sc, WRITE_REGISTER);
331 b1io_put_word(sc, reg);
332 b1io_put_word(sc, val);
333 return b1io_get_word(sc);
334 }
335
336 /*
337 // t1io_outp
338 // I/O port write operation for the T1, which does not seem
339 // to have the analysis port.
340 */
341
t1io_outp(iavc_softc_t * sc,int off,u_int8_t val)342 static __inline void t1io_outp(iavc_softc_t *sc, int off, u_int8_t val)
343 {
344 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, off, val);
345 }
346
t1io_inp(iavc_softc_t * sc,int off)347 static __inline u_int8_t t1io_inp(iavc_softc_t *sc, int off)
348 {
349 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, off);
350 }
351
t1io_isfastlink(iavc_softc_t * sc)352 static __inline int t1io_isfastlink(iavc_softc_t *sc)
353 {
354 return ((bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_IDENT) & ~0x82) == 1);
355 }
356
t1io_fifostatus(iavc_softc_t * sc)357 static __inline u_int8_t t1io_fifostatus(iavc_softc_t *sc)
358 {
359 return bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, T1_FIFOSTAT);
360 }
361
t1io_get_slice(iavc_softc_t * sc,u_int8_t * dp)362 static __inline int t1io_get_slice(iavc_softc_t *sc, u_int8_t *dp)
363 {
364 int len, i;
365 len = i = b1io_get_word(sc);
366 if (t1io_isfastlink(sc)) {
367 int status;
368 while (i) {
369 status = t1io_fifostatus(sc) & (T1F_IREADY|T1F_IHALF);
370 if (i >= FIFO_INPBSIZE) status |= T1F_IFULL;
371
372 switch (status) {
373 case T1F_IREADY|T1F_IHALF|T1F_IFULL:
374 bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
375 T1_READ, dp, FIFO_INPBSIZE);
376 dp += FIFO_INPBSIZE;
377 i -= FIFO_INPBSIZE;
378 break;
379
380 case T1F_IREADY|T1F_IHALF:
381 bus_space_read_multi_1(sc->sc_io_bt, sc->sc_io_bh,
382 T1_READ, dp, i);
383 dp += i;
384 i = 0;
385 break;
386
387 default:
388 *dp++ = b1io_get_byte(sc);
389 i--;
390 }
391 }
392 } else { /* not fastlink */
393 if (i--) *dp++ = b1io_get_byte(sc);
394 }
395 return len;
396 }
397
t1io_put_slice(iavc_softc_t * sc,u_int8_t * dp,int len)398 static __inline void t1io_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
399 {
400 int i = len;
401 b1io_put_word(sc, i);
402 if (t1io_isfastlink(sc)) {
403 int status;
404 while (i) {
405 status = t1io_fifostatus(sc) & (T1F_OREADY|T1F_OHALF);
406 if (i >= FIFO_OUTBSIZE) status |= T1F_OFULL;
407
408 switch (status) {
409 case T1F_OREADY|T1F_OHALF|T1F_OFULL:
410 bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
411 T1_WRITE, dp, FIFO_OUTBSIZE);
412 dp += FIFO_OUTBSIZE;
413 i -= FIFO_OUTBSIZE;
414 break;
415
416 case T1F_OREADY|T1F_OHALF:
417 bus_space_write_multi_1(sc->sc_io_bt, sc->sc_io_bh,
418 T1_WRITE, dp, i);
419 dp += i;
420 i = 0;
421 break;
422
423 default:
424 b1io_put_byte(sc, *dp++);
425 i--;
426 }
427 }
428 } else {
429 while (i--) b1io_put_byte(sc, *dp++);
430 }
431 }
432
433 /*
434 // An attempt to bring it all together:
435 // ------------------------------------
436 //
437 // iavc_{read,write}_reg
438 // Routines to access the device registers via the I/O port.
439 //
440 // iavc_{read,write}_port
441 // Routines to access the device I/O ports.
442 //
443 // iavc_tx_empty, iavc_rx_full
444 // Routines to check when the device has drained the last written
445 // byte, or produced a full byte to read.
446 //
447 // iavc_{get,put}_byte
448 // Routines to read/write byte values to the device via the I/O port.
449 //
450 // iavc_{get,put}_word
451 // Routines to read/write 32-bit words to the device via the I/O port.
452 //
453 // iavc_{get,put}_slice
454 // Routines to read/write {length, data} pairs to the device via the
455 // ubiquituous I/O port. Uses the HEMA FIFO on a T1.
456 */
457
458 #define iavc_read_reg(sc, reg) b1io_read_reg(sc, reg)
459 #define iavc_write_reg(sc, reg, val) b1io_write_reg(sc, reg, val)
460
461 #define iavc_read_port(sc, port) \
462 bus_space_read_1(sc->sc_io_bt, sc->sc_io_bh, (port))
463 #define iavc_write_port(sc, port, val) \
464 bus_space_write_1(sc->sc_io_bt, sc->sc_io_bh, (port), (val))
465
466 #define iavc_tx_empty(sc) b1io_tx_empty(sc)
467 #define iavc_rx_full(sc) b1io_rx_full(sc)
468
469 #define iavc_get_byte(sc) b1io_get_byte(sc)
470 #define iavc_put_byte(sc, val) b1io_put_byte(sc, val)
471 #define iavc_get_word(sc) b1io_get_word(sc)
472 #define iavc_put_word(sc, val) b1io_put_word(sc, val)
473
iavc_get_slice(iavc_softc_t * sc,u_int8_t * dp)474 static __inline u_int32_t iavc_get_slice(iavc_softc_t *sc, u_int8_t *dp)
475 {
476 if (sc->sc_t1) return t1io_get_slice(sc, dp);
477 else return b1io_get_slice(sc, dp);
478 }
479
iavc_put_slice(iavc_softc_t * sc,u_int8_t * dp,int len)480 static __inline void iavc_put_slice(iavc_softc_t *sc, u_int8_t *dp, int len)
481 {
482 if (sc->sc_t1) t1io_put_slice(sc, dp, len);
483 else b1io_put_slice(sc, dp, len);
484 }
485