1 /* $OpenBSD: hme.c,v 1.30 2004/05/12 06:35:10 tedu Exp $ */
2 /* $NetBSD: hme.c,v 1.21 2001/07/07 15:59:37 thorpej Exp $ */
3
4 /*-
5 * Copyright (c) 1999 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * HME Ethernet module driver.
42 */
43
44 #include "bpfilter.h"
45 #include "vlan.h"
46
47 #undef HMEDEBUG
48
49 #include <sys/param.h>
50 #include <sys/systm.h>
51 #include <sys/kernel.h>
52 #include <sys/mbuf.h>
53 #include <sys/syslog.h>
54 #include <sys/socket.h>
55 #include <sys/device.h>
56 #include <sys/malloc.h>
57 #include <sys/ioctl.h>
58 #include <sys/errno.h>
59
60 #include <net/if.h>
61 #include <net/if_dl.h>
62 #include <net/if_media.h>
63
64 #ifdef INET
65 #include <netinet/in.h>
66 #include <netinet/in_systm.h>
67 #include <netinet/in_var.h>
68 #include <netinet/ip.h>
69 #include <netinet/if_ether.h>
70 #endif
71
72 #if NBPFILTER > 0
73 #include <net/bpf.h>
74 #endif
75
76 #include <dev/mii/mii.h>
77 #include <dev/mii/miivar.h>
78
79 #include <machine/bus.h>
80
81 #if NVLAN > 0
82 #include <net/if_vlan_var.h>
83 #endif
84
85 #include <dev/ic/hmereg.h>
86 #include <dev/ic/hmevar.h>
87
88 struct cfdriver hme_cd = {
89 NULL, "hme", DV_IFNET
90 };
91
92 #define HME_RX_OFFSET 2
93
94 void hme_start(struct ifnet *);
95 void hme_stop(struct hme_softc *);
96 int hme_ioctl(struct ifnet *, u_long, caddr_t);
97 void hme_tick(void *);
98 void hme_watchdog(struct ifnet *);
99 void hme_shutdown(void *);
100 void hme_init(struct hme_softc *);
101 void hme_meminit(struct hme_softc *);
102 void hme_mifinit(struct hme_softc *);
103 void hme_reset(struct hme_softc *);
104 void hme_setladrf(struct hme_softc *);
105 int hme_newbuf(struct hme_softc *, struct hme_sxd *, int);
106 int hme_encap(struct hme_softc *, struct mbuf *, int *);
107
108 /* MII methods & callbacks */
109 static int hme_mii_readreg(struct device *, int, int);
110 static void hme_mii_writereg(struct device *, int, int, int);
111 static void hme_mii_statchg(struct device *);
112
113 int hme_mediachange(struct ifnet *);
114 void hme_mediastatus(struct ifnet *, struct ifmediareq *);
115
116 int hme_eint(struct hme_softc *, u_int);
117 int hme_rint(struct hme_softc *);
118 int hme_tint(struct hme_softc *);
119
120 void
hme_config(sc)121 hme_config(sc)
122 struct hme_softc *sc;
123 {
124 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
125 struct mii_data *mii = &sc->sc_mii;
126 struct mii_softc *child;
127 bus_dma_tag_t dmatag = sc->sc_dmatag;
128 bus_dma_segment_t seg;
129 bus_size_t size;
130 int rseg, error, i;
131
132 /*
133 * HME common initialization.
134 *
135 * hme_softc fields that must be initialized by the front-end:
136 *
137 * the bus tag:
138 * sc_bustag
139 *
140 * the dma bus tag:
141 * sc_dmatag
142 *
143 * the bus handles:
144 * sc_seb (Shared Ethernet Block registers)
145 * sc_erx (Receiver Unit registers)
146 * sc_etx (Transmitter Unit registers)
147 * sc_mac (MAC registers)
148 * sc_mif (Management Interface registers)
149 *
150 * the maximum bus burst size:
151 * sc_burst
152 *
153 * the local Ethernet address:
154 * sc_enaddr
155 *
156 */
157
158 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
159
160 /* Make sure the chip is stopped. */
161 hme_stop(sc);
162
163
164 for (i = 0; i < HME_TX_RING_SIZE; i++) {
165 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
166 MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
167 &sc->sc_txd[i].sd_map) != 0) {
168 sc->sc_txd[i].sd_map = NULL;
169 goto fail;
170 }
171 }
172 for (i = 0; i < HME_RX_RING_SIZE; i++) {
173 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
174 MCLBYTES, 0, BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
175 &sc->sc_rxd[i].sd_map) != 0) {
176 sc->sc_rxd[i].sd_map = NULL;
177 goto fail;
178 }
179 }
180 if (bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1, MCLBYTES, 0,
181 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &sc->sc_rxmap_spare) != 0) {
182 sc->sc_rxmap_spare = NULL;
183 goto fail;
184 }
185
186 /*
187 * Allocate DMA capable memory
188 * Buffer descriptors must be aligned on a 2048 byte boundary;
189 * take this into account when calculating the size. Note that
190 * the maximum number of descriptors (256) occupies 2048 bytes,
191 * so we allocate that much regardless of the number of descriptors.
192 */
193 size = (HME_XD_SIZE * HME_RX_RING_MAX) + /* RX descriptors */
194 (HME_XD_SIZE * HME_TX_RING_MAX); /* TX descriptors */
195
196 /* Allocate DMA buffer */
197 if ((error = bus_dmamem_alloc(dmatag, size, 2048, 0, &seg, 1, &rseg,
198 BUS_DMA_NOWAIT)) != 0) {
199 printf("%s: DMA buffer alloc error %d\n",
200 sc->sc_dev.dv_xname, error);
201 return;
202 }
203
204 /* Map DMA memory in CPU addressable space */
205 if ((error = bus_dmamem_map(dmatag, &seg, rseg, size,
206 &sc->sc_rb.rb_membase, BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
207 printf("%s: DMA buffer map error %d\n",
208 sc->sc_dev.dv_xname, error);
209 bus_dmamap_unload(dmatag, sc->sc_dmamap);
210 bus_dmamem_free(dmatag, &seg, rseg);
211 return;
212 }
213
214 if ((error = bus_dmamap_create(dmatag, size, 1, size, 0,
215 BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) {
216 printf("%s: DMA map create error %d\n",
217 sc->sc_dev.dv_xname, error);
218 return;
219 }
220
221 /* Load the buffer */
222 if ((error = bus_dmamap_load(dmatag, sc->sc_dmamap,
223 sc->sc_rb.rb_membase, size, NULL,
224 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
225 printf("%s: DMA buffer map load error %d\n",
226 sc->sc_dev.dv_xname, error);
227 bus_dmamem_free(dmatag, &seg, rseg);
228 return;
229 }
230 sc->sc_rb.rb_dmabase = sc->sc_dmamap->dm_segs[0].ds_addr;
231
232 printf(": address %s\n", ether_sprintf(sc->sc_enaddr));
233
234 /* Initialize ifnet structure. */
235 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
236 ifp->if_softc = sc;
237 ifp->if_start = hme_start;
238 ifp->if_ioctl = hme_ioctl;
239 ifp->if_watchdog = hme_watchdog;
240 ifp->if_flags =
241 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
242 IFQ_SET_READY(&ifp->if_snd);
243 ifp->if_capabilities |= IFCAP_VLAN_MTU;
244
245 /* Initialize ifmedia structures and MII info */
246 mii->mii_ifp = ifp;
247 mii->mii_readreg = hme_mii_readreg;
248 mii->mii_writereg = hme_mii_writereg;
249 mii->mii_statchg = hme_mii_statchg;
250
251 ifmedia_init(&mii->mii_media, IFM_IMASK,
252 hme_mediachange, hme_mediastatus);
253
254 hme_mifinit(sc);
255
256 if (sc->sc_tcvr == -1)
257 mii_attach(&sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
258 MII_OFFSET_ANY, 0);
259 else
260 mii_attach(&sc->sc_dev, mii, 0xffffffff, sc->sc_tcvr,
261 MII_OFFSET_ANY, 0);
262
263 child = LIST_FIRST(&mii->mii_phys);
264 if (child == NULL) {
265 /* No PHY attached */
266 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
267 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
268 } else {
269 /*
270 * Walk along the list of attached MII devices and
271 * establish an `MII instance' to `phy number'
272 * mapping. We'll use this mapping in media change
273 * requests to determine which phy to use to program
274 * the MIF configuration register.
275 */
276 for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
277 /*
278 * Note: we support just two PHYs: the built-in
279 * internal device and an external on the MII
280 * connector.
281 */
282 if (child->mii_phy > 1 || child->mii_inst > 1) {
283 printf("%s: cannot accommodate MII device %s"
284 " at phy %d, instance %d\n",
285 sc->sc_dev.dv_xname,
286 child->mii_dev.dv_xname,
287 child->mii_phy, child->mii_inst);
288 continue;
289 }
290
291 sc->sc_phys[child->mii_inst] = child->mii_phy;
292 }
293
294 /*
295 * XXX - we can really do the following ONLY if the
296 * phy indeed has the auto negotiation capability!!
297 */
298 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
299 }
300
301 /* Attach the interface. */
302 if_attach(ifp);
303 ether_ifattach(ifp);
304
305 sc->sc_sh = shutdownhook_establish(hme_shutdown, sc);
306 if (sc->sc_sh == NULL)
307 panic("hme_config: can't establish shutdownhook");
308
309 timeout_set(&sc->sc_tick_ch, hme_tick, sc);
310 return;
311
312 fail:
313 if (sc->sc_rxmap_spare != NULL)
314 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_rxmap_spare);
315 for (i = 0; i < HME_TX_RING_SIZE; i++)
316 if (sc->sc_txd[i].sd_map != NULL)
317 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_txd[i].sd_map);
318 for (i = 0; i < HME_RX_RING_SIZE; i++)
319 if (sc->sc_rxd[i].sd_map != NULL)
320 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_rxd[i].sd_map);
321 }
322
323 void
hme_tick(arg)324 hme_tick(arg)
325 void *arg;
326 {
327 struct hme_softc *sc = arg;
328 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
329 bus_space_tag_t t = sc->sc_bustag;
330 bus_space_handle_t mac = sc->sc_mac;
331 int s;
332
333 s = splnet();
334 /*
335 * Unload collision counters
336 */
337 ifp->if_collisions +=
338 bus_space_read_4(t, mac, HME_MACI_NCCNT) +
339 bus_space_read_4(t, mac, HME_MACI_FCCNT) +
340 bus_space_read_4(t, mac, HME_MACI_EXCNT) +
341 bus_space_read_4(t, mac, HME_MACI_LTCNT);
342
343 /*
344 * then clear the hardware counters.
345 */
346 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
347 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
348 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
349 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
350
351 mii_tick(&sc->sc_mii);
352 splx(s);
353
354 timeout_add(&sc->sc_tick_ch, hz);
355 }
356
357 void
hme_reset(sc)358 hme_reset(sc)
359 struct hme_softc *sc;
360 {
361 int s;
362
363 s = splnet();
364 hme_init(sc);
365 splx(s);
366 }
367
368 void
hme_stop(sc)369 hme_stop(sc)
370 struct hme_softc *sc;
371 {
372 bus_space_tag_t t = sc->sc_bustag;
373 bus_space_handle_t seb = sc->sc_seb;
374 int n;
375
376 timeout_del(&sc->sc_tick_ch);
377 mii_down(&sc->sc_mii);
378
379 /* Mask all interrupts */
380 bus_space_write_4(t, seb, HME_SEBI_IMASK, 0xffffffff);
381
382 /* Reset transmitter and receiver */
383 bus_space_write_4(t, seb, HME_SEBI_RESET,
384 (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX));
385
386 for (n = 0; n < 20; n++) {
387 u_int32_t v = bus_space_read_4(t, seb, HME_SEBI_RESET);
388 if ((v & (HME_SEB_RESET_ETX | HME_SEB_RESET_ERX)) == 0)
389 break;
390 DELAY(20);
391 }
392 if (n >= 20)
393 printf("%s: hme_stop: reset failed\n", sc->sc_dev.dv_xname);
394
395 for (n = 0; n < HME_TX_RING_SIZE; n++) {
396 if (sc->sc_txd[n].sd_loaded) {
397 bus_dmamap_sync(sc->sc_dmatag, sc->sc_txd[n].sd_map,
398 0, sc->sc_txd[n].sd_map->dm_mapsize,
399 BUS_DMASYNC_POSTWRITE);
400 bus_dmamap_unload(sc->sc_dmatag, sc->sc_txd[n].sd_map);
401 sc->sc_txd[n].sd_loaded = 0;
402 }
403 if (sc->sc_txd[n].sd_mbuf != NULL) {
404 m_freem(sc->sc_txd[n].sd_mbuf);
405 sc->sc_txd[n].sd_mbuf = NULL;
406 }
407 }
408 }
409
410 void
hme_meminit(sc)411 hme_meminit(sc)
412 struct hme_softc *sc;
413 {
414 bus_addr_t dma;
415 caddr_t p;
416 unsigned int i;
417 struct hme_ring *hr = &sc->sc_rb;
418
419 p = hr->rb_membase;
420 dma = hr->rb_dmabase;
421
422 /*
423 * Allocate transmit descriptors
424 */
425 hr->rb_txd = p;
426 hr->rb_txddma = dma;
427 p += HME_TX_RING_SIZE * HME_XD_SIZE;
428 dma += HME_TX_RING_SIZE * HME_XD_SIZE;
429 /* We have reserved descriptor space until the next 2048 byte boundary.*/
430 dma = (bus_addr_t)roundup((u_long)dma, 2048);
431 p = (caddr_t)roundup((u_long)p, 2048);
432
433 /*
434 * Allocate receive descriptors
435 */
436 hr->rb_rxd = p;
437 hr->rb_rxddma = dma;
438 p += HME_RX_RING_SIZE * HME_XD_SIZE;
439 dma += HME_RX_RING_SIZE * HME_XD_SIZE;
440 /* Again move forward to the next 2048 byte boundary.*/
441 dma = (bus_addr_t)roundup((u_long)dma, 2048);
442 p = (caddr_t)roundup((u_long)p, 2048);
443
444 /*
445 * Initialize transmit descriptors
446 */
447 for (i = 0; i < HME_TX_RING_SIZE; i++) {
448 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, i, 0);
449 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, i, 0);
450 sc->sc_txd[i].sd_mbuf = NULL;
451 }
452
453 /*
454 * Initialize receive descriptors
455 */
456 for (i = 0; i < HME_RX_RING_SIZE; i++) {
457 if (hme_newbuf(sc, &sc->sc_rxd[i], 1)) {
458 printf("%s: rx allocation failed\n",
459 sc->sc_dev.dv_xname);
460 break;
461 }
462 HME_XD_SETADDR(sc->sc_pci, hr->rb_rxd, i,
463 sc->sc_rxd[i].sd_map->dm_segs[0].ds_addr);
464 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_rxd, i,
465 HME_XD_OWN | HME_XD_ENCODE_RSIZE(HME_RX_PKTSIZE));
466 }
467
468 sc->sc_tx_prod = sc->sc_tx_cons = sc->sc_tx_cnt = 0;
469 sc->sc_last_rd = 0;
470 }
471
472 /*
473 * Initialization of interface; set up initialization block
474 * and transmit/receive descriptor rings.
475 */
476 void
hme_init(sc)477 hme_init(sc)
478 struct hme_softc *sc;
479 {
480 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
481 bus_space_tag_t t = sc->sc_bustag;
482 bus_space_handle_t seb = sc->sc_seb;
483 bus_space_handle_t etx = sc->sc_etx;
484 bus_space_handle_t erx = sc->sc_erx;
485 bus_space_handle_t mac = sc->sc_mac;
486 u_int8_t *ea;
487 u_int32_t v;
488
489 /*
490 * Initialization sequence. The numbered steps below correspond
491 * to the sequence outlined in section 6.3.5.1 in the Ethernet
492 * Channel Engine manual (part of the PCIO manual).
493 * See also the STP2002-STQ document from Sun Microsystems.
494 */
495
496 /* step 1 & 2. Reset the Ethernet Channel */
497 hme_stop(sc);
498
499 /* Re-initialize the MIF */
500 hme_mifinit(sc);
501
502 /* Call MI reset function if any */
503 if (sc->sc_hwreset)
504 (*sc->sc_hwreset)(sc);
505
506 #if 0
507 /* Mask all MIF interrupts, just in case */
508 bus_space_write_4(t, mif, HME_MIFI_IMASK, 0xffff);
509 #endif
510
511 /* step 3. Setup data structures in host memory */
512 hme_meminit(sc);
513
514 /* step 4. TX MAC registers & counters */
515 bus_space_write_4(t, mac, HME_MACI_NCCNT, 0);
516 bus_space_write_4(t, mac, HME_MACI_FCCNT, 0);
517 bus_space_write_4(t, mac, HME_MACI_EXCNT, 0);
518 bus_space_write_4(t, mac, HME_MACI_LTCNT, 0);
519 bus_space_write_4(t, mac, HME_MACI_TXSIZE, HME_MTU);
520
521 /* Load station MAC address */
522 ea = sc->sc_enaddr;
523 bus_space_write_4(t, mac, HME_MACI_MACADDR0, (ea[0] << 8) | ea[1]);
524 bus_space_write_4(t, mac, HME_MACI_MACADDR1, (ea[2] << 8) | ea[3]);
525 bus_space_write_4(t, mac, HME_MACI_MACADDR2, (ea[4] << 8) | ea[5]);
526
527 /*
528 * Init seed for backoff
529 * (source suggested by manual: low 10 bits of MAC address)
530 */
531 v = ((ea[4] << 8) | ea[5]) & 0x3fff;
532 bus_space_write_4(t, mac, HME_MACI_RANDSEED, v);
533
534
535 /* Note: Accepting power-on default for other MAC registers here.. */
536
537
538 /* step 5. RX MAC registers & counters */
539 hme_setladrf(sc);
540
541 /* step 6 & 7. Program Descriptor Ring Base Addresses */
542 bus_space_write_4(t, etx, HME_ETXI_RING, sc->sc_rb.rb_txddma);
543 bus_space_write_4(t, etx, HME_ETXI_RSIZE, HME_TX_RING_SIZE);
544
545 bus_space_write_4(t, erx, HME_ERXI_RING, sc->sc_rb.rb_rxddma);
546 bus_space_write_4(t, mac, HME_MACI_RXSIZE, HME_MTU);
547
548 /* step 8. Global Configuration & Interrupt Mask */
549 bus_space_write_4(t, seb, HME_SEBI_IMASK,
550 ~(HME_SEB_STAT_HOSTTOTX | HME_SEB_STAT_RXTOHOST |
551 HME_SEB_STAT_TXALL | HME_SEB_STAT_TXPERR |
552 HME_SEB_STAT_RCNTEXP | HME_SEB_STAT_ALL_ERRORS));
553
554 switch (sc->sc_burst) {
555 default:
556 v = 0;
557 break;
558 case 16:
559 v = HME_SEB_CFG_BURST16;
560 break;
561 case 32:
562 v = HME_SEB_CFG_BURST32;
563 break;
564 case 64:
565 v = HME_SEB_CFG_BURST64;
566 break;
567 }
568 bus_space_write_4(t, seb, HME_SEBI_CFG, v);
569
570 /* step 9. ETX Configuration: use mostly default values */
571
572 /* Enable DMA */
573 v = bus_space_read_4(t, etx, HME_ETXI_CFG);
574 v |= HME_ETX_CFG_DMAENABLE;
575 bus_space_write_4(t, etx, HME_ETXI_CFG, v);
576
577 /* Transmit Descriptor ring size: in increments of 16 */
578 bus_space_write_4(t, etx, HME_ETXI_RSIZE, HME_TX_RING_SIZE / 16 - 1);
579
580 /* step 10. ERX Configuration */
581 v = bus_space_read_4(t, erx, HME_ERXI_CFG);
582 v &= ~HME_ERX_CFG_RINGSIZE256;
583 #if HME_RX_RING_SIZE == 32
584 v |= HME_ERX_CFG_RINGSIZE32;
585 #elif HME_RX_RING_SIZE == 64
586 v |= HME_ERX_CFG_RINGSIZE64;
587 #elif HME_RX_RING_SIZE == 128
588 v |= HME_ERX_CFG_RINGSIZE128;
589 #elif HME_RX_RING_SIZE == 256
590 v |= HME_ERX_CFG_RINGSIZE256;
591 #else
592 # error "RX ring size must be 32, 64, 128, or 256"
593 #endif
594 /* Enable DMA */
595 v |= HME_ERX_CFG_DMAENABLE | (HME_RX_OFFSET << 3);
596 bus_space_write_4(t, erx, HME_ERXI_CFG, v);
597
598 /* step 11. XIF Configuration */
599 v = bus_space_read_4(t, mac, HME_MACI_XIF);
600 v |= HME_MAC_XIF_OE;
601 bus_space_write_4(t, mac, HME_MACI_XIF, v);
602
603 /* step 12. RX_MAC Configuration Register */
604 v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
605 v |= HME_MAC_RXCFG_ENABLE;
606 bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
607
608 /* step 13. TX_MAC Configuration Register */
609 v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
610 v |= (HME_MAC_TXCFG_ENABLE | HME_MAC_TXCFG_DGIVEUP);
611 bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
612
613 /* step 14. Issue Transmit Pending command */
614
615 /* Call MI initialization function if any */
616 if (sc->sc_hwinit)
617 (*sc->sc_hwinit)(sc);
618
619 /* Start the one second timer. */
620 timeout_add(&sc->sc_tick_ch, hz);
621
622 ifp->if_flags |= IFF_RUNNING;
623 ifp->if_flags &= ~IFF_OACTIVE;
624 ifp->if_timer = 0;
625 hme_start(ifp);
626 }
627
628 void
hme_start(ifp)629 hme_start(ifp)
630 struct ifnet *ifp;
631 {
632 struct hme_softc *sc = (struct hme_softc *)ifp->if_softc;
633 struct mbuf *m;
634 int bix, cnt = 0;
635
636 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
637 return;
638
639 bix = sc->sc_tx_prod;
640 while (sc->sc_txd[bix].sd_mbuf == NULL) {
641 IFQ_POLL(&ifp->if_snd, m);
642 if (m == NULL)
643 break;
644
645 #if NBPFILTER > 0
646 /*
647 * If BPF is listening on this interface, let it see the
648 * packet before we commit it to the wire.
649 */
650 if (ifp->if_bpf)
651 bpf_mtap(ifp->if_bpf, m);
652 #endif
653
654 if (hme_encap(sc, m, &bix)) {
655 ifp->if_flags |= IFF_OACTIVE;
656 break;
657 }
658
659 IFQ_DEQUEUE(&ifp->if_snd, m);
660
661 bus_space_write_4(sc->sc_bustag, sc->sc_etx, HME_ETXI_PENDING,
662 HME_ETX_TP_DMAWAKEUP);
663 cnt++;
664 }
665
666 if (cnt != 0) {
667 sc->sc_tx_prod = bix;
668 ifp->if_timer = 5;
669 }
670 }
671
672 /*
673 * Transmit interrupt.
674 */
675 int
hme_tint(sc)676 hme_tint(sc)
677 struct hme_softc *sc;
678 {
679 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
680 unsigned int ri, txflags;
681 struct hme_sxd *sd;
682 int cnt = sc->sc_tx_cnt;
683
684 /* Fetch current position in the transmit ring */
685 ri = sc->sc_tx_cons;
686 sd = &sc->sc_txd[ri];
687
688 for (;;) {
689 if (cnt <= 0)
690 break;
691
692 txflags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_txd, ri);
693
694 if (txflags & HME_XD_OWN)
695 break;
696
697 ifp->if_flags &= ~IFF_OACTIVE;
698 if (txflags & HME_XD_EOP)
699 ifp->if_opackets++;
700
701 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map,
702 0, sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
703 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
704 sd->sd_loaded = 0;
705
706 if (sd->sd_mbuf != NULL) {
707 m_freem(sd->sd_mbuf);
708 sd->sd_mbuf = NULL;
709 }
710
711 if (++ri == HME_TX_RING_SIZE) {
712 ri = 0;
713 sd = sc->sc_txd;
714 } else
715 sd++;
716
717 --cnt;
718 }
719
720 sc->sc_tx_cnt = cnt;
721 ifp->if_timer = cnt > 0 ? 5 : 0;
722
723 /* Update ring */
724 sc->sc_tx_cons = ri;
725
726 hme_start(ifp);
727
728 return (1);
729 }
730
731 /*
732 * Receive interrupt.
733 */
734 int
hme_rint(sc)735 hme_rint(sc)
736 struct hme_softc *sc;
737 {
738 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
739 struct mbuf *m;
740 struct hme_sxd *sd;
741 unsigned int ri, len;
742 u_int32_t flags;
743
744 ri = sc->sc_last_rd;
745 sd = &sc->sc_rxd[ri];
746
747 /*
748 * Process all buffers with valid data.
749 */
750 for (;;) {
751 flags = HME_XD_GETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ri);
752 if (flags & HME_XD_OWN)
753 break;
754
755 if (flags & HME_XD_OFL) {
756 printf("%s: buffer overflow, ri=%d; flags=0x%x\n",
757 sc->sc_dev.dv_xname, ri, flags);
758 goto again;
759 }
760
761 m = sd->sd_mbuf;
762 len = HME_XD_DECODE_RSIZE(flags);
763 m->m_pkthdr.len = m->m_len = len;
764
765 if (hme_newbuf(sc, sd, 0)) {
766 /*
767 * Allocation of new mbuf cluster failed, leave the
768 * old one in place and keep going.
769 */
770 ifp->if_ierrors++;
771 goto again;
772 }
773
774 #if NBPFILTER > 0
775 if (ifp->if_bpf) {
776 m->m_pkthdr.len = m->m_len = len;
777 bpf_mtap(ifp->if_bpf, m);
778 }
779 #endif
780
781 ifp->if_ipackets++;
782 ether_input_mbuf(ifp, m);
783
784 again:
785 HME_XD_SETADDR(sc->sc_pci, sc->sc_rb.rb_rxd, ri,
786 sd->sd_map->dm_segs[0].ds_addr);
787 HME_XD_SETFLAGS(sc->sc_pci, sc->sc_rb.rb_rxd, ri,
788 HME_XD_OWN | HME_XD_ENCODE_RSIZE(HME_RX_PKTSIZE));
789
790 if (++ri == HME_RX_RING_SIZE) {
791 ri = 0;
792 sd = sc->sc_rxd;
793 } else
794 sd++;
795 }
796
797 sc->sc_last_rd = ri;
798 return (1);
799 }
800
801 int
hme_eint(sc,status)802 hme_eint(sc, status)
803 struct hme_softc *sc;
804 u_int status;
805 {
806 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
807
808 if (status & HME_SEB_STAT_MIFIRQ) {
809 printf("%s: XXXlink status changed\n", sc->sc_dev.dv_xname);
810 status &= ~HME_SEB_STAT_MIFIRQ;
811 }
812
813 if (status & HME_SEB_STAT_DTIMEXP) {
814 ifp->if_oerrors++;
815 status &= ~HME_SEB_STAT_DTIMEXP;
816 }
817
818 if (status & HME_SEB_STAT_NORXD) {
819 ifp->if_ierrors++;
820 status &= ~HME_SEB_STAT_NORXD;
821 }
822
823 status &= ~(HME_SEB_STAT_RXTOHOST | HME_SEB_STAT_GOTFRAME |
824 HME_SEB_STAT_SENTFRAME | HME_SEB_STAT_HOSTTOTX |
825 HME_SEB_STAT_TXALL);
826
827 if (status == 0)
828 return (1);
829
830 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, HME_SEB_STAT_BITS);
831 return (1);
832 }
833
834 int
hme_intr(v)835 hme_intr(v)
836 void *v;
837 {
838 struct hme_softc *sc = (struct hme_softc *)v;
839 bus_space_tag_t t = sc->sc_bustag;
840 bus_space_handle_t seb = sc->sc_seb;
841 u_int32_t status;
842 int r = 0;
843
844 status = bus_space_read_4(t, seb, HME_SEBI_STAT);
845
846 if ((status & HME_SEB_STAT_ALL_ERRORS) != 0)
847 r |= hme_eint(sc, status);
848
849 if ((status & (HME_SEB_STAT_TXALL | HME_SEB_STAT_HOSTTOTX)) != 0)
850 r |= hme_tint(sc);
851
852 if ((status & HME_SEB_STAT_RXTOHOST) != 0)
853 r |= hme_rint(sc);
854
855 return (r);
856 }
857
858
859 void
hme_watchdog(ifp)860 hme_watchdog(ifp)
861 struct ifnet *ifp;
862 {
863 struct hme_softc *sc = ifp->if_softc;
864
865 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
866 ifp->if_oerrors++;
867
868 hme_reset(sc);
869 }
870
871 /*
872 * Initialize the MII Management Interface
873 */
874 void
hme_mifinit(sc)875 hme_mifinit(sc)
876 struct hme_softc *sc;
877 {
878 bus_space_tag_t t = sc->sc_bustag;
879 bus_space_handle_t mif = sc->sc_mif;
880 bus_space_handle_t mac = sc->sc_mac;
881 int phy;
882 u_int32_t v;
883
884 v = bus_space_read_4(t, mif, HME_MIFI_CFG);
885 phy = HME_PHYAD_EXTERNAL;
886 if (v & HME_MIF_CFG_MDI1)
887 phy = sc->sc_tcvr = HME_PHYAD_EXTERNAL;
888 else if (v & HME_MIF_CFG_MDI0)
889 phy = sc->sc_tcvr = HME_PHYAD_INTERNAL;
890 else
891 sc->sc_tcvr = -1;
892
893 /* Configure the MIF in frame mode, no poll, current phy select */
894 v = 0;
895 if (phy == HME_PHYAD_EXTERNAL)
896 v |= HME_MIF_CFG_PHY;
897 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
898
899 /* If an external transceiver is selected, enable its MII drivers */
900 v = bus_space_read_4(t, mac, HME_MACI_XIF);
901 v &= ~HME_MAC_XIF_MIIENABLE;
902 if (phy == HME_PHYAD_EXTERNAL)
903 v |= HME_MAC_XIF_MIIENABLE;
904 bus_space_write_4(t, mac, HME_MACI_XIF, v);
905 }
906
907 /*
908 * MII interface
909 */
910 static int
hme_mii_readreg(self,phy,reg)911 hme_mii_readreg(self, phy, reg)
912 struct device *self;
913 int phy, reg;
914 {
915 struct hme_softc *sc = (struct hme_softc *)self;
916 bus_space_tag_t t = sc->sc_bustag;
917 bus_space_handle_t mif = sc->sc_mif;
918 bus_space_handle_t mac = sc->sc_mac;
919 u_int32_t v, xif_cfg, mifi_cfg;
920 int n;
921
922 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
923 return (0);
924
925 /* Select the desired PHY in the MIF configuration register */
926 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
927 v &= ~HME_MIF_CFG_PHY;
928 if (phy == HME_PHYAD_EXTERNAL)
929 v |= HME_MIF_CFG_PHY;
930 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
931
932 /* Enable MII drivers on external transceiver */
933 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
934 if (phy == HME_PHYAD_EXTERNAL)
935 v |= HME_MAC_XIF_MIIENABLE;
936 else
937 v &= ~HME_MAC_XIF_MIIENABLE;
938 bus_space_write_4(t, mac, HME_MACI_XIF, v);
939
940 /* Construct the frame command */
941 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) |
942 HME_MIF_FO_TAMSB |
943 (MII_COMMAND_READ << HME_MIF_FO_OPC_SHIFT) |
944 (phy << HME_MIF_FO_PHYAD_SHIFT) |
945 (reg << HME_MIF_FO_REGAD_SHIFT);
946
947 bus_space_write_4(t, mif, HME_MIFI_FO, v);
948 for (n = 0; n < 100; n++) {
949 DELAY(1);
950 v = bus_space_read_4(t, mif, HME_MIFI_FO);
951 if (v & HME_MIF_FO_TALSB) {
952 v &= HME_MIF_FO_DATA;
953 goto out;
954 }
955 }
956
957 v = 0;
958 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname);
959
960 out:
961 /* Restore MIFI_CFG register */
962 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
963 /* Restore XIF register */
964 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
965 return (v);
966 }
967
968 static void
hme_mii_writereg(self,phy,reg,val)969 hme_mii_writereg(self, phy, reg, val)
970 struct device *self;
971 int phy, reg, val;
972 {
973 struct hme_softc *sc = (void *)self;
974 bus_space_tag_t t = sc->sc_bustag;
975 bus_space_handle_t mif = sc->sc_mif;
976 bus_space_handle_t mac = sc->sc_mac;
977 u_int32_t v, xif_cfg, mifi_cfg;
978 int n;
979
980 /* We can at most have two PHYs */
981 if (phy != HME_PHYAD_EXTERNAL && phy != HME_PHYAD_INTERNAL)
982 return;
983
984 /* Select the desired PHY in the MIF configuration register */
985 v = mifi_cfg = bus_space_read_4(t, mif, HME_MIFI_CFG);
986 v &= ~HME_MIF_CFG_PHY;
987 if (phy == HME_PHYAD_EXTERNAL)
988 v |= HME_MIF_CFG_PHY;
989 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
990
991 /* Enable MII drivers on external transceiver */
992 v = xif_cfg = bus_space_read_4(t, mac, HME_MACI_XIF);
993 if (phy == HME_PHYAD_EXTERNAL)
994 v |= HME_MAC_XIF_MIIENABLE;
995 else
996 v &= ~HME_MAC_XIF_MIIENABLE;
997 bus_space_write_4(t, mac, HME_MACI_XIF, v);
998
999 /* Construct the frame command */
1000 v = (MII_COMMAND_START << HME_MIF_FO_ST_SHIFT) |
1001 HME_MIF_FO_TAMSB |
1002 (MII_COMMAND_WRITE << HME_MIF_FO_OPC_SHIFT) |
1003 (phy << HME_MIF_FO_PHYAD_SHIFT) |
1004 (reg << HME_MIF_FO_REGAD_SHIFT) |
1005 (val & HME_MIF_FO_DATA);
1006
1007 bus_space_write_4(t, mif, HME_MIFI_FO, v);
1008 for (n = 0; n < 100; n++) {
1009 DELAY(1);
1010 v = bus_space_read_4(t, mif, HME_MIFI_FO);
1011 if (v & HME_MIF_FO_TALSB)
1012 goto out;
1013 }
1014
1015 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname);
1016 out:
1017 /* Restore MIFI_CFG register */
1018 bus_space_write_4(t, mif, HME_MIFI_CFG, mifi_cfg);
1019 /* Restore XIF register */
1020 bus_space_write_4(t, mac, HME_MACI_XIF, xif_cfg);
1021 }
1022
1023 static void
hme_mii_statchg(dev)1024 hme_mii_statchg(dev)
1025 struct device *dev;
1026 {
1027 struct hme_softc *sc = (void *)dev;
1028 bus_space_tag_t t = sc->sc_bustag;
1029 bus_space_handle_t mac = sc->sc_mac;
1030 u_int32_t v;
1031
1032 #ifdef HMEDEBUG
1033 if (sc->sc_debug)
1034 printf("hme_mii_statchg: status change\n", phy);
1035 #endif
1036
1037 /* Set the MAC Full Duplex bit appropriately */
1038 /* Apparently the hme chip is SIMPLE if working in full duplex mode,
1039 but not otherwise. */
1040 v = bus_space_read_4(t, mac, HME_MACI_TXCFG);
1041 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
1042 v |= HME_MAC_TXCFG_FULLDPLX;
1043 sc->sc_arpcom.ac_if.if_flags |= IFF_SIMPLEX;
1044 } else {
1045 v &= ~HME_MAC_TXCFG_FULLDPLX;
1046 sc->sc_arpcom.ac_if.if_flags &= ~IFF_SIMPLEX;
1047 }
1048 bus_space_write_4(t, mac, HME_MACI_TXCFG, v);
1049 }
1050
1051 int
hme_mediachange(ifp)1052 hme_mediachange(ifp)
1053 struct ifnet *ifp;
1054 {
1055 struct hme_softc *sc = ifp->if_softc;
1056 bus_space_tag_t t = sc->sc_bustag;
1057 bus_space_handle_t mif = sc->sc_mif;
1058 bus_space_handle_t mac = sc->sc_mac;
1059 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1060 int phy = sc->sc_phys[instance];
1061 u_int32_t v;
1062
1063 #ifdef HMEDEBUG
1064 if (sc->sc_debug)
1065 printf("hme_mediachange: phy = %d\n", phy);
1066 #endif
1067 if (IFM_TYPE(sc->sc_media.ifm_media) != IFM_ETHER)
1068 return (EINVAL);
1069
1070 /* Select the current PHY in the MIF configuration register */
1071 v = bus_space_read_4(t, mif, HME_MIFI_CFG);
1072 v &= ~HME_MIF_CFG_PHY;
1073 if (phy == HME_PHYAD_EXTERNAL)
1074 v |= HME_MIF_CFG_PHY;
1075 bus_space_write_4(t, mif, HME_MIFI_CFG, v);
1076
1077 /* If an external transceiver is selected, enable its MII drivers */
1078 v = bus_space_read_4(t, mac, HME_MACI_XIF);
1079 v &= ~HME_MAC_XIF_MIIENABLE;
1080 if (phy == HME_PHYAD_EXTERNAL)
1081 v |= HME_MAC_XIF_MIIENABLE;
1082 bus_space_write_4(t, mac, HME_MACI_XIF, v);
1083
1084 return (mii_mediachg(&sc->sc_mii));
1085 }
1086
1087 void
hme_mediastatus(ifp,ifmr)1088 hme_mediastatus(ifp, ifmr)
1089 struct ifnet *ifp;
1090 struct ifmediareq *ifmr;
1091 {
1092 struct hme_softc *sc = ifp->if_softc;
1093
1094 if ((ifp->if_flags & IFF_UP) == 0)
1095 return;
1096
1097 mii_pollstat(&sc->sc_mii);
1098 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1099 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1100 }
1101
1102 /*
1103 * Process an ioctl request.
1104 */
1105 int
hme_ioctl(ifp,cmd,data)1106 hme_ioctl(ifp, cmd, data)
1107 struct ifnet *ifp;
1108 u_long cmd;
1109 caddr_t data;
1110 {
1111 struct hme_softc *sc = ifp->if_softc;
1112 struct ifaddr *ifa = (struct ifaddr *)data;
1113 struct ifreq *ifr = (struct ifreq *)data;
1114 int s, error = 0;
1115
1116 s = splnet();
1117
1118 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
1119 splx(s);
1120 return (error);
1121 }
1122
1123 switch (cmd) {
1124
1125 case SIOCSIFADDR:
1126 ifp->if_flags |= IFF_UP;
1127
1128 switch (ifa->ifa_addr->sa_family) {
1129 #ifdef INET
1130 case AF_INET:
1131 hme_init(sc);
1132 arp_ifinit(&sc->sc_arpcom, ifa);
1133 break;
1134 #endif
1135 default:
1136 hme_init(sc);
1137 break;
1138 }
1139 break;
1140
1141 case SIOCSIFFLAGS:
1142 if ((ifp->if_flags & IFF_UP) == 0 &&
1143 (ifp->if_flags & IFF_RUNNING) != 0) {
1144 /*
1145 * If interface is marked down and it is running, then
1146 * stop it.
1147 */
1148 hme_stop(sc);
1149 ifp->if_flags &= ~IFF_RUNNING;
1150 } else if ((ifp->if_flags & IFF_UP) != 0 &&
1151 (ifp->if_flags & IFF_RUNNING) == 0) {
1152 /*
1153 * If interface is marked up and it is stopped, then
1154 * start it.
1155 */
1156 hme_init(sc);
1157 } else if ((ifp->if_flags & IFF_UP) != 0) {
1158 /*
1159 * Reset the interface to pick up changes in any other
1160 * flags that affect hardware registers.
1161 */
1162 hme_init(sc);
1163 }
1164 #ifdef HMEDEBUG
1165 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
1166 #endif
1167 break;
1168
1169 case SIOCADDMULTI:
1170 case SIOCDELMULTI:
1171 error = (cmd == SIOCADDMULTI) ?
1172 ether_addmulti(ifr, &sc->sc_arpcom) :
1173 ether_delmulti(ifr, &sc->sc_arpcom);
1174
1175 if (error == ENETRESET) {
1176 /*
1177 * Multicast list has changed; set the hardware filter
1178 * accordingly.
1179 */
1180 hme_setladrf(sc);
1181 error = 0;
1182 }
1183 break;
1184
1185 case SIOCGIFMEDIA:
1186 case SIOCSIFMEDIA:
1187 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
1188 break;
1189
1190 default:
1191 error = ENOTTY;
1192 break;
1193 }
1194
1195 splx(s);
1196 return (error);
1197 }
1198
1199 void
hme_shutdown(arg)1200 hme_shutdown(arg)
1201 void *arg;
1202 {
1203 hme_stop((struct hme_softc *)arg);
1204 }
1205
1206 /*
1207 * Set up the logical address filter.
1208 */
1209 void
hme_setladrf(sc)1210 hme_setladrf(sc)
1211 struct hme_softc *sc;
1212 {
1213 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1214 struct ether_multi *enm;
1215 struct ether_multistep step;
1216 struct arpcom *ac = &sc->sc_arpcom;
1217 bus_space_tag_t t = sc->sc_bustag;
1218 bus_space_handle_t mac = sc->sc_mac;
1219 u_char *cp;
1220 u_int32_t crc;
1221 u_int32_t hash[4];
1222 u_int32_t v;
1223 int len;
1224
1225 /* Clear hash table */
1226 hash[3] = hash[2] = hash[1] = hash[0] = 0;
1227
1228 /* Get current RX configuration */
1229 v = bus_space_read_4(t, mac, HME_MACI_RXCFG);
1230
1231 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1232 /* Turn on promiscuous mode; turn off the hash filter */
1233 v |= HME_MAC_RXCFG_PMISC;
1234 v &= ~HME_MAC_RXCFG_HENABLE;
1235 ifp->if_flags |= IFF_ALLMULTI;
1236 goto chipit;
1237 }
1238
1239 /* Turn off promiscuous mode; turn on the hash filter */
1240 v &= ~HME_MAC_RXCFG_PMISC;
1241 v |= HME_MAC_RXCFG_HENABLE;
1242
1243 /*
1244 * Set up multicast address filter by passing all multicast addresses
1245 * through a crc generator, and then using the high order 6 bits as an
1246 * index into the 64 bit logical address filter. The high order bit
1247 * selects the word, while the rest of the bits select the bit within
1248 * the word.
1249 */
1250
1251 ETHER_FIRST_MULTI(step, ac, enm);
1252 while (enm != NULL) {
1253 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1254 /*
1255 * We must listen to a range of multicast addresses.
1256 * For now, just accept all multicasts, rather than
1257 * trying to set only those filter bits needed to match
1258 * the range. (At this time, the only use of address
1259 * ranges is for IP multicast routing, for which the
1260 * range is big enough to require all bits set.)
1261 */
1262 hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
1263 ifp->if_flags |= IFF_ALLMULTI;
1264 goto chipit;
1265 }
1266
1267 cp = enm->enm_addrlo;
1268 crc = 0xffffffff;
1269 for (len = sizeof(enm->enm_addrlo); --len >= 0;) {
1270 int octet = *cp++;
1271 int i;
1272
1273 #define MC_POLY_LE 0xedb88320UL /* mcast crc, little endian */
1274 for (i = 0; i < 8; i++) {
1275 if ((crc & 1) ^ (octet & 1)) {
1276 crc >>= 1;
1277 crc ^= MC_POLY_LE;
1278 } else {
1279 crc >>= 1;
1280 }
1281 octet >>= 1;
1282 }
1283 }
1284 /* Just want the 6 most significant bits. */
1285 crc >>= 26;
1286
1287 /* Set the corresponding bit in the filter. */
1288 hash[crc >> 4] |= 1 << (crc & 0xf);
1289
1290 ETHER_NEXT_MULTI(step, enm);
1291 }
1292
1293 ifp->if_flags &= ~IFF_ALLMULTI;
1294
1295 chipit:
1296 /* Now load the hash table into the chip */
1297 bus_space_write_4(t, mac, HME_MACI_HASHTAB0, hash[0]);
1298 bus_space_write_4(t, mac, HME_MACI_HASHTAB1, hash[1]);
1299 bus_space_write_4(t, mac, HME_MACI_HASHTAB2, hash[2]);
1300 bus_space_write_4(t, mac, HME_MACI_HASHTAB3, hash[3]);
1301 bus_space_write_4(t, mac, HME_MACI_RXCFG, v);
1302 }
1303
1304 int
hme_encap(sc,mhead,bixp)1305 hme_encap(sc, mhead, bixp)
1306 struct hme_softc *sc;
1307 struct mbuf *mhead;
1308 int *bixp;
1309 {
1310 struct hme_sxd *sd;
1311 struct mbuf *m;
1312 int frag, cur, cnt = 0;
1313 u_int32_t flags;
1314 struct hme_ring *hr = &sc->sc_rb;
1315
1316 cur = frag = *bixp;
1317 sd = &sc->sc_txd[frag];
1318
1319 for (m = mhead; m != NULL; m = m->m_next) {
1320 if (m->m_len == 0)
1321 continue;
1322
1323 if ((HME_TX_RING_SIZE - (sc->sc_tx_cnt + cnt)) < 5)
1324 goto err;
1325
1326 if (bus_dmamap_load(sc->sc_dmatag, sd->sd_map,
1327 mtod(m, caddr_t), m->m_len, NULL, BUS_DMA_NOWAIT) != 0)
1328 goto err;
1329
1330 sd->sd_loaded = 1;
1331 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
1332 sd->sd_map->dm_mapsize, BUS_DMASYNC_PREWRITE);
1333
1334 sd->sd_mbuf = NULL;
1335
1336 flags = HME_XD_ENCODE_TSIZE(m->m_len);
1337 if (cnt == 0)
1338 flags |= HME_XD_SOP;
1339 else
1340 flags |= HME_XD_OWN;
1341
1342 HME_XD_SETADDR(sc->sc_pci, hr->rb_txd, frag,
1343 sd->sd_map->dm_segs[0].ds_addr);
1344 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, frag, flags);
1345
1346 cur = frag;
1347 cnt++;
1348 if (++frag == HME_TX_RING_SIZE) {
1349 frag = 0;
1350 sd = sc->sc_txd;
1351 } else
1352 sd++;
1353 }
1354
1355 /* Set end of packet on last descriptor. */
1356 flags = HME_XD_GETFLAGS(sc->sc_pci, hr->rb_txd, cur);
1357 flags |= HME_XD_EOP;
1358 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, cur, flags);
1359 sc->sc_txd[cur].sd_mbuf = mhead;
1360
1361 /* Give first frame over to the hardware. */
1362 flags = HME_XD_GETFLAGS(sc->sc_pci, hr->rb_txd, (*bixp));
1363 flags |= HME_XD_OWN;
1364 HME_XD_SETFLAGS(sc->sc_pci, hr->rb_txd, (*bixp), flags);
1365
1366 sc->sc_tx_cnt += cnt;
1367 *bixp = frag;
1368
1369 /* sync descriptors */
1370
1371 return (0);
1372
1373 err:
1374 /*
1375 * Invalidate the stuff we may have already put into place. We
1376 * will be called again to queue it later.
1377 */
1378 for (; cnt > 0; cnt--) {
1379 if (--frag == -1)
1380 frag = HME_TX_RING_SIZE - 1;
1381 sd = &sc->sc_txd[frag];
1382 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
1383 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1384 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
1385 sd->sd_loaded = 0;
1386 sd->sd_mbuf = NULL;
1387 }
1388 return (ENOBUFS);
1389 }
1390
1391 int
hme_newbuf(sc,d,freeit)1392 hme_newbuf(sc, d, freeit)
1393 struct hme_softc *sc;
1394 struct hme_sxd *d;
1395 int freeit;
1396 {
1397 struct mbuf *m;
1398 bus_dmamap_t map;
1399
1400 /*
1401 * All operations should be on local variables and/or rx spare map
1402 * until we're sure everything is a success.
1403 */
1404
1405 MGETHDR(m, M_DONTWAIT, MT_DATA);
1406 if (m == NULL)
1407 return (ENOBUFS);
1408 m->m_pkthdr.rcvif = &sc->sc_arpcom.ac_if;
1409
1410 MCLGET(m, M_DONTWAIT);
1411 if ((m->m_flags & M_EXT) == 0) {
1412 m_freem(m);
1413 return (ENOBUFS);
1414 }
1415
1416 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_rxmap_spare,
1417 mtod(m, caddr_t), MCLBYTES - HME_RX_OFFSET, NULL,
1418 BUS_DMA_NOWAIT) != 0) {
1419 m_freem(m);
1420 return (ENOBUFS);
1421 }
1422
1423 /*
1424 * At this point we have a new buffer loaded into the spare map.
1425 * Just need to clear out the old mbuf/map and put the new one
1426 * in place.
1427 */
1428
1429 if (d->sd_loaded) {
1430 bus_dmamap_sync(sc->sc_dmatag, d->sd_map,
1431 0, d->sd_map->dm_mapsize, BUS_DMASYNC_POSTREAD);
1432 bus_dmamap_unload(sc->sc_dmatag, d->sd_map);
1433 d->sd_loaded = 0;
1434 }
1435
1436 if ((d->sd_mbuf != NULL) && freeit) {
1437 m_freem(d->sd_mbuf);
1438 d->sd_mbuf = NULL;
1439 }
1440
1441 map = d->sd_map;
1442 d->sd_map = sc->sc_rxmap_spare;
1443 sc->sc_rxmap_spare = map;
1444
1445 d->sd_loaded = 1;
1446
1447 bus_dmamap_sync(sc->sc_dmatag, d->sd_map, 0, d->sd_map->dm_mapsize,
1448 BUS_DMASYNC_PREREAD);
1449
1450 m->m_data += HME_RX_OFFSET;
1451 d->sd_mbuf = m;
1452 return (0);
1453 }
1454