1 /* $OpenBSD: gemvar.h,v 1.9 2003/10/21 18:58:49 jmc Exp $ */ 2 /* $NetBSD: gemvar.h,v 1.1 2001/09/16 00:11:43 eeh Exp $ */ 3 4 /* 5 * 6 * Copyright (C) 2001 Eduardo Horvath. 7 * All rights reserved. 8 * 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 */ 32 33 #ifndef _IF_GEMVAR_H 34 #define _IF_GEMVAR_H 35 36 #include <sys/queue.h> 37 #include <sys/timeout.h> 38 39 /* 40 * Misc. definitions for the Sun ``Gem'' Ethernet controller family driver. 41 */ 42 43 /* 44 * Transmit descriptor list size. This is arbitrary, but allocate 45 * enough descriptors for 64 pending transmissions and 16 segments 46 * per packet. 47 */ 48 #define GEM_NTXSEGS 16 49 50 #define GEM_TXQUEUELEN 64 51 #define GEM_NTXDESC (GEM_TXQUEUELEN * GEM_NTXSEGS) 52 #define GEM_NTXDESC_MASK (GEM_NTXDESC - 1) 53 #define GEM_NEXTTX(x) ((x + 1) & GEM_NTXDESC_MASK) 54 55 struct gem_sxd { 56 struct mbuf *sd_mbuf; 57 bus_dmamap_t sd_map; 58 }; 59 60 /* 61 * Receive descriptor list size. We have one Rx buffer per incoming 62 * packet, so this logic is a little simpler. 63 */ 64 #define GEM_NRXDESC 128 65 #define GEM_NRXDESC_MASK (GEM_NRXDESC - 1) 66 #define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK) 67 68 /* 69 * Control structures are DMA'd to the GEM chip. We allocate them in 70 * a single clump that maps to a single DMA segment to make several things 71 * easier. 72 */ 73 struct gem_control_data { 74 /* 75 * The transmit descriptors. 76 */ 77 struct gem_desc gcd_txdescs[GEM_NTXDESC]; 78 79 /* 80 * The receive descriptors. 81 */ 82 struct gem_desc gcd_rxdescs[GEM_NRXDESC]; 83 }; 84 85 #define GEM_CDOFF(x) offsetof(struct gem_control_data, x) 86 #define GEM_CDTXOFF(x) GEM_CDOFF(gcd_txdescs[(x)]) 87 #define GEM_CDRXOFF(x) GEM_CDOFF(gcd_rxdescs[(x)]) 88 89 /* 90 * Software state for receive jobs. 91 */ 92 struct gem_rxsoft { 93 struct mbuf *rxs_mbuf; /* head of our mbuf chain */ 94 bus_dmamap_t rxs_dmamap; /* our DMA map */ 95 }; 96 97 98 /* 99 * Table which describes the transmit threshold mode. We generally 100 * start at index 0. Whenever we get a transmit underrun, we increment 101 * our index, falling back if we encounter the NULL terminator. 102 */ 103 struct gem_txthresh_tab { 104 u_int32_t txth_opmode; /* OPMODE bits */ 105 const char *txth_name; /* name of mode */ 106 }; 107 108 /* 109 * Some misc. statics, useful for debugging. 110 */ 111 struct gem_stats { 112 u_long ts_tx_uf; /* transmit underflow errors */ 113 u_long ts_tx_to; /* transmit jabber timeouts */ 114 u_long ts_tx_ec; /* excessive collision count */ 115 u_long ts_tx_lc; /* late collision count */ 116 }; 117 118 /* 119 * Software state per device. 120 */ 121 struct gem_softc { 122 struct device sc_dev; /* generic device information */ 123 struct arpcom sc_arpcom; /* ethernet common data */ 124 struct mii_data sc_mii; /* MII media control */ 125 #define sc_media sc_mii.mii_media/* shorthand */ 126 struct timeout sc_tick_ch; /* tick callout */ 127 128 /* The following bus handles are to be provided by the bus front-end */ 129 bus_space_tag_t sc_bustag; /* bus tag */ 130 bus_dma_tag_t sc_dmatag; /* bus dma tag */ 131 bus_dmamap_t sc_dmamap; /* bus dma handle */ 132 bus_space_handle_t sc_h; /* bus space handle for all regs */ 133 #if 0 134 /* The following may be needed for SBus */ 135 bus_space_handle_t sc_seb; /* HME Global registers */ 136 bus_space_handle_t sc_erx; /* HME ERX registers */ 137 bus_space_handle_t sc_etx; /* HME ETX registers */ 138 bus_space_handle_t sc_mac; /* HME MAC registers */ 139 bus_space_handle_t sc_mif; /* HME MIF registers */ 140 #endif 141 int sc_burst; /* DVMA burst size in effect */ 142 int sc_phys[2]; /* MII instance -> PHY map */ 143 144 int sc_mif_config; /* Selected MII reg setting */ 145 146 int sc_pci; /* XXXXX -- PCI buses are LE. */ 147 u_int sc_variant; /* which GEM are we dealing with? */ 148 #define GEM_UNKNOWN 0 /* don't know */ 149 #define GEM_SUN_GEM 1 /* Sun GEM variant */ 150 #define GEM_APPLE_GMAC 2 /* Apple GMAC variant */ 151 152 u_int sc_flags; /* */ 153 #define GEM_GIGABIT 0x0001 /* has a gigabit PHY */ 154 155 156 void *sc_sdhook; /* shutdown hook */ 157 void *sc_powerhook; /* power management hook */ 158 159 struct gem_stats sc_stats; /* debugging stats */ 160 161 /* 162 * Ring buffer DMA stuff. 163 */ 164 bus_dma_segment_t sc_cdseg; /* control data memory */ 165 int sc_cdnseg; /* number of segments */ 166 bus_dmamap_t sc_cddmamap; /* control data DMA map */ 167 #define sc_cddma sc_cddmamap->dm_segs[0].ds_addr 168 169 /* 170 * Software state for transmit and receive descriptors. 171 */ 172 struct gem_sxd sc_txd[GEM_NTXDESC]; 173 u_int32_t sc_tx_cnt, sc_tx_prod, sc_tx_cons; 174 175 struct gem_rxsoft sc_rxsoft[GEM_NRXDESC]; 176 177 /* 178 * Control data structures. 179 */ 180 struct gem_control_data *sc_control_data; 181 #define sc_txdescs sc_control_data->gcd_txdescs 182 #define sc_rxdescs sc_control_data->gcd_rxdescs 183 184 int sc_txfree; /* number of free Tx descriptors */ 185 int sc_txnext; /* next ready Tx descriptor */ 186 187 u_int32_t sc_tdctl_ch; /* conditional desc chaining */ 188 u_int32_t sc_tdctl_er; /* conditional desc end-of-ring */ 189 190 u_int32_t sc_setup_fsls; /* FS|LS on setup descriptor */ 191 192 int sc_rxptr; /* next ready RX descriptor/descsoft */ 193 int sc_rxfifosize; 194 195 /* ========== */ 196 int sc_inited; 197 int sc_debug; 198 void *sc_sh; /* shutdownhook cookie */ 199 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; /* MAC address */ 200 201 /* Special hardware hooks */ 202 void (*sc_hwreset)(struct gem_softc *); 203 void (*sc_hwinit)(struct gem_softc *); 204 }; 205 206 #define GEM_DMA_READ(sc, v) (((sc)->sc_pci) ? letoh64(v) : betoh64(v)) 207 #define GEM_DMA_WRITE(sc, v) (((sc)->sc_pci) ? htole64(v) : htobe64(v)) 208 209 /* 210 * This macro returns the current media entry for *non-MII* media. 211 */ 212 #define GEM_CURRENT_MEDIA(sc) \ 213 (IFM_SUBTYPE((sc)->sc_mii.mii_media.ifm_cur->ifm_media) != IFM_AUTO ? \ 214 (sc)->sc_mii.mii_media.ifm_cur : (sc)->sc_nway_active) 215 216 /* 217 * This macro determines if a change to media-related OPMODE bits requires 218 * a chip reset. 219 */ 220 #define GEM_MEDIA_NEEDSRESET(sc, newbits) \ 221 (((sc)->sc_opmode & OPMODE_MEDIA_BITS) != \ 222 ((newbits) & OPMODE_MEDIA_BITS)) 223 224 #define GEM_CDTXADDR(sc, x) ((sc)->sc_cddma + GEM_CDTXOFF((x))) 225 #define GEM_CDRXADDR(sc, x) ((sc)->sc_cddma + GEM_CDRXOFF((x))) 226 227 #define GEM_CDSPADDR(sc) ((sc)->sc_cddma + GEM_CDSPOFF) 228 229 #define GEM_CDTXSYNC(sc, x, n, ops) \ 230 do { \ 231 int __x, __n; \ 232 \ 233 __x = (x); \ 234 __n = (n); \ 235 \ 236 /* If it will wrap around, sync to the end of the ring. */ \ 237 if ((__x + __n) > GEM_NTXDESC) { \ 238 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 239 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * \ 240 (GEM_NTXDESC - __x), (ops)); \ 241 __n -= (GEM_NTXDESC - __x); \ 242 __x = 0; \ 243 } \ 244 \ 245 /* Now sync whatever is left. */ \ 246 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 247 GEM_CDTXOFF(__x), sizeof(struct gem_desc) * __n, (ops)); \ 248 } while (0) 249 250 #define GEM_CDRXSYNC(sc, x, ops) \ 251 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 252 GEM_CDRXOFF((x)), sizeof(struct gem_desc), (ops)) 253 254 #define GEM_CDSPSYNC(sc, ops) \ 255 bus_dmamap_sync((sc)->sc_dmatag, (sc)->sc_cddmamap, \ 256 GEM_CDSPOFF, GEM_SETUP_PACKET_LEN, (ops)) 257 258 #define GEM_INIT_RXDESC(sc, x) \ 259 do { \ 260 struct gem_rxsoft *__rxs = &sc->sc_rxsoft[(x)]; \ 261 struct gem_desc *__rxd = &sc->sc_rxdescs[(x)]; \ 262 struct mbuf *__m = __rxs->rxs_mbuf; \ 263 \ 264 __m->m_data = __m->m_ext.ext_buf; \ 265 __rxd->gd_addr = \ 266 GEM_DMA_WRITE((sc), __rxs->rxs_dmamap->dm_segs[0].ds_addr); \ 267 __rxd->gd_flags = \ 268 GEM_DMA_WRITE((sc), \ 269 (((__m->m_ext.ext_size)<<GEM_RD_BUFSHIFT) \ 270 & GEM_RD_BUFSIZE) | GEM_RD_OWN); \ 271 GEM_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \ 272 } while (0) 273 274 #ifdef _KERNEL 275 void gem_attach(struct gem_softc *, const u_int8_t *); 276 int gem_activate(struct device *, enum devact); 277 int gem_detach(struct gem_softc *); 278 int gem_intr(void *); 279 int gem_read_srom(struct gem_softc *); 280 int gem_srom_crcok(const u_int8_t *); 281 int gem_isv_srom(const u_int8_t *); 282 int gem_isv_srom_enaddr(struct gem_softc *, u_int8_t *); 283 int gem_parse_old_srom(struct gem_softc *, u_int8_t *); 284 285 int gem_mediachange(struct ifnet *); 286 void gem_mediastatus(struct ifnet *, struct ifmediareq *); 287 288 void gem_config(struct gem_softc *); 289 void gem_reset(struct gem_softc *); 290 int gem_intr(void *); 291 #endif /* _KERNEL */ 292 293 294 #endif 295