1 /* $OpenBSD: gem.c,v 1.37 2004/02/02 08:40:48 brad Exp $ */
2 /* $NetBSD: gem.c,v 1.1 2001/09/16 00:11:43 eeh Exp $ */
3
4 /*
5 *
6 * Copyright (C) 2001 Eduardo Horvath.
7 * All rights reserved.
8 *
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 */
32
33 /*
34 * Driver for Sun GEM ethernet controllers.
35 */
36
37 #include "bpfilter.h"
38 #include "vlan.h"
39
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/timeout.h>
43 #include <sys/mbuf.h>
44 #include <sys/syslog.h>
45 #include <sys/malloc.h>
46 #include <sys/kernel.h>
47 #include <sys/socket.h>
48 #include <sys/ioctl.h>
49 #include <sys/errno.h>
50 #include <sys/device.h>
51
52 #include <machine/endian.h>
53
54 #include <net/if.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57
58 #ifdef INET
59 #include <netinet/in.h>
60 #include <netinet/if_ether.h>
61 #endif
62
63 #if NBPFILTER > 0
64 #include <net/bpf.h>
65 #endif
66
67 #if NVLAN > 0
68 #include <net/if_vlan_var.h>
69 #endif
70
71 #include <machine/bus.h>
72 #include <machine/intr.h>
73
74 #include <dev/mii/mii.h>
75 #include <dev/mii/miivar.h>
76 #include <dev/mii/mii_bitbang.h>
77
78 #include <dev/ic/gemreg.h>
79 #include <dev/ic/gemvar.h>
80
81 #define TRIES 10000
82
83 struct cfdriver gem_cd = {
84 NULL, "gem", DV_IFNET
85 };
86
87 void gem_start(struct ifnet *);
88 void gem_stop(struct ifnet *, int);
89 int gem_ioctl(struct ifnet *, u_long, caddr_t);
90 void gem_tick(void *);
91 void gem_watchdog(struct ifnet *);
92 void gem_shutdown(void *);
93 int gem_init(struct ifnet *);
94 void gem_init_regs(struct gem_softc *sc);
95 static int gem_ringsize(int sz);
96 int gem_meminit(struct gem_softc *);
97 void gem_mifinit(struct gem_softc *);
98 void gem_reset(struct gem_softc *);
99 int gem_reset_rx(struct gem_softc *sc);
100 int gem_reset_tx(struct gem_softc *sc);
101 int gem_disable_rx(struct gem_softc *sc);
102 int gem_disable_tx(struct gem_softc *sc);
103 void gem_rxdrain(struct gem_softc *sc);
104 int gem_add_rxbuf(struct gem_softc *sc, int idx);
105 void gem_setladrf(struct gem_softc *);
106 int gem_encap(struct gem_softc *, struct mbuf *, u_int32_t *);
107
108 /* MII methods & callbacks */
109 static int gem_mii_readreg(struct device *, int, int);
110 static void gem_mii_writereg(struct device *, int, int, int);
111 static void gem_mii_statchg(struct device *);
112
113 int gem_mediachange(struct ifnet *);
114 void gem_mediastatus(struct ifnet *, struct ifmediareq *);
115
116 struct mbuf *gem_get(struct gem_softc *, int, int);
117 int gem_eint(struct gem_softc *, u_int);
118 int gem_rint(struct gem_softc *);
119 int gem_tint(struct gem_softc *, u_int32_t);
120
121 #ifdef GEM_DEBUG
122 #define DPRINTF(sc, x) if ((sc)->sc_arpcom.ac_if.if_flags & IFF_DEBUG) \
123 printf x
124 #else
125 #define DPRINTF(sc, x) /* nothing */
126 #endif
127
128
129 /*
130 * gem_config:
131 *
132 * Attach a Gem interface to the system.
133 */
134 void
gem_config(sc)135 gem_config(sc)
136 struct gem_softc *sc;
137 {
138 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
139 struct mii_data *mii = &sc->sc_mii;
140 struct mii_softc *child;
141 int i, error;
142 struct ifmedia_entry *ifm;
143
144 bcopy(sc->sc_enaddr, sc->sc_arpcom.ac_enaddr, ETHER_ADDR_LEN);
145
146 /* Make sure the chip is stopped. */
147 ifp->if_softc = sc;
148 gem_reset(sc);
149
150 /*
151 * Allocate the control data structures, and create and load the
152 * DMA map for it.
153 */
154 if ((error = bus_dmamem_alloc(sc->sc_dmatag,
155 sizeof(struct gem_control_data), PAGE_SIZE, 0, &sc->sc_cdseg,
156 1, &sc->sc_cdnseg, 0)) != 0) {
157 printf("%s: unable to allocate control data, error = %d\n",
158 sc->sc_dev.dv_xname, error);
159 goto fail_0;
160 }
161
162 /* XXX should map this in with correct endianness */
163 if ((error = bus_dmamem_map(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg,
164 sizeof(struct gem_control_data), (caddr_t *)&sc->sc_control_data,
165 BUS_DMA_COHERENT)) != 0) {
166 printf("%s: unable to map control data, error = %d\n",
167 sc->sc_dev.dv_xname, error);
168 goto fail_1;
169 }
170
171 if ((error = bus_dmamap_create(sc->sc_dmatag,
172 sizeof(struct gem_control_data), 1,
173 sizeof(struct gem_control_data), 0, 0, &sc->sc_cddmamap)) != 0) {
174 printf("%s: unable to create control data DMA map, "
175 "error = %d\n", sc->sc_dev.dv_xname, error);
176 goto fail_2;
177 }
178
179 if ((error = bus_dmamap_load(sc->sc_dmatag, sc->sc_cddmamap,
180 sc->sc_control_data, sizeof(struct gem_control_data), NULL,
181 0)) != 0) {
182 printf("%s: unable to load control data DMA map, error = %d\n",
183 sc->sc_dev.dv_xname, error);
184 goto fail_3;
185 }
186
187 /*
188 * Create the receive buffer DMA maps.
189 */
190 for (i = 0; i < GEM_NRXDESC; i++) {
191 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES, 1,
192 MCLBYTES, 0, 0, &sc->sc_rxsoft[i].rxs_dmamap)) != 0) {
193 printf("%s: unable to create rx DMA map %d, "
194 "error = %d\n", sc->sc_dev.dv_xname, i, error);
195 goto fail_5;
196 }
197 sc->sc_rxsoft[i].rxs_mbuf = NULL;
198 }
199 /*
200 * Create the transmit buffer DMA maps.
201 */
202 for (i = 0; i < GEM_NTXDESC; i++) {
203 if ((error = bus_dmamap_create(sc->sc_dmatag, MCLBYTES,
204 GEM_NTXSEGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
205 &sc->sc_txd[i].sd_map)) != 0) {
206 printf("%s: unable to create tx DMA map %d, "
207 "error = %d\n", sc->sc_dev.dv_xname, i, error);
208 goto fail_6;
209 }
210 sc->sc_txd[i].sd_mbuf = NULL;
211 }
212
213 /*
214 * From this point forward, the attachment cannot fail. A failure
215 * before this point releases all resources that may have been
216 * allocated.
217 */
218
219 /* Announce ourselves. */
220 printf("%s: address %s\n", sc->sc_dev.dv_xname,
221 ether_sprintf(sc->sc_enaddr));
222
223 /* Get RX FIFO size */
224 sc->sc_rxfifosize = 64 *
225 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
226
227 /* Initialize ifnet structure. */
228 strlcpy(ifp->if_xname, sc->sc_dev.dv_xname, sizeof ifp->if_xname);
229 ifp->if_softc = sc;
230 ifp->if_flags =
231 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST;
232 ifp->if_start = gem_start;
233 ifp->if_ioctl = gem_ioctl;
234 ifp->if_watchdog = gem_watchdog;
235 IFQ_SET_READY(&ifp->if_snd);
236
237 /* Initialize ifmedia structures and MII info */
238 mii->mii_ifp = ifp;
239 mii->mii_readreg = gem_mii_readreg;
240 mii->mii_writereg = gem_mii_writereg;
241 mii->mii_statchg = gem_mii_statchg;
242
243 ifmedia_init(&mii->mii_media, 0, gem_mediachange, gem_mediastatus);
244
245 gem_mifinit(sc);
246
247 mii_attach(&sc->sc_dev, mii, 0xffffffff,
248 MII_PHY_ANY, MII_OFFSET_ANY, 0);
249
250 child = LIST_FIRST(&mii->mii_phys);
251 if (child == NULL) {
252 /* No PHY attached */
253 ifmedia_add(&sc->sc_media, IFM_ETHER|IFM_MANUAL, 0, NULL);
254 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_MANUAL);
255 } else {
256 /*
257 * Walk along the list of attached MII devices and
258 * establish an `MII instance' to `phy number'
259 * mapping. We'll use this mapping in media change
260 * requests to determine which phy to use to program
261 * the MIF configuration register.
262 */
263 for (; child != NULL; child = LIST_NEXT(child, mii_list)) {
264 /*
265 * Note: we support just two PHYs: the built-in
266 * internal device and an external on the MII
267 * connector.
268 */
269 if (child->mii_phy > 1 || child->mii_inst > 1) {
270 printf("%s: cannot accommodate MII device %s"
271 " at phy %d, instance %d\n",
272 sc->sc_dev.dv_xname,
273 child->mii_dev.dv_xname,
274 child->mii_phy, child->mii_inst);
275 continue;
276 }
277
278 sc->sc_phys[child->mii_inst] = child->mii_phy;
279 }
280
281 /*
282 * Now select and activate the PHY we will use.
283 *
284 * The order of preference is External (MDI1),
285 * Internal (MDI0), Serial Link (no MII).
286 */
287 if (sc->sc_phys[1]) {
288 #ifdef DEBUG
289 printf("using external phy\n");
290 #endif
291 sc->sc_mif_config |= GEM_MIF_CONFIG_PHY_SEL;
292 } else {
293 #ifdef DEBUG
294 printf("using internal phy\n");
295 #endif
296 sc->sc_mif_config &= ~GEM_MIF_CONFIG_PHY_SEL;
297 }
298 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_MIF_CONFIG,
299 sc->sc_mif_config);
300
301 /*
302 * XXX - we can really do the following ONLY if the
303 * phy indeed has the auto negotiation capability!!
304 */
305 ifmedia_set(&sc->sc_media, IFM_ETHER|IFM_AUTO);
306 }
307
308 /*
309 * If we support GigE media, we support jumbo frames too.
310 * Unless we are Apple.
311 */
312 TAILQ_FOREACH(ifm, &sc->sc_media.ifm_list, ifm_list) {
313 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T ||
314 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_SX ||
315 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_LX ||
316 IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_CX) {
317 #if 0
318 if (sc->sc_variant != GEM_APPLE_GMAC)
319 sc->sc_ethercom.ec_capabilities
320 |= ETHERCAP_JUMBO_MTU;
321 #endif
322
323 sc->sc_flags |= GEM_GIGABIT;
324 break;
325 }
326 }
327
328 /* Attach the interface. */
329 if_attach(ifp);
330 ether_ifattach(ifp);
331
332 sc->sc_sh = shutdownhook_establish(gem_shutdown, sc);
333 if (sc->sc_sh == NULL)
334 panic("gem_config: can't establish shutdownhook");
335
336 timeout_set(&sc->sc_tick_ch, gem_tick, sc);
337 return;
338
339 /*
340 * Free any resources we've allocated during the failed attach
341 * attempt. Do this in reverse order and fall through.
342 */
343 fail_6:
344 for (i = 0; i < GEM_NTXDESC; i++) {
345 if (sc->sc_txd[i].sd_map != NULL)
346 bus_dmamap_destroy(sc->sc_dmatag,
347 sc->sc_txd[i].sd_map);
348 }
349 fail_5:
350 for (i = 0; i < GEM_NRXDESC; i++) {
351 if (sc->sc_rxsoft[i].rxs_dmamap != NULL)
352 bus_dmamap_destroy(sc->sc_dmatag,
353 sc->sc_rxsoft[i].rxs_dmamap);
354 }
355 bus_dmamap_unload(sc->sc_dmatag, sc->sc_cddmamap);
356 fail_3:
357 bus_dmamap_destroy(sc->sc_dmatag, sc->sc_cddmamap);
358 fail_2:
359 bus_dmamem_unmap(sc->sc_dmatag, (caddr_t)sc->sc_control_data,
360 sizeof(struct gem_control_data));
361 fail_1:
362 bus_dmamem_free(sc->sc_dmatag, &sc->sc_cdseg, sc->sc_cdnseg);
363 fail_0:
364 return;
365 }
366
367
368 void
gem_tick(arg)369 gem_tick(arg)
370 void *arg;
371 {
372 struct gem_softc *sc = arg;
373 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
374 bus_space_tag_t t = sc->sc_bustag;
375 bus_space_handle_t mac = sc->sc_h;
376 int s;
377
378 /* unload collisions counters */
379 ifp->if_collisions +=
380 bus_space_read_4(t, mac, GEM_MAC_NORM_COLL_CNT) +
381 bus_space_read_4(t, mac, GEM_MAC_FIRST_COLL_CNT) +
382 bus_space_read_4(t, mac, GEM_MAC_EXCESS_COLL_CNT) +
383 bus_space_read_4(t, mac, GEM_MAC_LATE_COLL_CNT);
384
385 /* clear the hardware counters */
386 bus_space_write_4(t, mac, GEM_MAC_NORM_COLL_CNT, 0);
387 bus_space_write_4(t, mac, GEM_MAC_FIRST_COLL_CNT, 0);
388 bus_space_write_4(t, mac, GEM_MAC_EXCESS_COLL_CNT, 0);
389 bus_space_write_4(t, mac, GEM_MAC_LATE_COLL_CNT, 0);
390
391 s = splimp();
392 mii_tick(&sc->sc_mii);
393 splx(s);
394
395 timeout_add(&sc->sc_tick_ch, hz);
396 }
397
398 void
gem_reset(sc)399 gem_reset(sc)
400 struct gem_softc *sc;
401 {
402 bus_space_tag_t t = sc->sc_bustag;
403 bus_space_handle_t h = sc->sc_h;
404 int i;
405 int s;
406
407 s = splimp();
408 DPRINTF(sc, ("%s: gem_reset\n", sc->sc_dev.dv_xname));
409 gem_reset_rx(sc);
410 gem_reset_tx(sc);
411
412 /* Do a full reset */
413 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX|GEM_RESET_TX);
414 for (i=TRIES; i--; delay(100))
415 if ((bus_space_read_4(t, h, GEM_RESET) &
416 (GEM_RESET_RX|GEM_RESET_TX)) == 0)
417 break;
418 if ((bus_space_read_4(t, h, GEM_RESET) &
419 (GEM_RESET_RX|GEM_RESET_TX)) != 0) {
420 printf("%s: cannot reset device\n",
421 sc->sc_dev.dv_xname);
422 }
423 splx(s);
424 }
425
426
427 /*
428 * gem_rxdrain:
429 *
430 * Drain the receive queue.
431 */
432 void
gem_rxdrain(struct gem_softc * sc)433 gem_rxdrain(struct gem_softc *sc)
434 {
435 struct gem_rxsoft *rxs;
436 int i;
437
438 for (i = 0; i < GEM_NRXDESC; i++) {
439 rxs = &sc->sc_rxsoft[i];
440 if (rxs->rxs_mbuf != NULL) {
441 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
442 m_freem(rxs->rxs_mbuf);
443 rxs->rxs_mbuf = NULL;
444 }
445 }
446 }
447
448 /*
449 * Reset the whole thing.
450 */
451 void
gem_stop(struct ifnet * ifp,int disable)452 gem_stop(struct ifnet *ifp, int disable)
453 {
454 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
455 struct gem_sxd *sd;
456 u_int32_t i;
457
458 DPRINTF(sc, ("%s: gem_stop\n", sc->sc_dev.dv_xname));
459
460 timeout_del(&sc->sc_tick_ch);
461 mii_down(&sc->sc_mii);
462
463 gem_reset_rx(sc);
464 gem_reset_tx(sc);
465
466 /*
467 * Release any queued transmit buffers.
468 */
469 for (i = 0; i < GEM_NTXDESC; i++) {
470 sd = &sc->sc_txd[i];
471 if (sd->sd_mbuf != NULL) {
472 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
473 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
474 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
475 m_freem(sd->sd_mbuf);
476 sd->sd_mbuf = NULL;
477 }
478 }
479 sc->sc_tx_cnt = sc->sc_tx_prod = sc->sc_tx_cons = 0;
480
481 if (disable) {
482 gem_rxdrain(sc);
483 }
484
485 /*
486 * Mark the interface down and cancel the watchdog timer.
487 */
488 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
489 ifp->if_timer = 0;
490 }
491
492
493 /*
494 * Reset the receiver
495 */
496 int
gem_reset_rx(struct gem_softc * sc)497 gem_reset_rx(struct gem_softc *sc)
498 {
499 bus_space_tag_t t = sc->sc_bustag;
500 bus_space_handle_t h = sc->sc_h;
501 int i;
502
503 /*
504 * Resetting while DMA is in progress can cause a bus hang, so we
505 * disable DMA first.
506 */
507 gem_disable_rx(sc);
508 bus_space_write_4(t, h, GEM_RX_CONFIG, 0);
509 /* Wait till it finishes */
510 for (i = TRIES; i--; delay(100))
511 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) == 0)
512 break;
513 if ((bus_space_read_4(t, h, GEM_RX_CONFIG) & 1) != 0)
514 printf("%s: cannot disable rx dma\n",
515 sc->sc_dev.dv_xname);
516
517 /* Wait 5ms extra. */
518 delay(5000);
519
520 /* Finally, reset the ERX */
521 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_RX);
522 /* Wait till it finishes */
523 for (i = TRIES; i--; delay(100))
524 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) == 0)
525 break;
526 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_RX) != 0) {
527 printf("%s: cannot reset receiver\n",
528 sc->sc_dev.dv_xname);
529 return (1);
530 }
531 return (0);
532 }
533
534
535 /*
536 * Reset the transmitter
537 */
538 int
gem_reset_tx(struct gem_softc * sc)539 gem_reset_tx(struct gem_softc *sc)
540 {
541 bus_space_tag_t t = sc->sc_bustag;
542 bus_space_handle_t h = sc->sc_h;
543 int i;
544
545 /*
546 * Resetting while DMA is in progress can cause a bus hang, so we
547 * disable DMA first.
548 */
549 gem_disable_tx(sc);
550 bus_space_write_4(t, h, GEM_TX_CONFIG, 0);
551 /* Wait till it finishes */
552 for (i = TRIES; i--; delay(100))
553 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) == 0)
554 break;
555 if ((bus_space_read_4(t, h, GEM_TX_CONFIG) & 1) != 0)
556 printf("%s: cannot disable tx dma\n",
557 sc->sc_dev.dv_xname);
558
559 /* Wait 5ms extra. */
560 delay(5000);
561
562 /* Finally, reset the ETX */
563 bus_space_write_4(t, h, GEM_RESET, GEM_RESET_TX);
564 /* Wait till it finishes */
565 for (i = TRIES; i--; delay(100))
566 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) == 0)
567 break;
568 if ((bus_space_read_4(t, h, GEM_RESET) & GEM_RESET_TX) != 0) {
569 printf("%s: cannot reset transmitter\n",
570 sc->sc_dev.dv_xname);
571 return (1);
572 }
573 return (0);
574 }
575
576 /*
577 * disable receiver.
578 */
579 int
gem_disable_rx(struct gem_softc * sc)580 gem_disable_rx(struct gem_softc *sc)
581 {
582 bus_space_tag_t t = sc->sc_bustag;
583 bus_space_handle_t h = sc->sc_h;
584 int i;
585 u_int32_t cfg;
586
587 /* Flip the enable bit */
588 cfg = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
589 cfg &= ~GEM_MAC_RX_ENABLE;
590 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, cfg);
591
592 /* Wait for it to finish */
593 for (i = TRIES; i--; delay(100))
594 if ((bus_space_read_4(t, h, GEM_MAC_RX_CONFIG) &
595 GEM_MAC_RX_ENABLE) == 0)
596 return (0);
597 return (1);
598 }
599
600 /*
601 * disable transmitter.
602 */
603 int
gem_disable_tx(struct gem_softc * sc)604 gem_disable_tx(struct gem_softc *sc)
605 {
606 bus_space_tag_t t = sc->sc_bustag;
607 bus_space_handle_t h = sc->sc_h;
608 int i;
609 u_int32_t cfg;
610
611 /* Flip the enable bit */
612 cfg = bus_space_read_4(t, h, GEM_MAC_TX_CONFIG);
613 cfg &= ~GEM_MAC_TX_ENABLE;
614 bus_space_write_4(t, h, GEM_MAC_TX_CONFIG, cfg);
615
616 /* Wait for it to finish */
617 for (i = TRIES; i--; delay(100))
618 if ((bus_space_read_4(t, h, GEM_MAC_TX_CONFIG) &
619 GEM_MAC_TX_ENABLE) == 0)
620 return (0);
621 return (1);
622 }
623
624 /*
625 * Initialize interface.
626 */
627 int
gem_meminit(struct gem_softc * sc)628 gem_meminit(struct gem_softc *sc)
629 {
630 struct gem_rxsoft *rxs;
631 int i, error;
632
633 /*
634 * Initialize the transmit descriptor ring.
635 */
636 for (i = 0; i < GEM_NTXDESC; i++) {
637 sc->sc_txdescs[i].gd_flags = 0;
638 sc->sc_txdescs[i].gd_addr = 0;
639 }
640 GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
641 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
642
643 /*
644 * Initialize the receive descriptor and receive job
645 * descriptor rings.
646 */
647 for (i = 0; i < GEM_NRXDESC; i++) {
648 rxs = &sc->sc_rxsoft[i];
649 if (rxs->rxs_mbuf == NULL) {
650 if ((error = gem_add_rxbuf(sc, i)) != 0) {
651 printf("%s: unable to allocate or map rx "
652 "buffer %d, error = %d\n",
653 sc->sc_dev.dv_xname, i, error);
654 /*
655 * XXX Should attempt to run with fewer receive
656 * XXX buffers instead of just failing.
657 */
658 gem_rxdrain(sc);
659 return (1);
660 }
661 } else
662 GEM_INIT_RXDESC(sc, i);
663 }
664 sc->sc_rxptr = 0;
665
666 return (0);
667 }
668
669 static int
gem_ringsize(int sz)670 gem_ringsize(int sz)
671 {
672 switch (sz) {
673 case 32:
674 return GEM_RING_SZ_32;
675 case 64:
676 return GEM_RING_SZ_64;
677 case 128:
678 return GEM_RING_SZ_128;
679 case 256:
680 return GEM_RING_SZ_256;
681 case 512:
682 return GEM_RING_SZ_512;
683 case 1024:
684 return GEM_RING_SZ_1024;
685 case 2048:
686 return GEM_RING_SZ_2048;
687 case 4096:
688 return GEM_RING_SZ_4096;
689 case 8192:
690 return GEM_RING_SZ_8192;
691 default:
692 printf("gem: invalid Receive Descriptor ring size %d\n", sz);
693 return GEM_RING_SZ_32;
694 }
695 }
696
697 /*
698 * Initialization of interface; set up initialization block
699 * and transmit/receive descriptor rings.
700 */
701 int
gem_init(struct ifnet * ifp)702 gem_init(struct ifnet *ifp)
703 {
704
705 struct gem_softc *sc = (struct gem_softc *)ifp->if_softc;
706 bus_space_tag_t t = sc->sc_bustag;
707 bus_space_handle_t h = sc->sc_h;
708 int s;
709 u_int max_frame_size;
710 u_int32_t v;
711
712 s = splimp();
713
714 DPRINTF(sc, ("%s: gem_init: calling stop\n", sc->sc_dev.dv_xname));
715 /*
716 * Initialization sequence. The numbered steps below correspond
717 * to the sequence outlined in section 6.3.5.1 in the Ethernet
718 * Channel Engine manual (part of the PCIO manual).
719 * See also the STP2002-STQ document from Sun Microsystems.
720 */
721
722 /* step 1 & 2. Reset the Ethernet Channel */
723 gem_stop(ifp, 0);
724 gem_reset(sc);
725 DPRINTF(sc, ("%s: gem_init: restarting\n", sc->sc_dev.dv_xname));
726
727 /* Re-initialize the MIF */
728 gem_mifinit(sc);
729
730 /* Call MI reset function if any */
731 if (sc->sc_hwreset)
732 (*sc->sc_hwreset)(sc);
733
734 /* step 3. Setup data structures in host memory */
735 gem_meminit(sc);
736
737 /* step 4. TX MAC registers & counters */
738 gem_init_regs(sc);
739 max_frame_size = max(ifp->if_mtu, ETHERMTU);
740 max_frame_size += ETHER_HDR_LEN + ETHER_CRC_LEN;
741 #if 0
742 if (sc->sc_ethercom.ec_capenable & ETHERCAP_VLAN_MTU)
743 max_frame_size += ETHER_VLAN_ENCAP_LEN;
744 #endif
745 v = (max_frame_size) | (0x2000 << 16) /* Burst size */;
746 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v);
747
748 /* step 5. RX MAC registers & counters */
749 gem_setladrf(sc);
750
751 /* step 6 & 7. Program Descriptor Ring Base Addresses */
752 bus_space_write_4(t, h, GEM_TX_RING_PTR_HI,
753 (((uint64_t)GEM_CDTXADDR(sc,0)) >> 32));
754 bus_space_write_4(t, h, GEM_TX_RING_PTR_LO, GEM_CDTXADDR(sc, 0));
755
756 bus_space_write_4(t, h, GEM_RX_RING_PTR_HI,
757 (((uint64_t)GEM_CDRXADDR(sc,0)) >> 32));
758 bus_space_write_4(t, h, GEM_RX_RING_PTR_LO, GEM_CDRXADDR(sc, 0));
759
760 /* step 8. Global Configuration & Interrupt Mask */
761 bus_space_write_4(t, h, GEM_INTMASK,
762 ~(GEM_INTR_TX_INTME|
763 GEM_INTR_TX_EMPTY|
764 GEM_INTR_RX_DONE|GEM_INTR_RX_NOBUF|
765 GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
766 GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
767 GEM_INTR_BERR));
768 bus_space_write_4(t, h, GEM_MAC_RX_MASK,
769 GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
770 bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
771 bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
772
773 /* step 9. ETX Configuration: use mostly default values */
774
775 /* Enable DMA */
776 v = gem_ringsize(GEM_NTXDESC /*XXX*/);
777 bus_space_write_4(t, h, GEM_TX_CONFIG,
778 v|GEM_TX_CONFIG_TXDMA_EN|
779 ((0x400<<10)&GEM_TX_CONFIG_TXFIFO_TH));
780 bus_space_write_4(t, h, GEM_TX_KICK, 0);
781
782 /* step 10. ERX Configuration */
783
784 /* Encode Receive Descriptor ring size: four possible values */
785 v = gem_ringsize(GEM_NRXDESC /*XXX*/);
786
787 /* Enable DMA */
788 bus_space_write_4(t, h, GEM_RX_CONFIG,
789 v|(GEM_THRSH_1024<<GEM_RX_CONFIG_FIFO_THRS_SHIFT)|
790 (2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
791 (0<<GEM_RX_CONFIG_CXM_START_SHFT));
792 /*
793 * The following value is for an OFF Threshold of about 3/4 full
794 * and an ON Threshold of 1/4 full.
795 */
796 bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
797 (3 * sc->sc_rxfifosize / 256) |
798 ( (sc->sc_rxfifosize / 256) << 12));
799 bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
800
801 /* step 11. Configure Media */
802 mii_mediachg(&sc->sc_mii);
803
804 /* step 12. RX_MAC Configuration Register */
805 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
806 v |= GEM_MAC_RX_ENABLE;
807 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
808
809 /* step 14. Issue Transmit Pending command */
810
811 /* Call MI initialization function if any */
812 if (sc->sc_hwinit)
813 (*sc->sc_hwinit)(sc);
814
815
816 /* step 15. Give the receiver a swift kick */
817 bus_space_write_4(t, h, GEM_RX_KICK, GEM_NRXDESC-4);
818
819 /* Start the one second timer. */
820 timeout_add(&sc->sc_tick_ch, hz);
821
822 ifp->if_flags |= IFF_RUNNING;
823 ifp->if_flags &= ~IFF_OACTIVE;
824 ifp->if_timer = 0;
825 splx(s);
826
827 return (0);
828 }
829
830 void
gem_init_regs(struct gem_softc * sc)831 gem_init_regs(struct gem_softc *sc)
832 {
833 bus_space_tag_t t = sc->sc_bustag;
834 bus_space_handle_t h = sc->sc_h;
835 u_int32_t v;
836
837 /* These regs are not cleared on reset */
838 sc->sc_inited = 0;
839 if (!sc->sc_inited) {
840
841 /* Wooo. Magic values. */
842 bus_space_write_4(t, h, GEM_MAC_IPG0, 0);
843 bus_space_write_4(t, h, GEM_MAC_IPG1, 8);
844 bus_space_write_4(t, h, GEM_MAC_IPG2, 4);
845
846 bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
847 /* Max frame and max burst size */
848 v = ETHER_MAX_LEN | (0x2000 << 16) /* Burst size */;
849 bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME, v);
850
851 bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
852 bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
853 bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
854 /* Dunno.... */
855 bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
856 bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
857 ((sc->sc_enaddr[5]<<8)|sc->sc_enaddr[4])&0x3ff);
858
859 /* Secondary MAC addr set to 0:0:0:0:0:0 */
860 bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
861 bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
862 bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
863 /* MAC control addr set to 0:1:c2:0:1:80 */
864 bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
865 bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
866 bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
867
868 /* MAC filter addr set to 0:0:0:0:0:0 */
869 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER0, 0);
870 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER1, 0);
871 bus_space_write_4(t, h, GEM_MAC_ADDR_FILTER2, 0);
872
873 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK1_2, 0);
874 bus_space_write_4(t, h, GEM_MAC_ADR_FLT_MASK0, 0);
875
876 sc->sc_inited = 1;
877 }
878
879 /* Counters need to be zeroed */
880 bus_space_write_4(t, h, GEM_MAC_NORM_COLL_CNT, 0);
881 bus_space_write_4(t, h, GEM_MAC_FIRST_COLL_CNT, 0);
882 bus_space_write_4(t, h, GEM_MAC_EXCESS_COLL_CNT, 0);
883 bus_space_write_4(t, h, GEM_MAC_LATE_COLL_CNT, 0);
884 bus_space_write_4(t, h, GEM_MAC_DEFER_TMR_CNT, 0);
885 bus_space_write_4(t, h, GEM_MAC_PEAK_ATTEMPTS, 0);
886 bus_space_write_4(t, h, GEM_MAC_RX_FRAME_COUNT, 0);
887 bus_space_write_4(t, h, GEM_MAC_RX_LEN_ERR_CNT, 0);
888 bus_space_write_4(t, h, GEM_MAC_RX_ALIGN_ERR, 0);
889 bus_space_write_4(t, h, GEM_MAC_RX_CRC_ERR_CNT, 0);
890 bus_space_write_4(t, h, GEM_MAC_RX_CODE_VIOL, 0);
891
892 /* Un-pause stuff */
893 bus_space_write_4(t, h, GEM_MAC_SEND_PAUSE_CMD, 0);
894
895 /*
896 * Set the station address.
897 */
898 bus_space_write_4(t, h, GEM_MAC_ADDR0,
899 (sc->sc_enaddr[4]<<8) | sc->sc_enaddr[5]);
900 bus_space_write_4(t, h, GEM_MAC_ADDR1,
901 (sc->sc_enaddr[2]<<8) | sc->sc_enaddr[3]);
902 bus_space_write_4(t, h, GEM_MAC_ADDR2,
903 (sc->sc_enaddr[0]<<8) | sc->sc_enaddr[1]);
904
905
906 /*
907 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
908 */
909 sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
910 v = GEM_MAC_XIF_TX_MII_ENA;
911 if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
912 v |= GEM_MAC_XIF_FDPLX_LED;
913 if (sc->sc_flags & GEM_GIGABIT)
914 v |= GEM_MAC_XIF_GMII_MODE;
915 }
916 bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
917 }
918
919 /*
920 * Receive interrupt.
921 */
922 int
gem_rint(sc)923 gem_rint(sc)
924 struct gem_softc *sc;
925 {
926 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
927 bus_space_tag_t t = sc->sc_bustag;
928 bus_space_handle_t h = sc->sc_h;
929 struct ether_header *eh;
930 struct gem_rxsoft *rxs;
931 struct mbuf *m;
932 u_int64_t rxstat;
933 int i, len;
934
935 for (i = sc->sc_rxptr;; i = GEM_NEXTRX(i)) {
936 rxs = &sc->sc_rxsoft[i];
937
938 GEM_CDRXSYNC(sc, i,
939 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
940
941 rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
942
943 if (rxstat & GEM_RD_OWN) {
944 /*
945 * We have processed all of the receive buffers.
946 */
947 break;
948 }
949
950 if (rxstat & GEM_RD_BAD_CRC) {
951 printf("%s: receive error: CRC error\n",
952 sc->sc_dev.dv_xname);
953 GEM_INIT_RXDESC(sc, i);
954 continue;
955 }
956
957 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
958 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
959 #ifdef GEM_DEBUG
960 if (ifp->if_flags & IFF_DEBUG) {
961 printf(" rxsoft %p descriptor %d: ", rxs, i);
962 printf("gd_flags: 0x%016llx\t", (long long)
963 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags));
964 printf("gd_addr: 0x%016llx\n", (long long)
965 GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_addr));
966 }
967 #endif
968
969 /*
970 * No errors; receive the packet. Note the Gem
971 * includes the CRC with every packet.
972 */
973 len = GEM_RD_BUFLEN(rxstat);
974
975 /*
976 * Allocate a new mbuf cluster. If that fails, we are
977 * out of memory, and must drop the packet and recycle
978 * the buffer that's already attached to this descriptor.
979 */
980 m = rxs->rxs_mbuf;
981 if (gem_add_rxbuf(sc, i) != 0) {
982 ifp->if_ierrors++;
983 GEM_INIT_RXDESC(sc, i);
984 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
985 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
986 continue;
987 }
988 m->m_data += 2; /* We're already off by two */
989
990 ifp->if_ipackets++;
991 eh = mtod(m, struct ether_header *);
992 m->m_pkthdr.rcvif = ifp;
993 m->m_pkthdr.len = m->m_len = len;
994
995 #if NBPFILTER > 0
996 /*
997 * Pass this up to any BPF listeners, but only
998 * pass it up the stack if its for us.
999 */
1000 if (ifp->if_bpf)
1001 bpf_mtap(ifp->if_bpf, m);
1002 #endif /* NPBFILTER > 0 */
1003
1004 /* Pass it on. */
1005 ether_input_mbuf(ifp, m);
1006 }
1007
1008 /* Update the receive pointer. */
1009 sc->sc_rxptr = i;
1010 bus_space_write_4(t, h, GEM_RX_KICK, i);
1011
1012 DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n",
1013 sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
1014
1015 return (1);
1016 }
1017
1018
1019 /*
1020 * gem_add_rxbuf:
1021 *
1022 * Add a receive buffer to the indicated descriptor.
1023 */
1024 int
gem_add_rxbuf(struct gem_softc * sc,int idx)1025 gem_add_rxbuf(struct gem_softc *sc, int idx)
1026 {
1027 struct gem_rxsoft *rxs = &sc->sc_rxsoft[idx];
1028 struct mbuf *m;
1029 int error;
1030
1031 MGETHDR(m, M_DONTWAIT, MT_DATA);
1032 if (m == NULL)
1033 return (ENOBUFS);
1034
1035 MCLGET(m, M_DONTWAIT);
1036 if ((m->m_flags & M_EXT) == 0) {
1037 m_freem(m);
1038 return (ENOBUFS);
1039 }
1040
1041 #ifdef GEM_DEBUG
1042 /* bzero the packet to check dma */
1043 memset(m->m_ext.ext_buf, 0, m->m_ext.ext_size);
1044 #endif
1045
1046 if (rxs->rxs_mbuf != NULL)
1047 bus_dmamap_unload(sc->sc_dmatag, rxs->rxs_dmamap);
1048
1049 rxs->rxs_mbuf = m;
1050
1051 error = bus_dmamap_load(sc->sc_dmatag, rxs->rxs_dmamap,
1052 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
1053 BUS_DMA_READ|BUS_DMA_NOWAIT);
1054 if (error) {
1055 printf("%s: can't load rx DMA map %d, error = %d\n",
1056 sc->sc_dev.dv_xname, idx, error);
1057 panic("gem_add_rxbuf"); /* XXX */
1058 }
1059
1060 bus_dmamap_sync(sc->sc_dmatag, rxs->rxs_dmamap, 0,
1061 rxs->rxs_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1062
1063 GEM_INIT_RXDESC(sc, idx);
1064
1065 return (0);
1066 }
1067
1068
1069 int
gem_eint(sc,status)1070 gem_eint(sc, status)
1071 struct gem_softc *sc;
1072 u_int status;
1073 {
1074 if ((status & GEM_INTR_MIF) != 0) {
1075 printf("%s: link status changed\n", sc->sc_dev.dv_xname);
1076 return (1);
1077 }
1078
1079 printf("%s: status=%b\n", sc->sc_dev.dv_xname, status, GEM_INTR_BITS);
1080 return (1);
1081 }
1082
1083
1084 int
gem_intr(v)1085 gem_intr(v)
1086 void *v;
1087 {
1088 struct gem_softc *sc = (struct gem_softc *)v;
1089 bus_space_tag_t t = sc->sc_bustag;
1090 bus_space_handle_t seb = sc->sc_h;
1091 u_int32_t status;
1092 int r = 0;
1093
1094 status = bus_space_read_4(t, seb, GEM_STATUS);
1095 DPRINTF(sc, ("%s: gem_intr: cplt %xstatus %b\n",
1096 sc->sc_dev.dv_xname, (status>>19), status, GEM_INTR_BITS));
1097
1098 if ((status & (GEM_INTR_RX_TAG_ERR | GEM_INTR_BERR)) != 0)
1099 r |= gem_eint(sc, status);
1100
1101 if ((status & (GEM_INTR_TX_EMPTY | GEM_INTR_TX_INTME)) != 0)
1102 r |= gem_tint(sc, status);
1103
1104 if ((status & (GEM_INTR_RX_DONE | GEM_INTR_RX_NOBUF)) != 0)
1105 r |= gem_rint(sc);
1106
1107 /* We should eventually do more than just print out error stats. */
1108 if (status & GEM_INTR_TX_MAC) {
1109 int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
1110 if (txstat & ~GEM_MAC_TX_XMIT_DONE)
1111 printf("%s: MAC tx fault, status %x\n",
1112 sc->sc_dev.dv_xname, txstat);
1113 }
1114 if (status & GEM_INTR_RX_MAC) {
1115 int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
1116
1117 rxstat &= ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT);
1118 if (rxstat & GEM_MAC_RX_OVERFLOW) {
1119 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1120
1121 gem_init(ifp);
1122 ifp->if_ierrors++;
1123 } else {
1124 /*
1125 * Leave this in here until I figure out what to do
1126 * about other errors.
1127 */
1128 printf("%s: MAC rx fault, status %x\n",
1129 sc->sc_dev.dv_xname, rxstat);
1130 }
1131 }
1132 return (r);
1133 }
1134
1135
1136 void
gem_watchdog(ifp)1137 gem_watchdog(ifp)
1138 struct ifnet *ifp;
1139 {
1140 struct gem_softc *sc = ifp->if_softc;
1141
1142 DPRINTF(sc, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
1143 "GEM_MAC_RX_CONFIG %x\n",
1144 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_CONFIG),
1145 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_STATUS),
1146 bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_MAC_RX_CONFIG)));
1147
1148 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname);
1149 ++ifp->if_oerrors;
1150
1151 /* Try to get more packets going. */
1152 gem_init(ifp);
1153 }
1154
1155 /*
1156 * Initialize the MII Management Interface
1157 */
1158 void
gem_mifinit(sc)1159 gem_mifinit(sc)
1160 struct gem_softc *sc;
1161 {
1162 bus_space_tag_t t = sc->sc_bustag;
1163 bus_space_handle_t mif = sc->sc_h;
1164
1165 /* Configure the MIF in frame mode */
1166 sc->sc_mif_config = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1167 sc->sc_mif_config &= ~GEM_MIF_CONFIG_BB_ENA;
1168 bus_space_write_4(t, mif, GEM_MIF_CONFIG, sc->sc_mif_config);
1169 }
1170
1171 /*
1172 * MII interface
1173 *
1174 * The GEM MII interface supports at least three different operating modes:
1175 *
1176 * Bitbang mode is implemented using data, clock and output enable registers.
1177 *
1178 * Frame mode is implemented by loading a complete frame into the frame
1179 * register and polling the valid bit for completion.
1180 *
1181 * Polling mode uses the frame register but completion is indicated by
1182 * an interrupt.
1183 *
1184 */
1185 static int
gem_mii_readreg(self,phy,reg)1186 gem_mii_readreg(self, phy, reg)
1187 struct device *self;
1188 int phy, reg;
1189 {
1190 struct gem_softc *sc = (void *)self;
1191 bus_space_tag_t t = sc->sc_bustag;
1192 bus_space_handle_t mif = sc->sc_h;
1193 int n;
1194 u_int32_t v;
1195
1196 #ifdef GEM_DEBUG
1197 if (sc->sc_debug)
1198 printf("gem_mii_readreg: phy %d reg %d\n", phy, reg);
1199 #endif
1200
1201 /* Construct the frame command */
1202 v = (reg << GEM_MIF_REG_SHIFT) | (phy << GEM_MIF_PHY_SHIFT) |
1203 GEM_MIF_FRAME_READ;
1204
1205 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1206 for (n = 0; n < 100; n++) {
1207 DELAY(1);
1208 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1209 if (v & GEM_MIF_FRAME_TA0)
1210 return (v & GEM_MIF_FRAME_DATA);
1211 }
1212
1213 printf("%s: mii_read timeout\n", sc->sc_dev.dv_xname);
1214 return (0);
1215 }
1216
1217 static void
gem_mii_writereg(self,phy,reg,val)1218 gem_mii_writereg(self, phy, reg, val)
1219 struct device *self;
1220 int phy, reg, val;
1221 {
1222 struct gem_softc *sc = (void *)self;
1223 bus_space_tag_t t = sc->sc_bustag;
1224 bus_space_handle_t mif = sc->sc_h;
1225 int n;
1226 u_int32_t v;
1227
1228 #ifdef GEM_DEBUG
1229 if (sc->sc_debug)
1230 printf("gem_mii_writereg: phy %d reg %d val %x\n",
1231 phy, reg, val);
1232 #endif
1233
1234 #if 0
1235 /* Select the desired PHY in the MIF configuration register */
1236 v = bus_space_read_4(t, mif, GEM_MIF_CONFIG);
1237 /* Clear PHY select bit */
1238 v &= ~GEM_MIF_CONFIG_PHY_SEL;
1239 if (phy == GEM_PHYAD_EXTERNAL)
1240 /* Set PHY select bit to get at external device */
1241 v |= GEM_MIF_CONFIG_PHY_SEL;
1242 bus_space_write_4(t, mif, GEM_MIF_CONFIG, v);
1243 #endif
1244 /* Construct the frame command */
1245 v = GEM_MIF_FRAME_WRITE |
1246 (phy << GEM_MIF_PHY_SHIFT) |
1247 (reg << GEM_MIF_REG_SHIFT) |
1248 (val & GEM_MIF_FRAME_DATA);
1249
1250 bus_space_write_4(t, mif, GEM_MIF_FRAME, v);
1251 for (n = 0; n < 100; n++) {
1252 DELAY(1);
1253 v = bus_space_read_4(t, mif, GEM_MIF_FRAME);
1254 if (v & GEM_MIF_FRAME_TA0)
1255 return;
1256 }
1257
1258 printf("%s: mii_write timeout\n", sc->sc_dev.dv_xname);
1259 }
1260
1261 static void
gem_mii_statchg(dev)1262 gem_mii_statchg(dev)
1263 struct device *dev;
1264 {
1265 struct gem_softc *sc = (void *)dev;
1266 #ifdef GEM_DEBUG
1267 int instance = IFM_INST(sc->sc_mii.mii_media.ifm_cur->ifm_media);
1268 #endif
1269 bus_space_tag_t t = sc->sc_bustag;
1270 bus_space_handle_t mac = sc->sc_h;
1271 u_int32_t v;
1272
1273 #ifdef GEM_DEBUG
1274 if (sc->sc_debug)
1275 printf("gem_mii_statchg: status change: phy = %d\n",
1276 sc->sc_phys[instance]);
1277 #endif
1278
1279
1280 /* Set tx full duplex options */
1281 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, 0);
1282 delay(10000); /* reg must be cleared and delay before changing. */
1283 v = GEM_MAC_TX_ENA_IPG0|GEM_MAC_TX_NGU|GEM_MAC_TX_NGU_LIMIT|
1284 GEM_MAC_TX_ENABLE;
1285 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0) {
1286 v |= GEM_MAC_TX_IGN_CARRIER|GEM_MAC_TX_IGN_COLLIS;
1287 }
1288 bus_space_write_4(t, mac, GEM_MAC_TX_CONFIG, v);
1289
1290 /* XIF Configuration */
1291 /* We should really calculate all this rather than rely on defaults */
1292 v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG);
1293 v = GEM_MAC_XIF_LINK_LED;
1294 v |= GEM_MAC_XIF_TX_MII_ENA;
1295 /* If an external transceiver is connected, enable its MII drivers */
1296 sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
1297 if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
1298 /* External MII needs echo disable if half duplex. */
1299 if ((IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) != 0)
1300 /* turn on full duplex LED */
1301 v |= GEM_MAC_XIF_FDPLX_LED;
1302 else
1303 /* half duplex -- disable echo */
1304 v |= GEM_MAC_XIF_ECHO_DISABL;
1305
1306 switch (IFM_SUBTYPE(sc->sc_mii.mii_media_active)) {
1307 case IFM_1000_T: /* Gigabit using GMII interface */
1308 v |= GEM_MAC_XIF_GMII_MODE;
1309 break;
1310 default:
1311 v &= ~GEM_MAC_XIF_GMII_MODE;
1312 }
1313 } else
1314 /* Internal MII needs buf enable */
1315 v |= GEM_MAC_XIF_MII_BUF_ENA;
1316 bus_space_write_4(t, mac, GEM_MAC_XIF_CONFIG, v);
1317 }
1318
1319 int
gem_mediachange(ifp)1320 gem_mediachange(ifp)
1321 struct ifnet *ifp;
1322 {
1323 struct gem_softc *sc = ifp->if_softc;
1324 struct mii_data *mii = &sc->sc_mii;
1325
1326 if (mii->mii_instance) {
1327 struct mii_softc *miisc;
1328 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1329 miisc = LIST_NEXT(miisc, mii_list))
1330 mii_phy_reset(miisc);
1331 }
1332
1333 return (mii_mediachg(&sc->sc_mii));
1334 }
1335
1336 void
gem_mediastatus(ifp,ifmr)1337 gem_mediastatus(ifp, ifmr)
1338 struct ifnet *ifp;
1339 struct ifmediareq *ifmr;
1340 {
1341 struct gem_softc *sc = ifp->if_softc;
1342
1343 mii_pollstat(&sc->sc_mii);
1344 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1345 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1346 }
1347
1348 /*
1349 * Process an ioctl request.
1350 */
1351 int
gem_ioctl(ifp,cmd,data)1352 gem_ioctl(ifp, cmd, data)
1353 struct ifnet *ifp;
1354 u_long cmd;
1355 caddr_t data;
1356 {
1357 struct gem_softc *sc = ifp->if_softc;
1358 struct ifaddr *ifa = (struct ifaddr *)data;
1359 struct ifreq *ifr = (struct ifreq *)data;
1360 int s, error = 0;
1361
1362 s = splimp();
1363
1364 if ((error = ether_ioctl(ifp, &sc->sc_arpcom, cmd, data)) > 0) {
1365 splx(s);
1366 return (error);
1367 }
1368
1369 switch (cmd) {
1370
1371 case SIOCSIFADDR:
1372 ifp->if_flags |= IFF_UP;
1373
1374 switch (ifa->ifa_addr->sa_family) {
1375 #ifdef INET
1376 case AF_INET:
1377 gem_init(ifp);
1378 arp_ifinit(&sc->sc_arpcom, ifa);
1379 break;
1380 #endif
1381 #ifdef NS
1382 case AF_NS:
1383 {
1384 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr;
1385
1386 if (ns_nullhost(*ina))
1387 ina->x_host =
1388 *(union ns_host *)LLADDR(ifp->if_sadl);
1389 else {
1390 memcpy(LLADDR(ifp->if_sadl),
1391 ina->x_host.c_host, sizeof(sc->sc_enaddr));
1392 }
1393 /* Set new address. */
1394 gem_init(ifp);
1395 break;
1396 }
1397 #endif
1398 default:
1399 gem_init(ifp);
1400 break;
1401 }
1402 break;
1403
1404 case SIOCSIFFLAGS:
1405 if ((ifp->if_flags & IFF_UP) == 0 &&
1406 (ifp->if_flags & IFF_RUNNING) != 0) {
1407 /*
1408 * If interface is marked down and it is running, then
1409 * stop it.
1410 */
1411 gem_stop(ifp, 1);
1412 ifp->if_flags &= ~IFF_RUNNING;
1413 } else if ((ifp->if_flags & IFF_UP) != 0 &&
1414 (ifp->if_flags & IFF_RUNNING) == 0) {
1415 /*
1416 * If interface is marked up and it is stopped, then
1417 * start it.
1418 */
1419 gem_init(ifp);
1420 } else if ((ifp->if_flags & IFF_UP) != 0) {
1421 /*
1422 * Reset the interface to pick up changes in any other
1423 * flags that affect hardware registers.
1424 */
1425 /*gem_stop(sc);*/
1426 gem_init(ifp);
1427 }
1428 #ifdef HMEDEBUG
1429 sc->sc_debug = (ifp->if_flags & IFF_DEBUG) != 0 ? 1 : 0;
1430 #endif
1431 break;
1432
1433 case SIOCADDMULTI:
1434 case SIOCDELMULTI:
1435 error = (cmd == SIOCADDMULTI) ?
1436 ether_addmulti(ifr, &sc->sc_arpcom) :
1437 ether_delmulti(ifr, &sc->sc_arpcom);
1438
1439 if (error == ENETRESET) {
1440 /*
1441 * Multicast list has changed; set the hardware filter
1442 * accordingly.
1443 */
1444 gem_init(ifp);
1445 error = 0;
1446 }
1447 break;
1448
1449 case SIOCGIFMEDIA:
1450 case SIOCSIFMEDIA:
1451 error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd);
1452 break;
1453
1454 default:
1455 error = EINVAL;
1456 break;
1457 }
1458
1459 splx(s);
1460 return (error);
1461 }
1462
1463
1464 void
gem_shutdown(arg)1465 gem_shutdown(arg)
1466 void *arg;
1467 {
1468 struct gem_softc *sc = (struct gem_softc *)arg;
1469 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1470
1471 gem_stop(ifp, 1);
1472 }
1473
1474 /*
1475 * Set up the logical address filter.
1476 */
1477 void
gem_setladrf(sc)1478 gem_setladrf(sc)
1479 struct gem_softc *sc;
1480 {
1481 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1482 struct ether_multi *enm;
1483 struct ether_multistep step;
1484 struct arpcom *ac = &sc->sc_arpcom;
1485 bus_space_tag_t t = sc->sc_bustag;
1486 bus_space_handle_t h = sc->sc_h;
1487 u_int32_t crc, hash[16], v;
1488 int i;
1489
1490 /* Get current RX configuration */
1491 v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
1492
1493
1494 /*
1495 * Turn off promiscuous mode, promiscuous group mode (all multicast),
1496 * and hash filter. Depending on the case, the right bit will be
1497 * enabled.
1498 */
1499 v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
1500 GEM_MAC_RX_PROMISC_GRP);
1501
1502 if ((ifp->if_flags & IFF_PROMISC) != 0) {
1503 /* Turn on promiscuous mode */
1504 v |= GEM_MAC_RX_PROMISCUOUS;
1505 ifp->if_flags |= IFF_ALLMULTI;
1506 goto chipit;
1507 }
1508
1509 /*
1510 * Set up multicast address filter by passing all multicast addresses
1511 * through a crc generator, and then using the high order 8 bits as an
1512 * index into the 256 bit logical address filter. The high order 4
1513 * bits select the word, while the other 4 bits select the bit within
1514 * the word (where bit 0 is the MSB).
1515 */
1516
1517 /* Clear hash table */
1518 for (i = 0; i < 16; i++)
1519 hash[i] = 0;
1520
1521
1522 ETHER_FIRST_MULTI(step, ac, enm);
1523 while (enm != NULL) {
1524 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1525 /*
1526 * We must listen to a range of multicast addresses.
1527 * For now, just accept all multicasts, rather than
1528 * trying to set only those filter bits needed to match
1529 * the range. (At this time, the only use of address
1530 * ranges is for IP multicast routing, for which the
1531 * range is big enough to require all bits set.)
1532 * XXX use the addr filter for this
1533 */
1534 ifp->if_flags |= IFF_ALLMULTI;
1535 v |= GEM_MAC_RX_PROMISC_GRP;
1536 goto chipit;
1537 }
1538
1539 crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN);
1540
1541 /* Just want the 8 most significant bits. */
1542 crc >>= 24;
1543
1544 /* Set the corresponding bit in the filter. */
1545 hash[crc >> 4] |= 1 << (15 - (crc & 15));
1546
1547 ETHER_NEXT_MULTI(step, enm);
1548 }
1549
1550 v |= GEM_MAC_RX_HASH_FILTER;
1551 ifp->if_flags &= ~IFF_ALLMULTI;
1552
1553 /* Now load the hash table into the chip (if we are using it) */
1554 for (i = 0; i < 16; i++) {
1555 bus_space_write_4(t, h,
1556 GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
1557 hash[i]);
1558 }
1559
1560 chipit:
1561 bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
1562 }
1563
1564 int
gem_encap(sc,mhead,bixp)1565 gem_encap(sc, mhead, bixp)
1566 struct gem_softc *sc;
1567 struct mbuf *mhead;
1568 u_int32_t *bixp;
1569 {
1570 u_int64_t flags;
1571 u_int32_t cur, frag, i;
1572 bus_dmamap_t map;
1573
1574 cur = frag = *bixp;
1575 map = sc->sc_txd[cur].sd_map;
1576
1577 if (bus_dmamap_load_mbuf(sc->sc_dmatag, map, mhead,
1578 BUS_DMA_NOWAIT) != 0) {
1579 return (ENOBUFS);
1580 }
1581
1582 if ((sc->sc_tx_cnt + map->dm_nsegs) > (GEM_NTXDESC - 2)) {
1583 bus_dmamap_unload(sc->sc_dmatag, map);
1584 return (ENOBUFS);
1585 }
1586
1587 bus_dmamap_sync(sc->sc_dmatag, map, 0, map->dm_mapsize,
1588 BUS_DMASYNC_PREWRITE);
1589
1590 for (i = 0; i < map->dm_nsegs; i++) {
1591 sc->sc_txdescs[frag].gd_addr =
1592 GEM_DMA_WRITE(sc, map->dm_segs[i].ds_addr);
1593 flags = (map->dm_segs[i].ds_len & GEM_TD_BUFSIZE) |
1594 (i == 0 ? GEM_TD_START_OF_PACKET : 0) |
1595 ((i == (map->dm_nsegs - 1)) ? GEM_TD_END_OF_PACKET : 0);
1596 sc->sc_txdescs[frag].gd_flags = GEM_DMA_WRITE(sc, flags);
1597 bus_dmamap_sync(sc->sc_dmatag, sc->sc_cddmamap,
1598 GEM_CDTXOFF(frag), sizeof(struct gem_desc),
1599 BUS_DMASYNC_PREWRITE);
1600 cur = frag;
1601 if (++frag == GEM_NTXDESC)
1602 frag = 0;
1603 }
1604
1605 sc->sc_tx_cnt += map->dm_nsegs;
1606 sc->sc_txd[*bixp].sd_map = sc->sc_txd[cur].sd_map;
1607 sc->sc_txd[cur].sd_map = map;
1608 sc->sc_txd[cur].sd_mbuf = mhead;
1609
1610 bus_space_write_4(sc->sc_bustag, sc->sc_h, GEM_TX_KICK, frag);
1611
1612 *bixp = frag;
1613
1614 /* sync descriptors */
1615
1616 return (0);
1617 }
1618
1619 /*
1620 * Transmit interrupt.
1621 */
1622 int
gem_tint(sc,status)1623 gem_tint(sc, status)
1624 struct gem_softc *sc;
1625 u_int32_t status;
1626 {
1627 struct ifnet *ifp = &sc->sc_arpcom.ac_if;
1628 struct gem_sxd *sd;
1629 u_int32_t cons, hwcons;
1630
1631 hwcons = status >> 19;
1632 cons = sc->sc_tx_cons;
1633 while (cons != hwcons) {
1634 sd = &sc->sc_txd[cons];
1635 if (sd->sd_mbuf != NULL) {
1636 bus_dmamap_sync(sc->sc_dmatag, sd->sd_map, 0,
1637 sd->sd_map->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1638 bus_dmamap_unload(sc->sc_dmatag, sd->sd_map);
1639 m_freem(sd->sd_mbuf);
1640 sd->sd_mbuf = NULL;
1641 }
1642 sc->sc_tx_cnt--;
1643 ifp->if_opackets++;
1644 if (++cons == GEM_NTXDESC)
1645 cons = 0;
1646 }
1647 sc->sc_tx_cons = cons;
1648
1649 gem_start(ifp);
1650
1651 if (sc->sc_tx_cnt == 0)
1652 ifp->if_timer = 0;
1653
1654 return (1);
1655 }
1656
1657 void
gem_start(ifp)1658 gem_start(ifp)
1659 struct ifnet *ifp;
1660 {
1661 struct gem_softc *sc = ifp->if_softc;
1662 struct mbuf *m;
1663 u_int32_t bix;
1664
1665 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1666 return;
1667
1668 bix = sc->sc_tx_prod;
1669 while (sc->sc_txd[bix].sd_mbuf == NULL) {
1670 IFQ_POLL(&ifp->if_snd, m);
1671 if (m == NULL)
1672 break;
1673
1674 #if NBPFILTER > 0
1675 /*
1676 * If BPF is listening on this interface, let it see the
1677 * packet before we commit it to the wire.
1678 */
1679 if (ifp->if_bpf)
1680 bpf_mtap(ifp->if_bpf, m);
1681 #endif
1682
1683 /*
1684 * Encapsulate this packet and start it going...
1685 * or fail...
1686 */
1687 if (gem_encap(sc, m, &bix)) {
1688 ifp->if_timer = 2;
1689 break;
1690 }
1691
1692 IFQ_DEQUEUE(&ifp->if_snd, m);
1693 ifp->if_timer = 5;
1694 }
1695
1696 sc->sc_tx_prod = bix;
1697 }
1698