1 /* $OpenBSD: gdtvar.h,v 1.9 2003/12/16 09:29:35 niklas Exp $ */
2
3 /*
4 * Copyright (c) 1999, 2000 Niklas Hallqvist. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * This driver would not have written if it was not for the hardware donations
29 * from both ICP-Vortex and �ko.neT. I want to thank them for their support.
30 */
31
32 #define GDT_CMD_RESERVE 4 /* Internal driver cmd reserve. */
33
34 #define GDT_IOCTL_DUMMY _IOWR('B', 32, struct gdt_dummy)
35 struct gdt_dummy {
36 void *cookie;
37 int x;
38 };
39
40 /* XXX Is this pragma necessary? */
41 #pragma pack(1)
42
43 #define GDT_SCRATCH_SZ 4096
44
45 #define GDT_IOCTL_GENERAL _IOWR('B', 33, gdt_ucmd_t) /* general IOCTL */
46 typedef struct gdt_ucmd {
47 void *cookie;
48 u_int16_t io_node;
49 u_int16_t service;
50 u_int32_t timeout;
51 u_int16_t status;
52 u_int32_t info;
53
54 u_int32_t BoardNode; /* board node (always 0) */
55 u_int32_t CommandIndex; /* command number */
56 u_int16_t OpCode; /* the command (READ,..) */
57 union {
58 struct {
59 u_int16_t DeviceNo; /* number of cache drive */
60 u_int32_t BlockNo; /* block number */
61 u_int32_t BlockCnt; /* block count */
62 void *DestAddr; /* data */
63 } cache; /* cache service cmd. str. */
64 struct {
65 u_int16_t param_size; /* size of p_param buffer */
66 u_int32_t subfunc; /* IOCTL function */
67 u_int32_t channel; /* device */
68 void *p_param; /* data */
69 } ioctl; /* IOCTL command structure */
70 struct {
71 u_int16_t reserved;
72 u_int32_t direction; /* data direction */
73 u_int32_t mdisc_time; /* disc. time (0: no timeout)*/
74 u_int32_t mcon_time; /* connect time(0: no to.) */
75 void *sdata; /* dest. addr. (if s/g: -1) */
76 u_int32_t sdlen; /* data length (bytes) */
77 u_int32_t clen; /* SCSI cmd. length(6,10,12) */
78 u_int8_t cmd[12]; /* SCSI command */
79 u_int8_t target; /* target ID */
80 u_int8_t lun; /* LUN */
81 u_int8_t bus; /* SCSI bus number */
82 u_int8_t priority; /* only 0 used */
83 u_int32_t sense_len; /* sense data length */
84 void *sense_data; /* sense data addr. */
85 u_int32_t link_p; /* linked cmds (not supp.) */
86 } raw; /* raw service cmd. struct. */
87 } u;
88 u_int8_t data[GDT_SCRATCH_SZ];
89 int complete_flag;
90 TAILQ_ENTRY(gdt_ucmd) links;
91 } gdt_ucmd_t;
92
93 #define GDT_IOCTL_DRVERS _IOWR('B', 34, int) /* get driver version */
94 typedef struct gdt_drvers {
95 void *cookie;
96 int vers;
97 } gdt_drvers_t;
98
99 #define GDT_IOCTL_CTRTYPE _IOR('B', 35, gdt_ctrt_t) /* get ctr. type */
100 typedef struct gdt_ctrt {
101 void *cookie;
102 u_int16_t io_node;
103 u_int16_t oem_id;
104 u_int16_t type;
105 u_int32_t info;
106 u_int8_t access;
107 u_int8_t remote;
108 u_int16_t ext_type;
109 u_int16_t device_id;
110 u_int16_t sub_device_id;
111 } gdt_ctrt_t;
112
113 #define GDT_IOCTL_OSVERS _IOR('B', 36, gdt_osv_t) /* get OS version */
114 typedef struct gdt_osv {
115 void *cookie;
116 u_int8_t oscode;
117 u_int8_t version;
118 u_int8_t subversion;
119 u_int16_t revision;
120 char name[64];
121 } gdt_osv_t;
122
123 #define GDT_IOCTL_CTRCNT _IOR('B', 37, int) /* get ctr. count */
124 typedef struct gdt_ctrcnt {
125 void *cookie;
126 int cnt;
127 } gdt_ctrcnt_t;
128
129 #define GDT_IOCTL_EVENT _IOWR('B', 38, gdt_event_t) /* get event */
130
131 typedef struct {
132 u_int16_t size; /* size of structure */
133 union {
134 char stream[16];
135 struct {
136 u_int16_t ionode;
137 u_int16_t service;
138 u_int32_t index;
139 } driver;
140 struct {
141 u_int16_t ionode;
142 u_int16_t service;
143 u_int16_t status;
144 u_int32_t info;
145 u_int8_t scsi_coord[3];
146 } async;
147 struct {
148 u_int16_t ionode;
149 u_int16_t service;
150 u_int16_t status;
151 u_int32_t info;
152 u_int16_t hostdrive;
153 u_int8_t scsi_coord[3];
154 u_int8_t sense_key;
155 } sync;
156 struct {
157 u_int32_t l1, l2, l3, l4;
158 } test;
159 } eu;
160 u_int32_t severity;
161 u_int8_t event_string[256];
162 } gdt_evt_data;
163 #define GDT_ES_ASYNC 1
164 #define GDT_ES_DRIVER 2
165 #define GDT_ES_TEST 3
166 #define GDT_ES_SYNC 4
167
168 /* dvrevt structure */
169 typedef struct {
170 u_int32_t first_stamp;
171 u_int32_t last_stamp;
172 u_int16_t same_count;
173 u_int16_t event_source;
174 u_int16_t event_idx;
175 u_int8_t application;
176 u_int8_t reserved;
177 gdt_evt_data event_data;
178 } gdt_evt_str;
179
180 typedef struct gdt_event {
181 void *cookie;
182 int erase;
183 int handle;
184 gdt_evt_str dvr;
185 } gdt_event_t;
186
187 #define GDT_IOCTL_STATIST _IOR('B', 39, gdt_statist_t) /* get statistics */
188 typedef struct gdt_statist {
189 void *cookie;
190 u_int16_t io_count_act;
191 u_int16_t io_count_max;
192 u_int16_t req_queue_act;
193 u_int16_t req_queue_max;
194 u_int16_t cmd_index_act;
195 u_int16_t cmd_index_max;
196 u_int16_t sg_count_act;
197 u_int16_t sg_count_max;
198 } gdt_statist_t;
199
200 #pragma pack()
201
202 #ifdef _KERNEL
203
204 /* Debugging */
205 #ifdef GDT_DEBUG
206 #define GDT_DPRINTF(mask, args) if (gdt_debug & (mask)) printf args
207 #define GDT_D_INTR 0x01
208 #define GDT_D_MISC 0x02
209 #define GDT_D_CMD 0x04
210 #define GDT_D_QUEUE 0x08
211 #define GDT_D_IO 0x10
212 extern int gdt_debug;
213 #else
214 #define GDT_DPRINTF(mask, args)
215 #endif
216
217 /* Miscellaneous constants */
218 #define GDT_RETRIES 100000000 /* 100000 * 1us = 100s */
219 #define GDT_TIMEOUT 100000000 /* 100000 * 1us = 100s */
220 #define GDT_POLL_TIMEOUT 10000000 /* 10000 * 1us = 10s */
221 #define GDT_WATCH_TIMEOUT 10000 /* 10000 * 1ms = 10s */
222
223 /* Context structure for interrupt services */
224 struct gdt_intr_ctx {
225 u_int32_t info, info2;
226 u_int16_t cmd_status, service;
227 u_int8_t istatus;
228 };
229
230 /*
231 * A command contol block, one for each corresponding command index of the
232 * controller.
233 */
234 struct gdt_ccb {
235 TAILQ_ENTRY(gdt_ccb) gc_chain;
236 struct scsi_xfer *gc_xs;
237 struct gdt_ucmd *gc_ucmd;
238 bus_dmamap_t gc_dmamap_xfer;
239 int gc_timeout;
240 u_int32_t gc_info;
241 u_int32_t gc_blockno;
242 u_int32_t gc_blockcnt;
243 u_int16_t gc_status;
244 u_int8_t gc_service;
245 u_int8_t gc_cmd_index;
246 u_int8_t gc_flags;
247 #define GDT_GCF_CMD_MASK 0x3
248 #define GDT_GCF_UNUSED 0
249 #define GDT_GCF_INTERNAL 1
250 #define GDT_GCF_SCREEN 2
251 #define GDT_GCF_SCSI 3
252 #define GDT_GCF_WATCHDOG 0x4
253 };
254
255 static __inline__ int gdt_ccb_set_cmd(struct gdt_ccb *, int);
256 static __inline__ int
gdt_ccb_set_cmd(ccb,flag)257 gdt_ccb_set_cmd(ccb, flag)
258 struct gdt_ccb *ccb;
259 int flag;
260 {
261 int rv = ccb->gc_flags & GDT_GCF_CMD_MASK;
262
263 ccb->gc_flags &= ~GDT_GCF_CMD_MASK;
264 ccb->gc_flags |= flag;
265 return (rv);
266 }
267
268 struct gdt_softc {
269 struct device sc_dev;
270 void *sc_ih;
271 struct scsi_link sc_link; /* Virtual SCSI bus for cache devs */
272 struct scsi_link *sc_raw_link; /* Raw SCSI busses */
273
274 int sc_class; /* Controller class */
275 #define GDT_ISA 0x01
276 #define GDT_EISA 0x02
277 #define GDT_PCI 0x03
278 #define GDT_PCINEW 0x04
279 #define GDT_MPR 0x05
280 #define GDT_CLASS_MASK 0x07
281 #define GDT_FC 0x10
282 #define GDT_CLASS(gdt) ((gdt)->sc_class & GDT_CLASS_MASK)
283
284 bus_space_tag_t sc_dpmemt;
285 bus_space_handle_t sc_dpmemh;
286 bus_addr_t sc_dpmembase;
287 bus_dma_tag_t sc_dmat;
288
289 /* XXX These could go into a class-dependent opaque struct instead */
290 bus_space_tag_t sc_iot;
291 bus_space_handle_t sc_ioh;
292 bus_addr_t sc_iobase;
293
294 u_int16_t sc_ic_all_size;
295
296 struct gdt_ccb sc_ccbs[GDT_MAXCMDS];
297 TAILQ_HEAD(, gdt_ccb) sc_free_ccb, sc_ccbq;
298 TAILQ_HEAD(, gdt_ucmd) sc_ucmdq;
299 LIST_HEAD(, scsi_xfer) sc_queue;
300 struct scsi_xfer *sc_queuelast;
301
302 int sc_ndevs;
303
304 u_int16_t sc_cmd_len;
305 u_int16_t sc_cmd_off;
306 u_int16_t sc_cmd_cnt;
307 u_int8_t sc_cmd[GDT_CMD_SZ];
308
309 u_int32_t sc_info;
310 u_int32_t sc_info2;
311 bus_dma_segment_t sc_scratch_seg;
312 caddr_t sc_scratch;
313 u_int16_t sc_status;
314
315 u_int8_t sc_bus_cnt;
316 u_int8_t sc_bus_id[GDT_MAXBUS];
317 u_int8_t sc_more_proc;
318
319 struct {
320 u_int8_t hd_present;
321 u_int8_t hd_is_logdrv;
322 u_int8_t hd_is_arraydrv;
323 u_int8_t hd_is_master;
324 u_int8_t hd_is_parity;
325 u_int8_t hd_is_hotfix;
326 u_int8_t hd_master_no;
327 u_int8_t hd_lock;
328 u_int8_t hd_heads;
329 u_int8_t hd_secs;
330 u_int16_t hd_devtype;
331 u_int32_t hd_size;
332 u_int8_t hd_ldr_no;
333 u_int8_t hd_rw_attribs;
334 u_int32_t hd_start_sec;
335 } sc_hdr[GDT_MAX_HDRIVES];
336
337 struct {
338 u_int32_t cp_version;
339 u_int16_t cp_state;
340 u_int16_t cp_strategy;
341 u_int16_t cp_write_back;
342 u_int16_t cp_block_size;
343 } sc_cpar;
344
345 struct {
346 u_int32_t bi_ser_no; /* serial number */
347 u_int8_t bi_oem_id[2]; /* u_int8_t OEM ID */
348 u_int16_t bi_ep_flags; /* eprom flags */
349 u_int32_t bi_proc_id; /* processor ID */
350 u_int32_t bi_memsize; /* memory size (bytes) */
351 u_int8_t bi_mem_banks; /* memory banks */
352 u_int8_t bi_chan_type; /* channel type */
353 u_int8_t bi_chan_count; /* channel count */
354 u_int8_t bi_rdongle_pres; /* dongle present */
355 u_int32_t bi_epr_fw_ver; /* (eprom) firmware ver */
356 u_int32_t bi_upd_fw_ver; /* (update) firmware ver */
357 u_int32_t bi_upd_revision; /* update revision */
358 char bi_type_string[16]; /* char controller name */
359 char bi_raid_string[16]; /* char RAID firmware name */
360 u_int8_t bi_update_pres; /* update present? */
361 u_int8_t bi_xor_pres; /* XOR engine present */
362 u_int8_t bi_prom_type; /* ROM type (eprom/flash) */
363 u_int8_t bi_prom_count; /* number of ROM devices */
364 u_int32_t bi_dup_pres; /* duplexing module pres? */
365 u_int32_t bi_chan_pres; /* # of exp. channels */
366 u_int32_t bi_mem_pres; /* memory expansion inst? */
367 u_int8_t bi_ft_bus_system; /* fault bus supported? */
368 u_int8_t bi_subtype_valid; /* board_subtype valid */
369 u_int8_t bi_board_subtype; /* subtype/hardware level */
370 u_int8_t bi_rampar_pres; /* RAM parity check hw? */
371 } sc_binfo;
372
373 struct {
374 u_int8_t bf_chaining; /* chaining supported */
375 u_int8_t bf_striping; /* striping (RAID-0) supported */
376 u_int8_t bf_mirroring; /* mirroring (RAID-1) supported */
377 u_int8_t bf_raid; /* RAID-4/5/10 supported */
378 } sc_bfeat;
379
380 u_int16_t sc_raw_feat;
381 u_int16_t sc_cache_feat;
382
383 void (*sc_copy_cmd)(struct gdt_softc *, struct gdt_ccb *);
384 u_int8_t (*sc_get_status)(struct gdt_softc *);
385 void (*sc_intr)(struct gdt_softc *, struct gdt_intr_ctx *);
386 void (*sc_release_event)(struct gdt_softc *, struct gdt_ccb *);
387 void (*sc_set_sema0)(struct gdt_softc *);
388 int (*sc_test_busy)(struct gdt_softc *);
389 };
390
391 /* XXX These have to become spinlocks in case of SMP */
392 #define GDT_LOCK_GDT(gdt) splbio()
393 #define GDT_UNLOCK_GDT(gdt, lock) splx(lock)
394 typedef int gdt_lock_t;
395
396 void gdtminphys(struct buf *);
397 int gdt_attach(struct gdt_softc *);
398 int gdt_intr(void *);
399
400 #ifdef __GNUC__
401 /* These all require correctly aligned buffers */
402 static __inline__ void gdt_enc16(u_int8_t *, u_int16_t);
403 static __inline__ void gdt_enc32(u_int8_t *, u_int32_t);
404 static __inline__ u_int16_t gdt_dec16(u_int8_t *);
405 static __inline__ u_int32_t gdt_dec32(u_int8_t *);
406
407 static __inline__ void
gdt_enc16(addr,value)408 gdt_enc16(addr, value)
409 u_int8_t *addr;
410 u_int16_t value;
411 {
412 *(u_int16_t *)addr = htole16(value);
413 }
414
415 static __inline__ void
gdt_enc32(addr,value)416 gdt_enc32(addr, value)
417 u_int8_t *addr;
418 u_int32_t value;
419 {
420 *(u_int32_t *)addr = htole32(value);
421 }
422
423 static __inline__ u_int16_t
gdt_dec16(addr)424 gdt_dec16(addr)
425 u_int8_t *addr;
426 {
427 return letoh16(*(u_int16_t *)addr);
428 }
429
430 static __inline__ u_int32_t
gdt_dec32(addr)431 gdt_dec32(addr)
432 u_int8_t *addr;
433 {
434 return letoh32(*(u_int32_t *)addr);
435 }
436 #endif
437
438 #if defined(__alpha__)
439 /* XXX XXX NEED REAL DMA MAPPING SUPPORT XXX XXX */
440 #undef vtophys
441 #define vtophys(va) alpha_XXX_dmamap((vm_offset_t)(va))
442 #endif
443
444 extern u_int8_t gdt_polling;
445
446 #endif
447