1 /* $OpenBSD: fxpreg.h,v 1.11 2006/03/04 03:48:37 brad Exp $ */ 2 3 /* 4 * Copyright (c) 1995, David Greenman 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD: if_fxpreg.h,v 1.13 1998/06/08 09:47:46 bde Exp $ 30 */ 31 32 #define FXP_VENDORID_INTEL 0x8086 33 #define FXP_DEVICEID_i82557 0x1229 34 35 #define FXP_PCI_MMBA 0x10 36 #define FXP_PCI_IOBA 0x14 37 38 /* 39 * Control/status registers. 40 */ 41 #define FXP_CSR_SCB_RUSCUS 0 /* scb_rus/scb_cus (1 byte) */ 42 #define FXP_CSR_SCB_STATACK 1 /* scb_statack (1 byte) */ 43 #define FXP_CSR_SCB_COMMAND 2 /* scb_command (1 byte) */ 44 #define FXP_CSR_SCB_INTRCNTL 3 /* scb_intrcntl (1 byte) */ 45 #define FXP_CSR_SCB_GENERAL 4 /* scb_general (4 bytes) */ 46 #define FXP_CSR_PORT 8 /* port (4 bytes) */ 47 #define FXP_CSR_FLASHCONTROL 12 /* flash control (2 bytes) */ 48 #define FXP_CSR_EEPROMCONTROL 14 /* eeprom control (2 bytes) */ 49 #define FXP_CSR_MDICONTROL 16 /* mdi control (4 bytes) */ 50 51 /* 52 * FOR REFERENCE ONLY, the old definition of FXP_CSR_SCB_RUSCUS: 53 * 54 * volatile u_int8_t :2, 55 * scb_rus:4, 56 * scb_cus:2; 57 */ 58 59 #define FXP_PORT_SOFTWARE_RESET 0 60 #define FXP_PORT_SELFTEST 1 61 #define FXP_PORT_SELECTIVE_RESET 2 62 #define FXP_PORT_DUMP 3 63 64 #define FXP_SCB_RUS_IDLE 0 65 #define FXP_SCB_RUS_SUSPENDED 1 66 #define FXP_SCB_RUS_NORESOURCES 2 67 #define FXP_SCB_RUS_READY 4 68 #define FXP_SCB_RUS_SUSP_NORBDS 9 69 #define FXP_SCB_RUS_NORES_NORBDS 10 70 #define FXP_SCB_RUS_READY_NORBDS 12 71 72 #define FXP_SCB_CUS_IDLE 0 73 #define FXP_SCB_CUS_SUSPENDED 1 74 #define FXP_SCB_CUS_ACTIVE 2 75 76 #define FXP_SCB_STATACK_SWI 0x04 77 #define FXP_SCB_STATACK_MDI 0x08 78 #define FXP_SCB_STATACK_RNR 0x10 79 #define FXP_SCB_STATACK_CNA 0x20 80 #define FXP_SCB_STATACK_FR 0x40 81 #define FXP_SCB_STATACK_CXTNO 0x80 82 83 #define FXP_SCB_COMMAND_CU_NOP 0x00 84 #define FXP_SCB_COMMAND_CU_START 0x10 85 #define FXP_SCB_COMMAND_CU_RESUME 0x20 86 #define FXP_SCB_COMMAND_CU_DUMP_ADR 0x40 87 #define FXP_SCB_COMMAND_CU_DUMP 0x50 88 #define FXP_SCB_COMMAND_CU_BASE 0x60 89 #define FXP_SCB_COMMAND_CU_DUMPRESET 0x70 90 91 #define FXP_SCB_COMMAND_RU_NOP 0 92 #define FXP_SCB_COMMAND_RU_START 1 93 #define FXP_SCB_COMMAND_RU_RESUME 2 94 #define FXP_SCB_COMMAND_RU_ABORT 4 95 #define FXP_SCB_COMMAND_RU_LOADHDS 5 96 #define FXP_SCB_COMMAND_RU_BASE 6 97 #define FXP_SCB_COMMAND_RU_RBDRESUME 7 98 99 #define FXP_SCB_INTRCNTL_REQUEST_SWI 0x02 100 101 /* 102 * Command block definitions 103 */ 104 struct fxp_cb_nop { 105 void *fill[2]; 106 volatile u_int16_t cb_status; 107 volatile u_int16_t cb_command; 108 volatile u_int32_t link_addr; 109 }; 110 struct fxp_cb_ias { 111 volatile u_int16_t cb_status; 112 volatile u_int16_t cb_command; 113 volatile u_int32_t link_addr; 114 volatile u_int8_t macaddr[6]; 115 }; 116 /* I hate bit-fields :-( */ /* SO WHY USE IT, EH? */ 117 118 /* 119 * Bitfields cleaned out since it is not endian compatible. OK 120 * you can define a big endian structure but can never be 100% safe... 121 * 122 * ANY PROGRAMER TRYING THE STUNT WITH BITFIELDS IN A DEVICE DRIVER 123 * SHOULD BE PUT UP AGAINST THE WALL, BLINDFOLDED AND SHOT! 124 */ 125 struct fxp_cb_config { 126 volatile u_int16_t cb_status; 127 volatile u_int16_t cb_command; 128 volatile u_int32_t link_addr; 129 volatile u_int8_t byte_count; 130 volatile u_int8_t fifo_limit; 131 volatile u_int8_t adaptive_ifs; 132 volatile u_int8_t ctrl0; 133 volatile u_int8_t rx_dma_bytecount; 134 volatile u_int8_t tx_dma_bytecount; 135 volatile u_int8_t ctrl1; 136 volatile u_int8_t ctrl2; 137 volatile u_int8_t mediatype; 138 volatile u_int8_t void2; 139 volatile u_int8_t ctrl3; 140 volatile u_int8_t linear_priority; 141 volatile u_int8_t interfrm_spacing; 142 volatile u_int8_t void3; 143 volatile u_int8_t void4; 144 volatile u_int8_t promiscuous; 145 volatile u_int8_t void5; 146 volatile u_int8_t void6; 147 volatile u_int8_t stripping; 148 volatile u_int8_t fdx_pin; 149 volatile u_int8_t multi_ia; 150 volatile u_int8_t mc_all; 151 }; 152 153 #define MAXMCADDR 80 154 struct fxp_cb_mcs { 155 volatile u_int16_t cb_status; 156 volatile u_int16_t cb_command; 157 volatile u_int32_t link_addr; 158 volatile u_int16_t mc_cnt; 159 volatile u_int8_t mc_addr[MAXMCADDR][6]; 160 }; 161 162 /* 163 * Number of DMA segments in a TxCB. Note that this is carefully 164 * chosen to make the total struct size an even power of two. It's 165 * critical that no TxCB be split across a page boundary since 166 * no attempt is made to allocate physically contiguous memory. 167 */ 168 #define SZ_TXCB 16 /* TX control block head size = 4 32 bit words */ 169 #define SZ_TBD 8 /* Fragment ptr/size block size */ 170 #define FXP_NTXSEG ((256 - SZ_TXCB) / SZ_TBD) 171 172 struct fxp_tbd { 173 volatile u_int32_t tb_addr; 174 volatile u_int32_t tb_size; 175 }; 176 struct fxp_cb_tx { 177 volatile u_int16_t cb_status; 178 volatile u_int16_t cb_command; 179 volatile u_int32_t link_addr; 180 volatile u_int32_t tbd_array_addr; 181 volatile u_int16_t byte_count; 182 volatile u_int8_t tx_threshold; 183 volatile u_int8_t tbd_number; 184 /* 185 * The following isn't actually part of the TxCB. 186 */ 187 volatile struct fxp_tbd tbd[FXP_NTXSEG]; 188 }; 189 190 /* 191 * Control Block (CB) definitions 192 */ 193 194 /* status */ 195 #define FXP_CB_STATUS_OK 0x2000 196 #define FXP_CB_STATUS_C 0x8000 197 /* commands */ 198 #define FXP_CB_COMMAND_NOP 0x0 199 #define FXP_CB_COMMAND_IAS 0x1 200 #define FXP_CB_COMMAND_CONFIG 0x2 201 #define FXP_CB_COMMAND_MCAS 0x3 202 #define FXP_CB_COMMAND_XMIT 0x4 203 #define FXP_CB_COMMAND_UCODE 0x5 204 #define FXP_CB_COMMAND_DUMP 0x6 205 #define FXP_CB_COMMAND_DIAG 0x7 206 /* command flags */ 207 #define FXP_CB_COMMAND_SF 0x0008 /* simple/flexible mode */ 208 #define FXP_CB_COMMAND_I 0x2000 /* generate interrupt on completion */ 209 #define FXP_CB_COMMAND_S 0x4000 /* suspend on completion */ 210 #define FXP_CB_COMMAND_EL 0x8000 /* end of list */ 211 212 /* 213 * RFA definitions 214 */ 215 216 struct fxp_rfa { 217 volatile u_int16_t rfa_status; 218 volatile u_int16_t rfa_control; 219 volatile u_int32_t link_addr; 220 volatile u_int32_t rbd_addr; 221 volatile u_int16_t actual_size; 222 volatile u_int16_t size; 223 }; 224 #define FXP_RFA_STATUS_RCOL 0x0001 /* receive collision */ 225 #define FXP_RFA_STATUS_IAMATCH 0x0002 /* 0 = matches station address */ 226 #define FXP_RFA_STATUS_S4 0x0010 /* receive error from PHY */ 227 #define FXP_RFA_STATUS_TL 0x0020 /* type/length */ 228 #define FXP_RFA_STATUS_FTS 0x0080 /* frame too short */ 229 #define FXP_RFA_STATUS_OVERRUN 0x0100 /* DMA overrun */ 230 #define FXP_RFA_STATUS_RNR 0x0200 /* RU not ready */ 231 #define FXP_RFA_STATUS_ALIGN 0x0400 /* alignment error */ 232 #define FXP_RFA_STATUS_CRC 0x0800 /* CRC error */ 233 #define FXP_RFA_STATUS_OK 0x2000 /* packet received okay */ 234 #define FXP_RFA_STATUS_C 0x8000 /* packet reception complete */ 235 #define FXP_RFA_CONTROL_SF 0x08 /* simple/flexible memory mode */ 236 #define FXP_RFA_CONTROL_H 0x10 /* header RFD */ 237 #define FXP_RFA_CONTROL_S 0x4000 /* suspend after reception */ 238 #define FXP_RFA_CONTROL_EL 0x8000 /* end of list */ 239 240 /* 241 * Statistics dump area definitions 242 */ 243 struct fxp_stats { 244 volatile u_int32_t tx_good; 245 volatile u_int32_t tx_maxcols; 246 volatile u_int32_t tx_latecols; 247 volatile u_int32_t tx_underruns; 248 volatile u_int32_t tx_lostcrs; 249 volatile u_int32_t tx_deffered; 250 volatile u_int32_t tx_single_collisions; 251 volatile u_int32_t tx_multiple_collisions; 252 volatile u_int32_t tx_total_collisions; 253 volatile u_int32_t rx_good; 254 volatile u_int32_t rx_crc_errors; 255 volatile u_int32_t rx_alignment_errors; 256 volatile u_int32_t rx_rnr_errors; 257 volatile u_int32_t rx_overrun_errors; 258 volatile u_int32_t rx_cdt_errors; 259 volatile u_int32_t rx_shortframes; 260 volatile u_int32_t completion_status; 261 }; 262 #define FXP_STATS_DUMP_COMPLETE 0xa005 263 #define FXP_STATS_DR_COMPLETE 0xa007 264 265 /* 266 * Serial EEPROM control register bits 267 */ 268 /* shift clock */ 269 #define FXP_EEPROM_EESK 0x01 270 /* chip select */ 271 #define FXP_EEPROM_EECS 0x02 272 /* data in */ 273 #define FXP_EEPROM_EEDI 0x04 274 /* data out */ 275 #define FXP_EEPROM_EEDO 0x08 276 277 /* 278 * Serial EEPROM opcodes, including start bit 279 */ 280 #define FXP_EEPROM_OPC_ERASE 0x4 281 #define FXP_EEPROM_OPC_WRITE 0x5 282 #define FXP_EEPROM_OPC_READ 0x6 283 284 /* 285 * Management Data Interface opcodes 286 */ 287 #define FXP_MDI_WRITE 0x1 288 #define FXP_MDI_READ 0x2 289 290 /* 291 * PHY device types 292 */ 293 #define FXP_PHY_DEVICE_MASK 0x3f00 294 #define FXP_PHY_SERIAL_ONLY 0x8000 295 #define FXP_PHY_NONE 0 296 #define FXP_PHY_82553A 1 297 #define FXP_PHY_82553C 2 298 #define FXP_PHY_82503 3 299 #define FXP_PHY_DP83840 4 300 #define FXP_PHY_80C240 5 301 #define FXP_PHY_80C24 6 302 #define FXP_PHY_82555 7 303 #define FXP_PHY_DP83840A 10 304 #define FXP_PHY_82555B 11 305 306 /* 307 * PHY BMCR Basic Mode Control Register 308 */ 309 #define FXP_PHY_BMCR 0x0 310 #define FXP_PHY_BMCR_FULLDUPLEX 0x0100 311 #define FXP_PHY_BMCR_AUTOEN 0x1000 312 #define FXP_PHY_BMCR_SPEED_100M 0x2000 313 314 /* 315 * DP84830 PHY, PCS Configuration Register 316 */ 317 #define FXP_DP83840_PCR 0x17 318 #define FXP_DP83840_PCR_LED4_MODE 0x0002 /* 1 = LED4 always indicates full duplex */ 319 #define FXP_DP83840_PCR_F_CONNECT 0x0020 /* 1 = force link disconnect function bypass */ 320 #define FXP_DP83840_PCR_BIT8 0x0100 321 #define FXP_DP83840_PCR_BIT10 0x0400 322 323 #define MAXUCODESIZE 192 324 struct fxp_cb_ucode { 325 volatile u_int16_t cb_status; 326 volatile u_int16_t cb_command; 327 volatile u_int32_t link_addr; 328 volatile u_int32_t ucode[MAXUCODESIZE]; 329 }; 330 331 /* 332 * Chip revision values. 333 */ 334 #define FXP_REV_82557 1 /* catchall 82557 */ 335 #define FXP_REV_82558_A4 4 /* 82558 A4 stepping */ 336 #define FXP_REV_82558_B0 5 /* 82558 B0 stepping */ 337 #define FXP_REV_82559_A0 8 /* 82559 A0 stepping */ 338 #define FXP_REV_82559S_A 9 /* 82559S A stepping */ 339 #define FXP_REV_82550 12 340 #define FXP_REV_82550_C 13 /* 82550 C stepping */ 341 #define FXP_REV_82551_E 14 /* 82551 */ 342 #define FXP_REV_82551_F 15 /* 82551 */ 343 #define FXP_REV_82551_10 16 /* 82551 */ 344